The Schematics drawing File name on each sheet Minimum number of characters in values Consistent character size for readability Schematics printed at a readable scale All components have reference designators Every component has a value Every component has a part name (except resistors, capacitors etc.) Every net has a name Special information for a component Polarized components connections checked Power and ground pins shown (preferred) or listed for each component Check hidden power and ground connections (they are the source for many troubles) Title block completed for each sheet All test points and jumpers are marked clearly and have reference designator Check that all required options appear clearly on the drawing Check connectors and on-board elements pin out Ensure socket pins are marked if in use Outside world I/O lines filtered for RFI Outside world I/O lines protected against static discharge Bypass cap for each IC Voltage ratings of components checked Pullups on all open collector outputs Sufficient power rails for analog circuits Ability to disable watchdog timer for testing and diagnostics and emulation Sufficient capacitance on low dropout voltage regulators Setup, hold, access times for data and address busses Check the data sheet fine print and apnotes for weird IC behaviors Check maximum power dissipation at worst-case operating temperatures Check time delays and slew rates of opamps used as comparators Estimate total worst case power supply current Check pin numbers of all custom-generated parts Ensure resistors are operating within their specified power range plus safety factor Resistor power ratings derated for elevated ambient temperatures Potentiometers should increase controlled quantity clockwise Part obsolescence review All no-connect pins on IC’s should be labelled NC Text should not overlap wire or symbol graphics on schematics Off board connectors identify all signals even if not used on this design Component choice and pin out Mating connectors on different assemblies checked for same pin out Oscillators checked for reliable startup Automotive powered devices must withstand 60 to 100 volt surges Check for voltage transients and high voltages on FET gates Ensure resistors are operating within their specified power range plus safety factor Resistor power ratings derates for elevated ambient temperatures Electrolytic/tantalum capacitor temperature/voltage derating sufficient for MTBF Low impedance sources driving tantalum caps can cause premature failure Check PLD pin outs each time a PLD is recompiled Recommended component reference designators (add/remove at your convenience): R fixed resistor RN resistor network RV variable resistor RL, K relays C capacitor (fixed or variable) L inductor, choke Q transistor, FET, SCR, TRIAC D diode, rectifier, Zener, varicap, LED VR voltage regulator U integrated circuit J socket, jack (female) OR the half that is stationary P plug (male) OR the half that is attached to a cable/wire JP jumper (pins, trace, or wire) X crystal S, SW mechanical switch F fuse FL filter T transformer TP test point KB keyboard B, BT battery Electronic design consideration Connect spare gates inputs or unused inputs to GND or Vcc Outside world I/O lines filtered for RFI All outside world I/O lines protected against electro static discharge Bypass capacitor(s) for each IC Voltage ratings of components checked Ensure 3.3 volt parts are 5 volt tolerant where they interface Verify power sequencing requirements on 5 volt and 3.3 volt rails Each IC has known or controlled power-up state Electrolytic and tantalum capacitors checked for no reverse voltage Ground makes first and breaks last for hot insertion Check for input voltages applied with power off and CMOS latch-up possibilities Reset circuit design tested with fast and slow power supply rise and fall time Check reset behavior in power cycles before the circuit is fully operational Check all resets for possible reset loops, especially for hot swap operations Enable halting watchdog timer for testing and diagnostics Sufficient capacitance on low dropout voltage regulators Capacitance and fan out limits checked for busses Check maximum power dissipation at worst-case operating temperatures Estimate total worst case power supply current Avoid reverse base-emitter current/voltage on bipolar transistors EMI & Signal Integrity checks: Are there decoupling capacitors in all areas where there are connectors or via’s, to minimise EMI loop sizes of signals and their return ground path? If not do you need to add some? A power plane will act like the ground plane to high speed signals as long as the return signal can jump to the real ground plane through a nearby decoupling capacitor. Ensure all high speed signal traces run over their own ground / power planes. Do not allow say a digital signal to travel over the analog plane unless it is going to a device in that area and in which case follow the devices digital ground trace to minimise the loop and therefore noise. If there are any slots or gaps in the Gnd / Power planes, ensure no high speed signals run over them (to avoid the return path having to loop round, creating EMI problems). For high speed signals minimise track stubs (to below the critical length – ideally < 6.5mm, no more than 12mm for a 1ns rise time signal). Ideally high speed connectors should have the ground plane getting through between pins to avoid signal return paths having to go round the connector to a ground pin on it. Differential pair tracks are as close together as possible, or spaced based on impedance calculation? Do any high speed signals need termination? This can be to VCC or Gnd and ideally should be at end of bus after the last receiving device. A good value is typically 50ohm, but anywhere from 30 – 100ohms is often fine. Should ideally match the impedance of the track. Add test points for important buses and connections to tight SMD chips so its easy to attach a wire or scope probe. Are power tracks big enough and do they have big enough via’s? Are there any very big through hole components such as elect capacitors? If so don’t connect to internal layers on multilayer designs in case they get knocked and the internal connection is damaged. Check connections into power planes on >2 layer boards are big enough (enough via’s and big enough tracks). Check all important IC power pins have good decoupling capacitor connections Check crystal connections are short Do you need to add manufacturer test points (pads) for voltage rails etc? Are there components that need copper plane heatsinking (voltage regulators, mosfets etc)? Do you need to separate earth tracks from other tracks to avoid static problems? Are all jumpers, connectors etc labelled on the silkscreen? Check all surface mount pads have tracks that come out of the end, not the side (i.e. no links between adjacent IC pads that will look like a short during inspection). Do you need to add fiducial marks for the pick and place machine? Are there nets that need their length equalised (e.g. fast differential connections such as Ethernet)? Add a hatch fill done on both sides connected to GND to improve EMC? These are a good general setting for the fill:- Track width: 0.3mm, Grid size: 0.6mm Create board outline on a mechanical layer Do a final design rule check Double check mounting positions will be OK in the equipment the PCB is fitted in. PCB Artwork Are there any antennas? Edit -> Copper Delete -> Open Trace Ends Are there any unused vias? Design -> Remove Unused Vias Are there any design rule errors you can't explain? Are there any connectivity errors at all? Does it look wrong? Look at the board for obvious stupidity like parts that have been eaten or moved. Are there bypass caps directly on the power rails of EVERY chip? Even the ones that don't look like ICs, like regulators? Are there filters directly on EVERY transistor gate/base? Are there filters directly on A/D converter pins? Are the traces wide enough? Especially power traces? Use power planes where possible, especially under processors Are the thermal reliefs as you intended? High-current components get no thermal relief, but also no solder mask! Otherwise it will be very difficult to solder. Make sure there's plenty of exposed copper on both sides of the board for those components. Everything else gets standard thermal reliefs, 10 mil or so is probably fine spoke width. Are all test points labeled? Is the board name printed on the silkscreen? Correct revision? Date? Is there sufficient distributed cap on the power rails? Are all isolation barriers wide enough? Are all high voltage clearances in place? Look particularly for traces under heat sinks tied to high voltage through a transistor tab. Also look for clearances to any mounting holes. Check all the layers. Are all footprints and pinouts correct? Re-check against data sheet. Is the silkscreen correct, showing reference designators, not values? Check the actual exported gerber. Are all user terminals marked with function, + -, other relevant information? Are all op-amp power rails connected? Hole diameter on drawing are finished sizes, after plating. Finished hole sizes are >=10 mils larger than lead Silkscreen legend text weight >=10 mils Pads >=15 mils larger than finished hole sizes Place thruhole components on 50 mil grid No silkscreen legend text over vias (if vias not soldermasked) or holes Soldermask does or does not cover vias All legend text reads in one or two directions Components labeled left-right, top-bottom Company logo in silkscreen legend Company logo in foil Copyright notice on PCB Date code on PCB PCB part number Assembly part number on PCB All polarized components point same way Components >=0.2″ from edge of PCB Ground planes where possible Test pad or test via on every net to allow in circuit test Test pads 200 mils from edge of board Mounting holes electrically isolated or not Mounting holes with or without islands Proper mounting hole clearance for hardware All polarized components checked No acute inside angles in foil Traces >= 20 mils from edge of PCB PCB revision on silkscreen legend Assembly revision blank on silkscreen legend Serial number blank on silkscreen legend Soldermask swell checked Thru hole drill tolerance noted Thru hole soldermask tolerance noted Thru hole route tolerance noted Thru hole silkscreen legend tolerance noted Drill legend shows all symbols and sizes Mounting holes matched 1:1 with mating parts Automated netlist check Manual netlist check Check netlist for nodes with only one connection CAD design rule check NC drill and photoplot file language format noted Tools on drill plot and NC drill file cross checked PCB thickness, material, copper weight noted Trace and space geometry noted Printed drill report sent with checkplots Printed aperture table sent with checkplots Photoplot files checked in file viewer Test coupon on PCB containing minimum geometry features Sufficient clearance for high voltage traces Component and trace keepout areas observed High frequency circuitry precautions observed Thermal reliefs for internal power layers Solder paste mask openings are proper size SMD component orientation arbitrary or consistent Ensure pin 1 interpretation and orientation consistent among all connectors of a given type on the board Clearance for emulator adapter or pod Standoffs on power resistors or other hot components Digital and analog signal commons joined at only one point EMI and RFI filtering as close as possible to exit and entry points in shielded areas Layout PCB so that any rework or repair of a component does not require removal of other components Extra connector and IC pins accessible on prototype boards, just in case Check all power and ground connections to ICs Provide ground test points, accessible and sized for scope ground clip Check hole diameters for odd components: rectangular pins, spring pins Check the orientation of all connectors using actual connector/cable Bypass capacitors located close to IC power pins All silkscreen text located to be readable when the board is populated All ICs have pin one clearly marked, visible even when chip is installed High pin count ICs and connectors have corner pins numbered for ease of location Silk screen tick marks for every 5th or 10th pin on high pin count ICs and connectors Verify that all series terminators are located near the source Place I/O drivers near where their signals leave the board High frequency crystal cases should be flush to the PCB and grounded Check for traces running under noisy or sensitive components Check IC pin count on layout vs schematic No vias under metal-film resistors and similar poorly insulated parts Check for traces which may be susceptible to solder bridging Maximize distances between features where possible Check for dead-end traces Check for power not shorted to ground Ensure schematic software did / did not separate Vcc from Vdd, Vss from GND as needed Provide multiple vias for high current and/or low impedance traces PCB has ground turrets, power rail test points, and test points for for important signals, all labeled Don't trust the auto-router. Testability Test points on PCBs for critical circuits, hard to reach nets Test pads for in-circuit or bed-of-nails functional testing Test pads on a regular grid Test procedure written for each test phase Special test arrangements and connectors for testing Maintainability Easy disassembly and reassembly Fuses accessible and labeled Self test mode Spare parts available Status LEDs on PCB Event logging of exceptional conditions Vibration tolerance of entire assembly and individual modules Surge current magnitude through semiconductors within rating Thermal cycling excursions internal to components and assemblies within acceptable limits Capacitors mounted below or away from heat-dissipating devices such as transformers Resistance and tolerance of entire product to static discharge via any path Safety Fuse and circuit breaker size and characteristics Ruse sizes marked near fuse holder Room to remove fuse without damaging other components Spare fuse storage Shock hazards Radiated energy warnings and shields Applicable standards checked Protection against liquids and foreign objects Documentation End-user instructions: unpacking, how to use, warranty, service, troubleshooting Service manual: troubleshooting procedures, parts lists, helpline info Design notes: why significant design decisions were made the way they were Other info that may be lost if designers depart the organization