(ExpressProject "HiSideSwTestBoard"
  (ProjectVersion "19981106")
  (ProjectType "PCB")
  (Folder "Design Resources"
    (Folder "Library"
      (File "C:\OrCAD\OrCAD_10.3\tools\capture\LIBRARY\capsym.olb"
        (Type "Schematic Library"))
      (File "C:\OrCAD\OrCAD_10.3\tools\capture\LIBRARY\Connector.olb"
        (Type "Schematic Library"))
      (File "C:\OrCAD\OrCAD_10.3\tools\capture\LIBRARY\Discrete.olb"
        (Type "Schematic Library")))
    (NoModify)
    (File ".\hisideswtestboard.dsn"
      (Type "Schematic Design"))
    (BuildFileAddedOrDeleted "x")
    (CompileFileAddedOrDeleted "x")
    (ANNOTATE_Scope "0")
    (ANNOTATE_Mode "1")
    (ANNOTATE_Action "0")
    (Annotate_Page_Order "0")
    (ANNOTATE_Reset_References_to_1 "FALSE")
    (ANNOTATE_No_Page_Number_Change "FALSE")
    (ANNOTATE_Property_Combine "{Value}{Source Package}{POWER_GROUP}")
    (ANNOTATE_IncludeNonPrimitive "FALSE")
    (DRC_Scope "0")
    (DRC_Action "0")
    (DRC_Create_Warnings "FALSE")
    (DRC_Check_Ports "FALSE")
    (DRC_Check_Off-Page_Connectors "FALSE")
    (DRC_Identical_References "TRUE")
    (DRC_Type_Mismatch "TRUE")
    (DRC_Report_Ports_and_Off-page_Connectors "FALSE")
    (DRC_SDT_Compatibility "FALSE")
    (DRC_Report_Off-grid_Objects "FALSE")
    (DRC_Check_Unconnected_Nets "TRUE")
    ([DRC0038] _Visible_unconnected_Power_Pins_are_connected_to_global_nets
       "FALSE")
    (DRC_Report_Netnames "FALSE")
    (DRC_View_Output "FALSE")
    (DRC_Report_File
       "X:\368000_DMO_AUV\SCHEMATICS\DCON\HISIDESWTESTBOARD\SCHPCB\HISIDESWTESTBOARD.DRC")
    (Netlist_TAB "3")
    (OTHER_Part_Value "{Value}")
    (OTHER_Netlist_File "HISIDESWTESTBOARD.NET")
    (OTHER_Netlist_File2 "HISIDESWTESTBOARD.CMP")
    (OTHER_View_Output "TRUE")
    (OTHER_View_Output2 "FALSE")
    (OTHER_Formatter "wirelist.dll")
    (OTHER_PCB_Footprint "{PCB Footprint}")
    (OTHER_Switch0 "FALSE")
    (OTHER_Switch1 "TRUE")
    (OTHER_Switch2 "FALSE")
    (OTHER_Switch3 "FALSE")
    (OTHER_Switch4 "FALSE")
    (OTHER_Switch5 "FALSE")
    (OTHER_Switch6 "FALSE")
    (LAYOUT_Netlist_File "HISIDESWTESTBOARD.MNL")
    (LAYOUT_PCB_Footprint "{PCB Footprint}")
    (FALSE)
    (LAYOUT_Units "0")
    ([DRC0038] _Visible_unconnected_Power_Pins_are_connected_to_global_nets
       "FALSE")
    (GATE_&_PIN_SWAP_Scope "0")
    (GATE_&_PIN_SWAP_File_Name
       "X:\368000_DMO_AUV\Schematics\DCON\HiSideSwTestBoard\SchPcb\HISIDESWTESTBOARD-7.SWP")
    (Backannotation_TAB "1"))
  (Folder "Outputs"
    (File ".\hisideswtestboard.drc"
      (Type "Report"))
    (File ".\hisideswtestboard.net"
      (Type "Report"))
    (File ".\hisideswtestboard.mnl"
      (Type "LAYOUT Netlist File")))
  (Folder "Referenced Projects")
  (PartMRUSelector)
  (GlobalState
    (FileView
      (Path "Design Resources")
      (Path "Design Resources" ".\hisideswtestboard.dsn")
      (Path "Design Resources" ".\hisideswtestboard.dsn" "SCHEMATIC1")
      (Path "Outputs")
      (Select "Design Resources" ".\hisideswtestboard.dsn" "SCHEMATIC1"
         "HI_SIDE_SW_TEST_BOARD"))
    (HierarchyView)
    (Doc
      (Type "COrCapturePMDoc")
      (Frame
        (Placement "44 2 3 -1 -1 -4 -23 0 200 0 557"))
      (Tab 0)))
  (MPSSessionName "drthom"))