TS 4100 pin mapping function pad: TS conn: FPGA Crossbar/Notes ---------------------------------------------------------------------------- CPU UARTS =========== UART7 TX LCD_DATA20 CN1 45 UART7 RX LCD_DATA21 CN1 42 UART7 CTS LCD_DATA04 CN1 32 UART7 RTS LCD_DATA05 CN1 34 UART6 TX LCD_DATA16 CN2 94 (UART C, 8->35) UART6 RX LCD_DATA17 CN2 96 (UART C, 31->12) UART6 CTS LCD_DATA06 CN1 38 UART6 RTS LCD_DATA07 CN1 40 UART5 TX CSI_MCLK CN2 34 UART5 RX CSI_PIXCLK CN2 32 UART5 CTS CSI_HSYNC CN2 70 UART5 RTS CSI_VSYNC CN2 72 UART4 TX UART5_TX CN2 90 UART4 RX UART5_RX CN2 92 UART4 CTS GPIO1_IO09 CN2 91 UART4 RTS GPIO1_IO08 CN1 57 UART3 TX UART4_TX CN2 86 (UART B, 7->34) UART3 RX UART4_RX CN2 88 (UART B, 30->11) UART3 CTS LCD_HSYNC CN1 51 UART3 RTS LCD_VSYNC CN1 53 UART2 TX UART3_TX CN2 78 (UART A, 5->33) UART2 RX UART3_RX CN2 80 (UART A, 29->9) UART2 CTS UART3_CTS CN1 74 (UART3_CTS -> DIO 32) UART2 RTS UART3_RTS CN1 76 (UART3_RTS -> DIO 31) (tested but UART2 RX line is connected to own level shifter on baseboard which breaks receiving) UART1 TX UART2_TX CN2 82 UART1 RX UART2_RX CN2 84 UART1 CTS UART2_CTS_B CN1 71 UART1 RTS UART2_RTS_B CN1 69 (tested but UART1 RX line is connected to own level shifter on baseboard which breaks receiving) UART0 TX UART1_TX CN2 93 UART0 RX UART1_RX CN2 95 SPI UARTs =========== UART CS0 CSI_DATA00 CN2 52 UART CS1 CSI_DATA01 CN2 55 UART CS2 CSI_DATA02 CN2 58 UART CS3 CSI_DATA03 CN2 60 UART CS4 CSI_DATA05 CN2 64 UART CS5 LCD_DATA09 CN2 99 [attached to IC on baseboard] UART CS6 LCD_DATA22 CN1 44 UART CS7 LCD_DATA23 CN1 46 UART IRQ0 LCD_DATA10 CN1 23 UART IRQ1 LCD_DATA11 CN1 25 UART IRQ2 LCD_DATA12 CN1 27 UART IRQ3 LCD_DATA13 CN1 31 UART IRQ4 LCD_DATA14 CN1 33 UART IRQ5 LCD_DATA15 CN1 35 UART IRQ6 LCD_DATA18 CN1 41 UART IRQ7 LCD_DATA19 CN1 43 ECSPI1 SCL CSI_DATA04 CN2 62 ECSPI1 MOSI CSI_DATA06 CN2 66 ECSPI1 MISO CSI_DATA07 CN2 68 Extra SPI =========== ECSPI3 SCL NAND_CE0_B CN2 71 [SPI_OB_CLK] ECSPI3 MOSI NAND_CE1_B CN2 67 [SPI_OB_MOSI] ECSPI3 MISO NAND_CLE CN2 69 [SPI_OB_MISO] VS100 CS UART1_CTS CN1 17 [SPARE_1] Misc GPIO =========== I2C3 SDA LCD_DATA00 CN2 30 [hooked up to FPGA, 0x28-0x2f] I2C3 SCL LCD_DATA01 CN2 28 [hooked up to FPGA, 0x28-0x2f] I2C4 SDA LCD_DATA0 2 CN1 28 I2C4 SCL LCD_DATA03 CN1 30 TS4100_GPS_1PPS LCD_DATA08 CN2 97 FPGA DIO ========== DISABLE_LOC_AIDS *DIO00 CN1 93 ENABLE_LOC_AIDS *DIO01 CN1 91 GPIO_ACOMMS_ON *DIO02 CN1 89 GPIO_ACOMMS_OFF *DIO03 CN1 87 PFON *DIO06 CN1 81 CAPGOOD *DIO07 CN1 79 TAILCONE_EN_CMD *DIO08 CN1 77 DVL_KFT_EN_CMD *DIO09 CN1 73 GULPERS_EN_CMD *DIO12 CN1 67 RESET_FRWV *DIO16 CN1 59 RESET_AHRS *DIO17 CN1 97 PDIS_UART0 *DIO24 CN1 90 PDIS_UART1 *DIO25 CN1 88 PDIS_UART2 *DIO26 CN1 86 PDIS_UART3 *DIO27 CN1 84 PDIS_UART4 *DIO39 CN1 58 PDIS_UART5 *DIO43 CN1 19 PDIS_UART7 *DIO45 CN1 37 PDIS_UART6 *DIO46 CN1 39 free IMX6 pins ================ (GPIO) LCD_CLK CN1 49 [10R res in series] (GPIO) LCD_ENABLE CN1 55 (JTAG, GPIO) JTAG_TDI CN2 36 (JTAG, GPIO) JTAG_TDO CN2 38 (JTAG, GPIO) JTAG_TCK CN2 42 [10k res to ground] (JTAG, GPIO) JTAG_TMS CN2 54 (JTAG, GPIO) JTAG_TRST_B CN2 40 free FPGA DIO: ================ (GPIO) *DIO04 CN1 85 (GPIO) *DIO05 CN1 83 (GPIO) *DIO13 CN1 65 (GPIO) *DIO14 CN1 63 (GPIO) *DIO15 CN1 61 (GPIO) *DIO18 CN1 99 (GPIO) *DIO19 CN1 100 (GPIO) *DIO20 CN1 98 (GPIO) *DIO21 CN1 96 (GPIO) *DIO22 CN1 94 (GPIO) *DIO23 CN1 92 (GPIO) *DIO28 CN1 82 (GPIO) *DIO29 CN1 80 (GPIO) *DIO30 CN1 78 (GPIO) *DIO33 CN1 72 (GPIO) *DIO34 CN1 70 (GPIO) *DIO35 CN1 68 (GPIO) *DIO36 CN1 66 (GPIO) *DIO37 CN1 64 (GPIO) *DIO38 CN1 60 (GPIO) *DIO41 CN1 24 (GPIO) *DIO42 CN1 26 (GPIO) *DIO44 CN1 21