Index of /internal/projects/368000_DMO_AUV/Schematics/MOTHERBOARD/SCH/2017/SchPcb/allegro/PowerBoard/Imported (1) POWERBOARDREV1.PrjPcb

[ICO]NameLast modifiedSizeDescription
[PARENTDIR]Parent Directory  -  
[ ]1PPS_FANOUT.SchDoc2017-12-18 17:22 334K 
[ ]BD_COMMS.SchDoc2017-12-11 14:49 34K 
[ ]BD_CONNECTORS.SchDoc2017-12-11 14:49 49K 
[ ]BD_PowerArchitecture.SchDoc2017-12-11 14:49 38K 
[ ]BD_TRIG_1PPS.SchDoc2017-12-11 14:48 55K 
[ ]COMMS_PWR_CHANNELS.SchDoc2017-12-11 14:48 21K 
[ ]DC_DC_3V3.SchDoc2017-12-18 17:22 134K 
[ ]DC_DC_5V.SchDoc2017-12-18 17:22 114K 
[ ]DC_DC_10V.SchDoc2017-12-18 17:22 57K 
[ ]DC_DC_12V.SchDoc2017-12-22 16:11 119K 
[ ]DROP_WEIGHT.SchDoc2017-12-18 17:22 73K 
[ ]ENV_SENSING.SchDoc2017-12-18 17:22 41K 
[DIR]History/2017-12-22 17:41 -  
[ ]OBSOLETE_BLK_DIAGRAM.SchDoc2017-12-11 14:48 83K 
[ ]POWERBOARDREV1.IntLib2017-12-15 13:02 94K 
[ ]POWERBOARDREV1.LOG2017-12-11 14:49 69K 
[ ]POWERBOARDREV1.PrjPcb2017-12-22 17:41 67K 
[ ]POWERBOARDREV1.PrjPcbStructure2017-12-22 16:11 53  
[ ]POWERBOARDREV1_Library.SchLib2017-12-11 14:49 341K 
[DIR]PSpice Models/2017-12-11 14:48 -  
[ ]PWR_CONNECTORS.SchDoc2017-12-22 17:08 309K 
[ ]PowerBoard.brd.PcbDoc2017-12-22 17:39 3.7M 
[ ]Powerboard_Misc.PcbLib2017-12-22 16:38 109K 
[ ]Powerboard_Misc.SchLib2017-12-20 08:30 6.0K 
[DIR]Project Logs for POWERBOARDREV1/2017-12-22 16:12 -  
[DIR]Project Outputs for POWERBOARDREV1/2017-12-22 11:48 -  
[ ]SCRATCH_PAD.SchDoc2017-12-11 14:48 15K 
[ ]STBY_PWR_ACOMMS.SchDoc2017-12-18 17:22 119K 
[ ]SWITCHED_BUS.SchDoc2017-12-22 11:04 612K 
[ ]SerialCables.SchDoc2017-12-11 14:48 26K 
[ ]TRIG_1PPS_ISO_POWER.SchDoc2017-12-18 17:22 201K 
[ ]TRIG_FANOUT_5V_BUS_DVL_.SchDoc2017-12-18 17:22 143K 
[ ]TRIG_FANOUT_F1.SchDoc2017-12-18 17:22 103K 
[ ]TRIG_FANOUT_F2.SchDoc2017-12-18 17:22 103K 
[ ]TRIG_FANOUT_F3.SchDoc2017-12-18 17:22 103K 
[ ]TRIG_FANOUT_F4.SchDoc2017-12-18 17:22 103K 
[ ]TRIG_uCNTLR_SPI_UART_7.SchDoc2017-12-18 17:22 97K 
[DIR]__Previews/2017-12-11 14:50 -  
[ ]uCHIP_XLP.SchDoc2017-12-18 17:22 205K 
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