\t (02:09:32) allegro 17.2 S028 Windows SPB 64-bit Edition
\t (02:09:32)     Journal start - Thu Dec 21 08:03:27 2017
\t (02:09:32)         Host=HINDENBURG User=drthom Pid=4056 CPUs=8
\t (02:09:32) CmdLine= C:\Cadence\SPB_17.2\tools\bin\allegro.exe
\t (02:09:32) 
\d (02:09:32) Design opened: S:/MOTHERBOARD/SCH/2017/SchPcb/backup/SUPERCAP.brd
\i (02:09:32) placementedit 
\i (02:09:40) color192 
\i (02:09:40) placementedit 
\i (02:09:55) QtSignal CVDLayerSplitter CVDLayersTree itemSelectionChanged Geometry "Package geometry"
\i (02:10:10) QtSignal CVDLayerSplitter CVDLayersTree itemSelectionChanged Components "Ref des"
\i (02:10:21) QtSignal CVDLayerSplitter CVDLayersTree itemSelectionChanged Stack-Up
\i (02:11:04) xsection 
\i (02:11:04) QtSignal CCMQtXSectionDlg m_dialogsTab currentChanged Info
\i (02:11:14) setwindow cmgr
\i (02:11:14) cm create Layer ( Design "SUPERCAP" ) 6 Dielectric
\i (02:11:14) cm create Layer ( Design "SUPERCAP" ) 7 Conductor LAYER_1
\i (02:11:21) cm create Layer ( Design "SUPERCAP" ) 9 Dielectric
\i (02:11:33) cm scope Design "SUPERCAP"
\i (02:11:33) cm putValue ( Layer "3" ) CDS_LAYER_NAME IN1 0
\i (02:11:36) cm putValue ( Layer "5" ) CDS_LAYER_NAME IN2 0
\i (02:11:47) cm putValue ( Layer "7" ) CDS_LAYER_NAME IN3 0
\i (02:11:50) cm create Layer ( Design "SUPERCAP" ) 9 Dielectric
\i (02:11:56) cm putValue ( Layer "9" ) CDS_LAYER_TYPE Conductor 0
\i (02:12:01) cm putValue ( Layer "9" ) CDS_LAYER_NAME IN4 0
\i (02:12:14) setwindow pcb
\i (02:12:14) QtFillin No
\i (02:12:16) QtSignal CCMQtXSectionDlg m_ApplyBtn clicked
\i (02:12:16) QtSignal CCMQtXSectionDlg m_dialogsTab currentChanged Info
\i (02:12:19) QtSignal CCMQtXSectionDlg m_OkBtn clicked
\i (02:12:19) setwindow cmgr
\i (02:12:19) cm exit
\i (02:12:19) setwindow pcb
\i (02:12:19) placementedit 
\i (02:12:31) color192 
\i (02:12:31) placementedit 
\i (02:12:38) pick grid -0.0439 1.1160
\t (02:12:38) last pick:  -0.0440 1.1160
\i (02:12:40) placementedit 
\i (02:12:42) drag_start grid -0.0439 1.0334
\i (02:12:44) drag_stop 1.5505 -0.1032
\i (02:12:45) prepopup 0.7838 0.5594
\i (02:12:48) pop dyn_option_select '@:@Place replicate create' 
\i (02:12:48) place replicate create 
\i (02:12:50) prepopup 0.3691 0.7353
\i (02:12:51) done 
\i (02:12:54) pick grid 0.5881 0.5288
\t (02:12:54) last pick:  0.5880 0.5290
\i (02:13:20) fillin "S:\MOTHERBOARD\SCH\2017\SchPcb\allegro\CpuBoard\allegro\SUPERCAP_IMPORT.mdd"
\w (02:13:20) WARNING(SPMHUT-48): Scaled value has been rounded off.
\w (02:13:20) WARNING(SPMHUT-48): Scaled value has been rounded off.
\w (02:13:20) WARNING(SPMHUT-48): Scaled value has been rounded off.
\i (02:13:20) placementedit 
\i (02:13:24) pick grid -0.0708 1.2686
\t (02:13:24) last pick:  -0.0710 1.2690
\i (02:13:26) save 
\i (02:13:28) fillin yes 
   (02:13:28) Loading consmgr.cxt 
   (02:13:28) Loading acns_formula.cxt 
\i (02:13:28) placementedit 
\i (02:13:40) open 
\i (02:13:45) fillin "menu_cancel"
\i (02:13:45) placementedit 
\i (02:13:49) opencd S:/MOTHERBOARD/SCH/2017/SchPcb/allegro/CpuBoard/allegro/CPUBOARDREV1.brd 
\t (02:13:49) Opening existing design...
\w (02:13:50) WARNING(SPMHDB-212): This design has functionality disabled due to the current product plus options selected. The following features are disabled: Via Z.  [help]
\i (02:13:52) fillin confirm
\i (02:13:52) trapsize 288
\t (02:13:52)     Journal end - Thu Dec 21 08:07:47 2017