MVC PS Spin notes: 1 Make the I2c pull ups 3.3k to match whats on the TS-4100 board 1 Add diode to coin cell battery See TPS3613-01 Data Sheet No info found on data sheet. Used UL safety guidelines ( diode in series w/ battery ) 1 U69 optoisolator is not needed. Remove R54, D112 and U69 Tie ACM+ to K4 -1 Tie ACM- to B Bus RTN 1 J6 is "vestigial" REMOVE CONNECTION FROM F6 TO NET "B_DROP_WT_PWR" Add a test point to F6 for future use 1 TVS_CDSOT23-T36C Diodes are unidirectional D84,D85,D86,D89,D90,D91,D92,D93,D94,D95,D96,D97,D98,D99,D100,D103 Footprint: sot_23_3 Digikey CDSOT23-T36CCT-ND Remove all and Replace with: 1 D84,D85,D86,D89,D90,D91,D92,D93,D94,D95,D96,D97,D98,D99,D100,D103 STS232360B151 Digikey: 283-STS232360B151CT-ND 1 Large common mode choke at SE corner, move it south Changed free wheeling diode to smaller package Moved FIL1 west 1 All VN750B5-E High Side Switches need a 100k 0603 pull-down across pins 1 and 2 U4 5 6 7 8 9 10 11 12 13 sch: U4 5 6 7 8 9 10 11 12 13 pcb: U4 5 6 7 8 9 10 11 12 13 1 U14 Temperature Sense for Hi Side Switches Remove resistors R124,125,126,127 connect U14 pin 4 directly to B_BUS GND 1 Add the Humidity and Pressure sensors to the power board One chip does Temp RH and Pressure: MS8602-02BA01 1 Add the memory chip to the power board I2C ADDRESS 1 Write protect: Add a connection to U18-7 ( RC3 ) to Memory Chip pin 7 ( WP ) 2AA512 memory chip Add a 100k pull up to B_3V3_BUS 1 Add ADC128 Vmon Chip for Isolated Power signals on the MVC_PS pcb as well as on the Trig_PPS_PC104 pcb Top resistor: 909k Signal Top R Vout B_3V3_ISO 8.87M 2.993 B_5V_SUPERCAP_FEED 1.07M 2.974 B_+12V_ISO 301k 2.985 B_BATT_12V_ISO 301k 2.985C RDF_PWR_FUSED (9V) 432k 2.899 1 I2C ADDRESS OF ISOLATED SIGNAL ADC 0x1F https://os.mbed.com/users/fblanc/code/ADC128D818/file/816284ff2a09/ADC128D818.h/ //Library for the ADC128D818 12 BIT ADC. enum ADC_MODE { ADC_MODE_0 = 0x00, ADC_MODE_1 = 0x01, ADC_MODE_2 = 0x02, ADC_MODE_3 = 0x03 }; enum ADC_ADDRESS { ADC_ADDRESS_LOW_LOW = 0x1D, ADC_ADDRESS_LOW_MID = 0x1E, ADC_ADDRESS_LOW_HIGH = 0x1F, ADC_ADDRESS_MID_LOW = 0x2D, ADC_ADDRESS_MID_MID = 0x2E, ADC_ADDRESS_MID_HIGH = 0x2F, ADC_ADDRESS_HIGH_LOW = 0x35, ADC_ADDRESS_HIGH_MID = 0x36, ADC_ADDRESS_HIGH_HIGH = 0x37 }; 1 ADC128 doc suggests input scaling voltage divider should use 10k to 100k for the "bottom" resistor 1 I2c Addresses: U23 is 0x37 ( not 0x1F ) ADC128 adc U119 is 0x69 ( not 0xD2 ) LTC2946 current sense U120 is 0x6F ( not 0xDE ) LTC2946 current sense 1 Latching relay K3 1 Latching relay K7 WAS: 5V_ISO on one side, other to GND thru a FET Try 3V version, drive coil w/ 3V3_BUS DSP2A-L2-DC3V DGK: 255-3719-ND NWK: 92T1093 1 RDF Backup Battery return tied to BUS_GND s/b GND_ISO 1 U138 Switching regulator for RDF Run off the Isolated Bus TSR2-2490 input 12-36 Volts 1 K5 RDF relay s/b a 9V relay, powered by net "RDF_9V" V23105A5006A201 DGK: PB1077-ND same pinout 1 U119 and U120 LTC2946 Current sensing chips ADIN pin 13 should tie to GND 1 Add RDF mount holes to the board in a place where it will not interfere with the CPU board components 1 J27 Avtrak 6 connector Delete connection from J27 pin 3 to R139 Add connection from TP149 to R139 0 Relabel the Silk Screen signal name for TP149 "AVTRAK_BURNWIRE_RELEASE" 1 Cut B_3V3_ISO supply to U123 pin 4, and blue wire B_3V3_BUS to pin 4 1 U21 INT_N pin 1 gets disconnected Remove R179 1 Change R9 to 200k 0 Net "RDF_PWR_FUSED" connect from TP144 thru Voltage Divider to XLP chip pin 7 Remove TP82 "RDF_PWR_FUSED" is either 6 or 9 V Vin Hi w TTL buffer 0.25 Vdd + 0.8 = 1.625 V 9V divider 909k / 453k = 2.993 V 6V divider 909k / 453k = 1.996 V THIS CAN'T BE RIGHT ... Net "RDF_PWR_FUSED" IS REFERRED TO "ISO_GND" "RDF_PWR_FUSED" is scaled and read out by the Isolated ADC. ? Shouldn't this be sufficient to ascertain status of " RDF_PWR_FUSED " ? 1 Blue Wire: scaled bus voltage, SCALED_BUS+ (TP129) to FUTURE_1 (TP81) on U18 Delete TP81 1 Add a RC low pass/de-bounce circuit before RB5; wouldn't cause any additional steady state current draw... L. Barker Probably wire the ground path if this is the case-cut the existing path and blue wire back to a more common Star node... H. Thomas On sheet 6, a text note near J16 Start Up Reed Switch says: " PINS 1 & 2 MAGNET IN MAKES CONNECTION; PIC RB5 GOES HIGH " Shouldn't this say instead " magnet OUT makes connection " ? Debounce info: http://www.ganssle.com/debouncing.htm 1 I didn't see any diode reference in the TPS3613-01 datasheet, but if our hypothesis is current leakage back out B_3V3_BUS, then a low drop series schottky on B_3V3_BUS makes sense. Both the PIC and GPIO expander are good to operate with the additional drop, though I didn't check to ensure all of the GPIO recipients are OK with an additional (but small) drop. Added 220 mV Schottky DGK: CUS08F30H3FCT-ND 0 (Probably a non-issue, but just saw this): I noticed that we potentially have the situation on U23 (Voltage monitor ADC on motherboard) where some of the inputs are higher than VREF (3.0V as provided by LDO). A fresh CR2032 will put out slightly over 3.0V, and the tailcone current monitor looks like it should clamp at 3.18V. The ADC is a 5V tolerant part, so we wont hurt it, but I don't know what it will respond with if Vin is above VREF. ADC128D818 doc pg 5 specs absolute max Voltage on IN0-IN7 as V+ plus 0.3. We are running it at 3.3V, so max V should be 3.6. In searching for max V on a fresh CR2032, I saw an estimate of 3.4 V. I measured two fresh CR2032's and read 3.260 V and 3.264 V. I had put the clamp on " TAILCONE_I_MON " since it seems that voltage could go higher if the tailcone experiences a huge current draw. 1 one thing that we need to look at is how the latch and relays behave during a reset of the 3.3 V power rail. Because of the way the I2c IO expander resets to a co figuration where the pins are all inputs with a pull-up, I’m worried this will toggle the latching relay control lines. We can probably make this work with strong pull downs if this is the case but it’s worth checking now GPIO Expander TCA9555PWR spec suggests High-level output current of 10 mA. Net " XLP_PIC_PWR " voltage level 2.78V ( 3.0 lithium coin cell - 0.220V schottky diode drop ). 2.78V / 10mA = 278 Ohms ( 0.0278 W ) Changed pull-down resistors on FETs for K3 and K7 to 280 Ohms. x One consideration would be to move U140 and U141 to the isolated 3V3 rail, rather than the non-isolated. I guess it can go either way. Note: if U140 Memory chip moves to 3V3_ISO, the signal " MEM_WRITE_EN_N " would need to be opto-isolated, or deleted and connect WP on the Memory chip to B_ISO, allowing the contents to always be written. 12 Feb 21 1 Put U21 TCA9555PWR back on " B_3V3_BUS " ? MAYBE: Remove U17 TPS3613-01; operate PIC off Coin Cell only. Expected current draw: 100 nA ? What about U144 de-bouncer 20 Feb 21 1 Apollo power latching relay: move on/off cmds to PIC 1 Buffer all battery - related ADC inputs w/ TLV2450 voltage follower 1 Add another battery backup pack for Apollo 1 U139 pin 4: change to Apollo power rail 1 Change R174 to 100k 1 Use a reed switch for SBD Warrior on/off 27 Feb 21 Backed up sch and pcb MVC_PS_REVB 4 layer design prior to adding layers to make 6 layer board MVC_PS_Revb_27Feb21_0907.DSN and MVC_PS_Revb_27Feb21_0907.brd 9 Mar 2021 From Sir Laughlin: Pg 4 1 The two BSS138 N FETS could use a gate resistor to limit inrush current, since they are connected directly to the PIC. A 470Ohm would limit this to 7 mA. I realize the 138s present small capacitive loads, but we want to treat that PIC like a golden cow given it's responsible for the drop weight. Make sure to put the gate resistor "after" the pull down so as not to create a voltage divider output at the FET gate. Q1 2 3 4 5 6 1 The 280 Ohm pull down's on the gates strike me as stiff. They only present a 11 mA load (well below the 25 mA GPIO limit of the PIC), so I was curious if there was a reason for them being so stiff. Answer: Note from Hans: "one thing that we need to look at is how the latch and relays behave during a reset of the 3.3 V power rail. Because of the way the I2c IO expander resets to a co figuration where the pins are all inputs with a pull-up, I’m worried this will toggle the latching relay control lines. We can probably make this work with strong pull downs if this is the case but it’s worth checking now" Pg 6 1 Change collector input net for optoisolator, already noted in your email. Pg 7 0 This BSS138 (Q4) has a 1M pull down! Seems light. Why the difference from the above 280s? Gate pull-down resistors: Q1 1M Tail Cone Power Enable 2 280 Ohms Latching Relay 3 280 Ohms 4 1M Drop Wt PIC Command 5 280 Ohms Latching Relay 6 280 Ohms 1 Add gate resistor as per note above? Pg 8 1 Same question/comment about the 280 pull-downs and need for gate resistor on the two BSS138s driving the latching relay. 13 Mar 2021 1 Replaced the two optoisolators ( U139 and U123 ) with a dual unit which is guaranteed to work at 40 uA input. This inverts the signal logic to the XLP micro for nets: AVTRAK_MISSION_ABORT_N PRES_SW_ON_N