(ExpressProject "FOO1"
  (ProjectVersion "19981106")
  (ProjectType "PCB")
  (Folder "Design Resources"
    (Folder "Library")
    (NoModify)
    (File ".\foo1.dsn"
      (Type "Schematic Design"))
    (BuildFileAddedOrDeleted "x")
    (CompileFileAddedOrDeleted "x")
    (DRC_Scope "0")
    (DRC_Action "0")
    (DRC_Create_Warnings "FALSE")
    (DRC_View_Output "FALSE")
    (DRC_Preserved_Waived "FALSE")
    (DRC_Run_Electrical_Rules "TRUE")
    (DRC_Run_Physical_Rules "FALSE")
    (DRC_Report_File "Z:\368000_DMO_AUV\SCHEMATICS\FOO\FOO1.DRC")
    (DRC_Check_Ports "FALSE")
    (DRC_Check_Off-Page_Connectors "FALSE")
    (DRC_Report_Ports_and_Off-page_Connectors "FALSE")
    (DRC_SDT_Compatibility "FALSE")
    (DRC_Report_Off-grid_Objects "FALSE")
    (DRC_Check_Unconnected_Nets "TRUE")
    (DRC_Check_for_Misleading_TAP "FALSE")
    (DRC_Report_Netnames "FALSE")
    (DRC_Check_Single_Node_Nets "TRUE")
    (DRC_Run_Electrical_Custom_DRC "FALSE")
    (DRC_Check_No_Driving_Source "TRUE")
    (DRC_Check_Duplicate_NetNames "TRUE")
    (DRC_Check_Floating_Pins "TRUE")
    (DRC_Check_Physical_Power_Pins_Visibility "TRUE")
    (DRC_Check_PCB_Footprint_Property "TRUE")
    (DRC_Check_Normal_Convert_View_Sync "TRUE")
    (DRC_Check_Incorrect_PinGroup_Assignment "TRUE")
    (DRC_Check_High_Speed_Props_Syntax "TRUE")
    (DRC_Check_Missing_Pin_Numbers "TRUE")
    (DRC_Check_Device_With_No_Pins "TRUE")
    (DRC_Check_Power_Ground_Short "TRUE")
    (DRC_Identical_References "TRUE")
    (DRC_Type_Mismatch "TRUE")
    (DRC_Visible_Power_pins "FALSE")
    (DRC_Report_Unused_Part_Packages "TRUE")
    (DRC_Check_Name_Prop_For_HierBlocks "TRUE")
    (DRC_Run_Physical_Custom_DRC "FALSE")
    (Netlist_TAB "0")
    (OTHER_Part_Value "{Value}")
    (OTHER_Netlist_File "FOO1.NET")
    (OTHER_Netlist_File2 "FOO1.CMP")
    (OTHER_View_Output "TRUE")
    (OTHER_View_Output2 "FALSE")
    (OTHER_Formatter "orWirelist.dll")
    (OTHER_PCB_Footprint "{PCB Footprint}")
    (OTHER_Switch0 "FALSE")
    (OTHER_Switch1 "TRUE")
    (OTHER_Switch2 "FALSE")
    (OTHER_Switch3 "FALSE")
    (OTHER_Switch4 "FALSE")
    (OTHER_Switch5 "FALSE")
    (OTHER_Switch6 "FALSE")
    ("Create Allegro Netlist" "TRUE")
    ("Allegro Netlist Directory" "allegro")
    ("View Allegro Netlist Files" "TRUE")
    ("Allegro Netlist Create DCF File" "FALSE")
    ("Update Allegro Board" "FALSE")
    ("Allegro Netlist Output Board File" "allegro\FOO1.brd")
    ("Allegro Netlist Remove Etch" "FALSE")
    ("Allegro Netlist Place Changed Component" "ALWAYS_REPLACE")
    ("Allegro Netlist Open Board in Allegro" "ALLEGRO")
    ("Allegro Setup Backup Versions" "3")
    ("Allegro Setup Output Warnings" "TRUE")
    ("Allegro Setup Ignore Constraints" "FALSE")
    ("Allegro Setup Part Type Length" "31")
    ("Allegro Netlist Combine Property String" "PCB Footprint")
    ("Allegro Netlist Ignore Fixed Property" "FALSE")
    ("Allegro Netlist User Defined Property" "FALSE"))
  (Folder "Outputs"
    (File ".\foo1.drc"
      (Type "Report"))
    (File ".\foo1.net"
      (Type "Report"))
    (File ".\allegro\pstxnet.dat"
      (Type "Report")
      (DisplayName "pstxnet.dat"))
    (File ".\allegro\pstxprt.dat"
      (Type "Report")
      (DisplayName "pstxprt.dat"))
    (File ".\allegro\pstchip.dat"
      (Type "Report")
      (DisplayName "pstchip.dat")))
  (Folder "Referenced Projects")
  (PartMRUSelector
    (TP_040
      (FullPartName "TP_040.Normal")
      (LibraryName "C:\CADENCE\SPB_16.6\TOOLS\CAPTURE\LIBRARY\DRT1.OLB")
      (DeviceIndex "0")))
  (GlobalState
    (FileView
      (Path "Design Resources")
      (Path "Design Resources" ".\foo1.dsn")
      (Path "Design Resources" ".\foo1.dsn" "SCHEMATIC1")
      (Path "Design Resources" ".\foo1.dsn" "Design Cache")
      (Path "Outputs")
      (Select "Design Resources" ".\foo1.dsn" "SCHEMATIC1"))
    (HierarchyView)
    (Doc
      (Type "COrCapturePMDoc")
      (Frame
        (Placement "44 0 1 -1 -1 -4 -23 0 200 0 515"))
      (Tab 0))
    (Doc
      (Type "COrSchematicDoc")
      (Frame
        (Placement "44 0 1 -1 -1 -4 -23 220 1851 220 762")
        (Scroll "-281 0")
        (Zoom "51")
        (Occurrence "/"))
      (Path "Z:\368000_DMO_AUV\SCHEMATICS\FOO\FOO1.DSN")
      (Schematic "SCHEMATIC1")
      (Page "PAGE1"))
    (Doc
      (Type "TextFile")
      (Frame
        (Placement "44 0 1 -1 -1 -4 -23 198 1829 198 740"))
      (Path "Z:\368000_DMO_AUV\SCHEMATICS\FOO\allegro\pstxprt.dat")
      (Scroll "0"))
    (Doc
      (Type "TextFile")
      (Frame
        (Placement "44 2 3 -1 -1 -4 -23 242 1873 242 784"))
      (Path "Z:\368000_DMO_AUV\SCHEMATICS\FOO\allegro\pstchip.dat")
      (Scroll "0"))
    (Doc
      (Type "TextFile")
      (Frame
        (Placement "44 0 1 -1 -1 -4 -23 220 1851 220 762"))
      (Path "Z:\368000_DMO_AUV\SCHEMATICS\FOO\allegro\pstxnet.dat")
      (Scroll "0")))
  (ISPCBBASICLICENSE "false")
  (MPSSessionName "drthom"))