(ExpressProject "HiSideLT1910"
  (ProjectVersion "19981106")
  (ProjectType "PCB")
  (Folder "Design Resources"
    (Folder "Library")
    (NoModify)
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      (Type "Schematic Design"))
    (BuildFileAddedOrDeleted "x")
    (CompileFileAddedOrDeleted "x")
    (DRC_Scope "0")
    (DRC_Action "0")
    (DRC_Create_Warnings "FALSE")
    (DRC_Check_Ports "FALSE")
    (DRC_Check_Off-Page_Connectors "FALSE")
    (DRC_Identical_References "TRUE")
    (DRC_Type_Mismatch "TRUE")
    (DRC_Report_Ports_and_Off-page_Connectors "FALSE")
    (DRC_SDT_Compatibility "FALSE")
    (DRC_Report_Off-grid_Objects "FALSE")
    (DRC_Check_Unconnected_Nets "TRUE")
    (DRC_Check_for_Misleading_TAP "FALSE")
    (DRC_Visible_Power_pins "FALSE")
    (DRC_Report_Netnames "FALSE")
    (DRC_View_Output "FALSE")
    (DRC_Report_File
       "\\TORNADO\PROJECTLIBRARY\368000_DMO_AUV\SCHEMATICS\HIGH_SIDER\LT1910\SCHPCB\HISIDELT1910.DRC")
    (Netlist_TAB "3")
    (OTHER_Part_Value "{Value}")
    (OTHER_Netlist_File "HISIDELT1910.NET")
    (OTHER_Netlist_File2 "HISIDELT1910.CMP")
    (OTHER_View_Output "TRUE")
    (OTHER_View_Output2 "FALSE")
    (OTHER_Formatter "wirelist.dll")
    (OTHER_PCB_Footprint "{PCB Footprint}")
    (OTHER_Switch0 "FALSE")
    (OTHER_Switch1 "TRUE")
    (OTHER_Switch2 "FALSE")
    (OTHER_Switch3 "FALSE")
    (OTHER_Switch4 "FALSE")
    (OTHER_Switch5 "FALSE")
    (OTHER_Switch6 "FALSE")
    (LAYOUT_Netlist_File "HISIDELT1910.MNL")
    (LAYOUT_PCB_Footprint "{PCB Footprint}")
    (FALSE)
    (LAYOUT_Units "0")
    (GATE_&_PIN_SWAP_Scope "0")
    (GATE_&_PIN_SWAP_File_Name
       "\\Tornado\projectlibrary\368000_DMO_AUV\Schematics\HIGH_SIDER\LT1910\SchPcb\HISIDELT1910-2.SWP")
    (Backannotation_TAB "1"))
  (Folder "Outputs"
    (File ".\hisidelt1910.drc"
      (Type "Report"))
    (File ".\hisidelt1910.net"
      (Type "Report"))
    (File ".\hisidelt1910.mnl"
      (Type "LAYOUT Netlist File")))
  (Folder "Referenced Projects")
  (PartMRUSelector
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      (FullPartName "CON1.Normal")
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      (DeviceIndex "0"))
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      (FullPartName "CON4.Normal")
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      (FullPartName "CAP NP.Normal")
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    (C
      (FullPartName "C.Normal")
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    (GND
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    ("N DGS"
      (FullPartName "N DGS.Normal")
      (LibraryName "C:\ORCAD\ORCAD_16.2\TOOLS\CAPTURE\LIBRARY\TRANSISTOR.OLB")
      (DeviceIndex "0"))
    (LT1910
      (FullPartName "LT1910.Normal")
      (LibraryName
         "\\TORNADO\ORCAD\MBARILIBS\CAPTURE_CIS_SYMBOL_LIBRARIES\DRT1.OLB")
      (DeviceIndex "0")))
  (LastUsedLibraryBrowseDirectory "C:\OrCAD\OrCAD_16.2\tools\capture\library")
  (GlobalState
    (FileView
      (Path "Design Resources")
      (Path "Design Resources" ".\hisidelt1910.dsn")
      (Path "Design Resources" ".\hisidelt1910.dsn" "SCHEMATIC1")
      (Path "Outputs")
      (Select "Design Resources" ".\hisidelt1910.dsn" "SCHEMATIC1" "PAGE1"))
    (HierarchyView)
    (Doc
      (Type "COrCapturePMDoc")
      (Frame
        (Placement "44 0 1 -1 -1 -4 -23 0 200 0 587"))
      (Tab 0))
    (Doc
      (Type "COrSchematicDoc")
      (Frame
        (Placement "44 2 3 -1 -1 -4 -23 286 1579 286 904")
        (Scroll "-237 0")
        (Zoom "89")
        (Occurrence "/"))
      (Path
         "\\TORNADO\PROJECTLIBRARY\368000_DMO_AUV\SCHEMATICS\HIGH_SIDER\LT1910\SCHPCB\HISIDELT1910.DSN")
      (Schematic "SCHEMATIC1")
      (Page "PAGE1")))
  (ISPCBBASICLICENSE "false")
  (MPSSessionName "drthom"))