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    (CompileFileAddedOrDeleted "x")
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    (DRC_Check_for_Misleading_TAP "FALSE")
    (DRC_Visible_Power_pins "FALSE")
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    (DRC_View_Output "FALSE")
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    (OTHER_Netlist_File2 "HIGH_SIDER.CMP")
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    (OTHER_View_Output2 "FALSE")
    (OTHER_Formatter "wirelist.dll")
    (OTHER_PCB_Footprint "{PCB Footprint}")
    (OTHER_Switch0 "FALSE")
    (OTHER_Switch1 "TRUE")
    (OTHER_Switch2 "FALSE")
    (OTHER_Switch3 "FALSE")
    (OTHER_Switch4 "FALSE")
    (OTHER_Switch5 "FALSE")
    (OTHER_Switch6 "FALSE")
    (LAYOUT_Netlist_File "HIGH_SIDER.MNL")
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    (LAYOUT_Units "0")
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    (File ".\high_sider.net"
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  (Folder "Referenced Projects")
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      (Path "Design Resources" ".\high_sider.dsn" "HIGH_SIDER")
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      (Select "Design Resources" ".\high_sider.dsn" "HIGH_SIDER" "PAGE1"))
    (HierarchyView)
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      (Frame
        (Placement "44 2 3 -1 -1 -4 -23 0 200 0 594"))
      (Tab 0)))
  (MPSSessionName "drthom"))