/* FILE: phy_dp83848.h * * Copyright 1996-2011 by InterNiche Technologies Inc. All rights reserved. * * Nat'l Semiconductor DP83848C PHY support * */ #ifndef _PHY_H_ #define _PHY_H_ 1 /* National Semiconductor DP83848 ID */ #define NATIONAL_OUI 0x080017 #define OUI_MSB ((NATIONAL_OUI >> 6) & 0xffff) #define OUI_LSB ((NATIONAL_OUI & 0x3f) << 10) #define VNDR_MDL (0x9 << 4) #define MDL_REV (0x0) /* MAC PHY address */ #define EMAC_PHY_ADDR 1 /* Standard IEEE PHY MII register definitions */ #define PHY_BMCR 0 /* Basic Mode Control Reg */ #define PHY_BMSR 1 /* Basic Mode Status Reg */ #define PHY_PHYIDR1 2 /* ID Reg #1 */ #define PHY_PHYIDR2 3 /* ID Reg #2 */ #define PHY_ANAR 4 /* AutoNeg. Advertisment Reg */ #define PHY_ANLPAR 5 /* AutoNeg. Link Partner (Base Page) Reg */ #define PHY_ANLPARNP 5 /* AutoNeg. Link Partner (Next Page) Reg */ #define PHY_ANER 6 /* AutoNeg. Expansion Reg */ #define PHY_ANNPTR 7 /* AutoNeg. Next Page TX Reg */ /* Extended registers for DP83848 */ #define PHY_PHYSTS 16 /* PHY Status Reg */ #define PHY_MICR 17 /* MII Interrupt Control Reg */ #define PHY_MISR 18 /* MII Interrupt Status Reg */ #define PHY_FCSCR 20 /* False Carrier Sense Counter Reg */ #define PHY_RECR 21 /* Receive Error Counter Reg */ #define PHY_PCSR 22 /* PCS Sub-layer Config/Status Reg */ #define PHY_RBR 23 /* RMII and Bypass Reg */ #define PHY_LEDCR 24 /* LED Direct Control Reg */ #define PHY_PHYCR 25 /* PHY Control Reg */ #define PHY_10BTSCR 26 /* 10Base-T Status/Control Reg */ #define PHY_CDCTRL1 27 /* CD Test Ctrl and BIST Ext Reg */ #define PHY_EDCR 29 /* Energy Detect Control Reg */ /* PHY_BMCR */ #define BMCR_COLL_TEST (1 << 7) #define BMCR_DUPLEX (1 << 8) #define BMCR_RE_AN (1 << 9) #define BMCR_ISOLATE (1 << 10) #define BMCR_PWR_DN (1 << 11) #define BMCR_AN (1 << 12) #define BMCR_SPEED (1 << 13) #define BMCR_LOOPBACK (1 << 14) #define BMCR_RESET (1 << 15) /* PHY_ANAR */ #define ANAR_SELECTOR_MSK (0x1f) #define ANAR_10 (1 << 5) #define ANAR_10_FD (1 << 6) #define ANAR_TX (1 << 7) #define ANAR_TX_FD (1 << 8) #define ANAR_T4 (1 << 9) #define ANAR_PAUSE (1 << 10) #define ANAR_ASM_DIR (1 << 11) #define ANAR_RF (1 << 13) #define ANAR_NP (1 << 15) /* PHY_PHYSTS */ #define PHYSTS_LINK (1 << 0) #define PHYSTS_SPEED (1 << 1) #define PHYSTS_DUPLEX (1 << 2) #define PHYSTS_LOOPBACK (1 << 3) #define PHYSTS_AN_DONE (1 << 4) #define PHYSTS_JABBER (1 << 5) #define PHYSTS_REM_FAULT (1 << 6) #define PHYSTS_MII_INTR (1 << 7) #define PHYSTS_PAGE (1 << 8) #define PHYSTS_DESCRAMBLER (1 << 9) #define PHYSTS_SIGNAL (1 << 10) #define PHYSTS_FCS_LATCH (1 << 11) #define PHYSTS_POLARITY (1 << 12) #define PHYSTS_RE_LATCH (1 << 13) #define PHYSTS_MDI_X (1 << 14) /* Interniche MAC interface routines */ extern void eth_setlink(unsigned phyaddr, int speed, bool_t duplex); /* PHY control */ extern int emac_phy_init(void); extern unsigned short emac_phy_read(unsigned phyaddr, const unsigned phyreg); extern void emac_phy_write(unsigned phyaddr, const unsigned phyreg, const unshort data); extern void usleep(int usec); #endif /* _PHY_H_ */