; generated by Component: ARM Compiler 5.06 update 1 (build 61) Tool: ArmCC [4d35ad]
; commandline ArmCC [--list --debug -c --asm --interleave -o.\obj\mdio.o --asm_dir=.\Obj\ --list_dir=.\Obj\ --depend=.\obj\mdio.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931 -I. -I.\Core_CM3 -ID:\work\arm\lpc1769_eth_bootloader\RTE -I"C:\Program Files\Keil\ARM\PACK\Keil\LPC1700_DFP\2.2.0\Device\Include" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -D__UVISION_VERSION=517 -DLPC175x_6x --omf_browse=.\obj\mdio.crf ethernet\mdio.c]
                          THUMB

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  delay PROC
;;;13     
;;;14     static void delay (void) {;};
000000  4770              BX       lr
;;;15     
                          ENDP

                  output_MDIO PROC
;;;18     
;;;19     static void output_MDIO (U32 val, U32 n) {
000002  b570              PUSH     {r4-r6,lr}
000004  4605              MOV      r5,r0
000006  460c              MOV      r4,r1
;;;20     
;;;21        /* Output a value to the MII PHY management interface. */
;;;22        for (val <<= (32 - n); n; val <<= 1, n--) {
000008  f1c40020          RSB      r0,r4,#0x20
00000c  4085              LSLS     r5,r5,r0
00000e  e019              B        |L1.68|
                  |L1.16|
;;;23           if (val & 0x80000000) {
000010  f0054000          AND      r0,r5,#0x80000000
000014  b120              CBZ      r0,|L1.32|
;;;24              LPC_GPIO2->FIOSET = MDIO;
000016  f44f7000          MOV      r0,#0x200
00001a  4946              LDR      r1,|L1.308|
00001c  6588              STR      r0,[r1,#0x58]
00001e  e003              B        |L1.40|
                  |L1.32|
;;;25           }
;;;26           else {
;;;27              LPC_GPIO2->FIOCLR = MDIO;
000020  f44f7000          MOV      r0,#0x200
000024  4943              LDR      r1,|L1.308|
000026  65c8              STR      r0,[r1,#0x5c]
                  |L1.40|
;;;28           }
;;;29           delay ();
000028  f7fffffe          BL       delay
;;;30           LPC_GPIO2->FIOSET = MDC;
00002c  f44f7080          MOV      r0,#0x100
000030  4940              LDR      r1,|L1.308|
000032  6588              STR      r0,[r1,#0x58]
;;;31           delay ();
000034  f7fffffe          BL       delay
;;;32           LPC_GPIO2->FIOCLR = MDC;
000038  f44f7080          MOV      r0,#0x100
00003c  493d              LDR      r1,|L1.308|
00003e  65c8              STR      r0,[r1,#0x5c]
000040  006d              LSLS     r5,r5,#1              ;22
000042  1e64              SUBS     r4,r4,#1              ;22
                  |L1.68|
000044  2c00              CMP      r4,#0                 ;22
000046  d1e3              BNE      |L1.16|
;;;33        }
;;;34     }
000048  bd70              POP      {r4-r6,pc}
;;;35     
                          ENDP

                  turnaround_MDIO PROC
;;;37     
;;;38     static void turnaround_MDIO (void) {
00004a  b510              PUSH     {r4,lr}
;;;39     
;;;40        /* Turnaround MDO is tristated. */
;;;41        LPC_GPIO2->FIODIR &= ~MDIO;
00004c  4839              LDR      r0,|L1.308|
00004e  6c00              LDR      r0,[r0,#0x40]
000050  f4207000          BIC      r0,r0,#0x200
000054  4937              LDR      r1,|L1.308|
000056  6408              STR      r0,[r1,#0x40]
;;;42        LPC_GPIO2->FIOSET  = MDC;
000058  1548              ASRS     r0,r1,#21
00005a  6588              STR      r0,[r1,#0x58]
;;;43        delay ();
00005c  f7fffffe          BL       delay
;;;44        LPC_GPIO2->FIOCLR  = MDC;
000060  f44f7080          MOV      r0,#0x100
000064  4933              LDR      r1,|L1.308|
000066  65c8              STR      r0,[r1,#0x5c]
;;;45        delay ();
000068  f7fffffe          BL       delay
;;;46     }
00006c  bd10              POP      {r4,pc}
;;;47     
                          ENDP

                  input_MDIO PROC
;;;49     
;;;50     static U32 input_MDIO (void) {
00006e  b570              PUSH     {r4-r6,lr}
;;;51     
;;;52        /* Input a value from the MII PHY management interface. */
;;;53        U32 i,val = 0;
000070  2400              MOVS     r4,#0
;;;54     
;;;55        for (i = 0; i < 16; i++) {
000072  2500              MOVS     r5,#0
000074  e012              B        |L1.156|
                  |L1.118|
;;;56           val <<= 1;
000076  0064              LSLS     r4,r4,#1
;;;57           LPC_GPIO2->FIOSET = MDC;
000078  f44f7080          MOV      r0,#0x100
00007c  492d              LDR      r1,|L1.308|
00007e  6588              STR      r0,[r1,#0x58]
;;;58           delay ();
000080  f7fffffe          BL       delay
;;;59           LPC_GPIO2->FIOCLR = MDC;
000084  f44f7080          MOV      r0,#0x100
000088  492a              LDR      r1,|L1.308|
00008a  65c8              STR      r0,[r1,#0x5c]
;;;60           if (LPC_GPIO2->FIOPIN & MDIO) {
00008c  4608              MOV      r0,r1
00008e  6d40              LDR      r0,[r0,#0x54]
000090  f4007000          AND      r0,r0,#0x200
000094  b108              CBZ      r0,|L1.154|
;;;61              val |= 1;
000096  f0440401          ORR      r4,r4,#1
                  |L1.154|
00009a  1c6d              ADDS     r5,r5,#1              ;55
                  |L1.156|
00009c  2d10              CMP      r5,#0x10              ;55
00009e  d3ea              BCC      |L1.118|
;;;62           }
;;;63        }
;;;64        return (val);
0000a0  4620              MOV      r0,r4
;;;65     }
0000a2  bd70              POP      {r4-r6,pc}
;;;66     
                          ENDP

                  mdio_read PROC
;;;67     
;;;68     U32 mdio_read(int PhyReg) {
0000a4  b570              PUSH     {r4-r6,lr}
0000a6  4604              MOV      r4,r0
;;;69        U32 val;
;;;70     
;;;71        /* Configuring MDC on P2.8 and MDIO on P2.9 */
;;;72        LPC_GPIO2->FIODIR |= MDIO;
0000a8  4822              LDR      r0,|L1.308|
0000aa  6c00              LDR      r0,[r0,#0x40]
0000ac  f4407000          ORR      r0,r0,#0x200
0000b0  4920              LDR      r1,|L1.308|
0000b2  6408              STR      r0,[r1,#0x40]
;;;73     
;;;74        /* 32 consecutive ones on MDO to establish sync */
;;;75        output_MDIO (0xFFFFFFFF, 32);
0000b4  2120              MOVS     r1,#0x20
0000b6  f04f30ff          MOV      r0,#0xffffffff
0000ba  f7fffffe          BL       output_MDIO
;;;76     
;;;77        /* start code (01), read command (10) */
;;;78        output_MDIO (0x06, 4);
0000be  2104              MOVS     r1,#4
0000c0  2006              MOVS     r0,#6
0000c2  f7fffffe          BL       output_MDIO
;;;79     
;;;80        /* write PHY address */
;;;81        output_MDIO (PHY_ADDRESS, 5);
0000c6  2105              MOVS     r1,#5
0000c8  2001              MOVS     r0,#1
0000ca  f7fffffe          BL       output_MDIO
;;;82     
;;;83        /* write the PHY register to write */
;;;84        output_MDIO (PhyReg, 5);
0000ce  2105              MOVS     r1,#5
0000d0  4620              MOV      r0,r4
0000d2  f7fffffe          BL       output_MDIO
;;;85     
;;;86        /* turnaround MDO is tristated */
;;;87        turnaround_MDIO ();
0000d6  f7fffffe          BL       turnaround_MDIO
;;;88     
;;;89        /* read the data value */
;;;90        val = input_MDIO ();
0000da  f7fffffe          BL       input_MDIO
0000de  4605              MOV      r5,r0
;;;91     
;;;92        /* turnaround MDIO is tristated */
;;;93        turnaround_MDIO ();
0000e0  f7fffffe          BL       turnaround_MDIO
;;;94     
;;;95        return (val);
0000e4  4628              MOV      r0,r5
;;;96     }
0000e6  bd70              POP      {r4-r6,pc}
;;;97     
                          ENDP

                  mdio_write PROC
;;;98     
;;;99     void mdio_write(int PhyReg, int Value) {
0000e8  b570              PUSH     {r4-r6,lr}
0000ea  4605              MOV      r5,r0
0000ec  460c              MOV      r4,r1
;;;100    
;;;101      /* Configuring MDC on P2.8 and MDIO on P2.9 */
;;;102      LPC_GPIO2->FIODIR |= MDIO;
0000ee  4811              LDR      r0,|L1.308|
0000f0  6c00              LDR      r0,[r0,#0x40]
0000f2  f4407000          ORR      r0,r0,#0x200
0000f6  490f              LDR      r1,|L1.308|
0000f8  6408              STR      r0,[r1,#0x40]
;;;103    
;;;104      /* 32 consecutive ones on MDO to establish sync */
;;;105      output_MDIO (0xFFFFFFFF, 32);
0000fa  2120              MOVS     r1,#0x20
0000fc  f04f30ff          MOV      r0,#0xffffffff
000100  f7fffffe          BL       output_MDIO
;;;106    
;;;107      /* start code (01), write command (01) */
;;;108      output_MDIO (0x05, 4);
000104  2104              MOVS     r1,#4
000106  2005              MOVS     r0,#5
000108  f7fffffe          BL       output_MDIO
;;;109    
;;;110      /* write PHY address */
;;;111      output_MDIO (PHY_ADDRESS, 5);
00010c  2105              MOVS     r1,#5
00010e  2001              MOVS     r0,#1
000110  f7fffffe          BL       output_MDIO
;;;112    
;;;113      /* write the PHY register to write */
;;;114      output_MDIO (PhyReg, 5);
000114  2105              MOVS     r1,#5
000116  4628              MOV      r0,r5
000118  f7fffffe          BL       output_MDIO
;;;115    
;;;116      /* turnaround MDIO (1,0)*/
;;;117      output_MDIO (0x02, 2);
00011c  2102              MOVS     r1,#2
00011e  4608              MOV      r0,r1
000120  f7fffffe          BL       output_MDIO
;;;118      
;;;119      /* write the data value */
;;;120      output_MDIO (Value, 16);
000124  2110              MOVS     r1,#0x10
000126  4620              MOV      r0,r4
000128  f7fffffe          BL       output_MDIO
;;;121    
;;;122      /* turnaround MDO is tristated */
;;;123      turnaround_MDIO ();
00012c  f7fffffe          BL       turnaround_MDIO
;;;124    }
000130  bd70              POP      {r4-r6,pc}
                          ENDP

000132  0000              DCW      0x0000
                  |L1.308|
                          DCD      0x2009c000
