LPCOpen Platform  v1.03
LPCOpen Platform for NXP LPC Microcontrollers
 All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
app_clock_apis.c
Go to the documentation of this file.
1 /*
2  * @brief Clock APIs example
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2012
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #include <stdlib.h>
33 #include <string.h>
34 #include "board.h"
35 #include "chip.h"
36 
62 /*****************************************************************************
63  * Private types/enumerations/variables
64  ****************************************************************************/
65 
66 /* Input Clock structure */
67 typedef struct {
69  char clkin_name[16];
70 } CLKIN_NAME_T;
71 
72 /* Base Clock Information structure */
73 typedef struct {
75  char clock_name[16];
77 
78 /* Peripheral Clock Information structure */
79 typedef struct {
81  char clock_name[16];
83 
84 static char menu[] =
85  "********************************************************************************\n\r"
86  "Clock APIs demo \n\r"
87  "Demonstrates how to setup, enable, disable clocks, reading the clock frequencies\n\r"
88  "********************************************************************************\n\r";
89 
91  {CLKIN_32K, "Ext 32KHz", },
92  {CLKIN_IRC, "Int IRC", },
93  {CLKIN_ENET_RX, "ENET_RX", },
94  {CLKIN_ENET_TX, "ENET_TX", },
95  {CLKIN_CLKIN, "Ext GPCLKIN", },
96  {CLKIN_CRYSTAL, "Crystal", },
97  {CLKIN_USBPLL, "USB PLL", },
98  {CLKIN_AUDIOPLL, "Audio PLL", },
99  {CLKIN_MAINPLL, "Main PLL", },
100  {CLKIN_IDIVA, "IDIV A", },
101  {CLKIN_IDIVB, "IDIV B", },
102  {CLKIN_IDIVC, "IDIV C", },
103  {CLKIN_IDIVD, "IDIV D", },
104  {CLKIN_IDIVE, "IDIV E", },
105 };
106 
108  {CLK_BASE_SAFE, "SAFE", },
109  {CLK_BASE_USB0, "USB0", },
110 #if defined(CHIP_LPC43XX)
111  {CLK_BASE_PERIPH, "PERIPH", },
112 #endif
113  {CLK_BASE_USB1, "USB1", },
114  {CLK_BASE_MX, "MX_CORE", },
115  {CLK_BASE_SPIFI, "SPIFI", },
116 #if defined(CHIP_LPC43XX)
117  {CLK_BASE_SPI, "SPI", },
118 #endif
119  {CLK_BASE_PHY_RX, "PHY_RX", },
120  {CLK_BASE_PHY_TX, "PHY_TX", },
121  {CLK_BASE_APB1, "APB1", },
122  {CLK_BASE_APB3, "APB3", },
123  {CLK_BASE_LCD, "LCD", },
124 #if defined(CHIP_LPC43XX)
125  {CLK_BASE_VADC, "VADC", },
126 #endif
127  {CLK_BASE_SDIO, "SDIO", },
128  {CLK_BASE_SSP0, "SSP0", },
129  {CLK_BASE_SSP1, "SSP1", },
130  {CLK_BASE_UART0, "UART0", },
131  {CLK_BASE_UART1, "UART1", },
132  {CLK_BASE_UART2, "UART2", },
133  {CLK_BASE_UART3, "UART3", },
134  {CLK_BASE_OUT, "BASE OUT", },
135  {CLK_BASE_CGU_OUT0, "CGU_OUT0", },
136  {CLK_BASE_CGU_OUT1, "CGU_OUT1", },
137 };
138 
140  /* CCU1 clocks */
141  {CLK_APB3_BUS, "APB3", },
142  {CLK_APB3_I2C1, "I2C1", },
143  {CLK_APB3_DAC, "DAC", },
144  {CLK_APB3_ADC0, "ADC0", },
145  {CLK_APB3_ADC1, "ADC1", },
146  {CLK_APB3_CAN0, "CAN0", },
147  {CLK_APB1_BUS, "APB1 BUS", },
148  {CLK_APB1_MOTOCON, "MOTORCON", },
149  {CLK_APB1_I2C0, "I2C0", },
150  {CLK_APB1_I2S, "I2S", },
151  {CLK_APB1_CAN1, "CAN1", },
152  {CLK_SPIFI, "SPIFI", },
153  {CLK_MX_BUS, "MX BUS", },
154  {CLK_MX_SPIFI, "MX SPIFI", },
155  {CLK_MX_GPIO, "GPIO", },
156  {CLK_MX_LCD, "LCD", },
157  {CLK_MX_ETHERNET, "ETHERNET", },
158  {CLK_MX_USB0, "MX USB0", },
159  {CLK_MX_EMC, "MX EMC", },
160  {CLK_MX_SDIO, "MX SDIO", },
161  {CLK_MX_DMA, "MX DMA", },
162  {CLK_MX_MXCORE, "MX CORE", },
163  {CLK_MX_SCT, "MX SCT", },
164  {CLK_MX_USB1, "MX USB1", },
165  {CLK_MX_EMC_DIV, "MX EMC DIV", },
166  {CLK_MX_FLASHA, "MX FLASH A", },
167  {CLK_MX_FLASHB, "MX FLASH B", },
168 #if defined(CHIP_LPC43XX)
169  {CLK_M4_M0APP, "M4 M0 APP", },
170  {CLK_MX_VADC, "VADC", },
171 #endif
172  {CLK_MX_EEPROM, "EEPROM", },
173  {CLK_MX_WWDT, "WWDT", },
174  {CLK_MX_UART0, "MX UART0", },
175  {CLK_MX_UART1, "MX UART1", },
176  {CLK_MX_SSP0, "MX SSP0", },
177  {CLK_MX_TIMER0, "TIMER0", },
178  {CLK_MX_TIMER1, "TIMER1", },
179  {CLK_MX_SCU, "SCU", },
180  {CLK_MX_CREG, "CREG", },
181  {CLK_MX_RITIMER, "RITIMER", },
182  {CLK_MX_UART2, "MX UART2", },
183  {CLK_MX_UART3, "MX UART3", },
184  {CLK_MX_TIMER2, "TIMER2", },
185  {CLK_MX_TIMER3, "TIMER3", },
186  {CLK_MX_SSP1, "MX SSP1", },
187  {CLK_MX_QEI, "QEI", },
188 #if defined(CHIP_LPC43XX)
189  {CLK_PERIPH_BUS, "PERI BUS", },
190  {CLK_PERIPH_CORE, "PERI CORE", },
191  {CLK_PERIPH_SGPIO, "SGPIO", },
192 #endif
193  /*{CLK_USB0, "BASE USB0", }, */
194  /*{CLK_USB1, "BASE USB1", }, */
195 #if defined(CHIP_LPC43XX)
196  {CLK_SPI, "SPI", },
197  /*{CLK_VADC, "VADC", }, */
198 #endif
199 
200  /* CCU2 clocks */
201  {CLK_APLL, "APLL", },
202  {CLK_APB2_UART3, "UART3", },
203  {CLK_APB2_UART2, "UART2", },
204  {CLK_APB0_UART1, "UART1", },
205  {CLK_APB0_UART0, "UART0", },
206  {CLK_APB2_SSP1, "SSP1", },
207  {CLK_APB0_SSP0, "SSP0", },
208  {CLK_APB2_SDIO, "SDIO", },
209 };
210 
211 /*****************************************************************************
212  * Public types/enumerations/variables
213  ****************************************************************************/
214 
215 /*****************************************************************************
216  * Private functions
217  ****************************************************************************/
218 
219 /*****************************************************************************
220  * Public functions
221  ****************************************************************************/
222 
227 int main(void)
228 {
229  bool bool_status;
230  uint32_t mainpll_freq, clkin_frq, dive_value, baseclk_frq, perclk_frq;
231  CHIP_CGU_CLKIN_T clk_in, base_input;
232  bool autoblocken;
233  bool powerdn;
234  int i;
235  volatile int k = 1;
236 
237  Board_Init();
238 
239  /* Print the Demo Information */
240  DEBUGOUT(menu);
241 
242  /* Main PLL should be locked, Check if Main PLL is locked */
243  DEBUGOUT("=========================================== \r\n");
244  DEBUGOUT("PLL functions \r\n");
245  DEBUGOUT("Main PLL : ");
246  bool_status = Chip_Clock_MainPLLLocked();
247  if (bool_status == true) {
248  DEBUGOUT("Locked\r\n");
249  }
250  else {
251  DEBUGOUT("Not Locked\r\n");
252  return 1;
253  }
254 
255  /* Read Main PLL frequency in Hz */
256  mainpll_freq = Chip_Clock_GetMainPLLHz();
257  if (mainpll_freq == 0) {
258  DEBUGOUT("Error in reading Main PLL frequency \r\n");
259  return 2;
260  }
261  DEBUGOUT("Main PLL Frequency in Hz : %d \r\n", mainpll_freq);
262  DEBUGOUT("=========================================== \r\n");
263 
264  DEBUGOUT("=========================================== \r\n");
265  DEBUGOUT("Clock Divider functions \r\n");
266  /*
267  * Divider E divider is used for SPIFI, source is set to
268  * Main PLL in SysInit code.
269  * Read Divider E source & verify it
270  */
272  if (clk_in != CLKIN_MAINPLL) {
273  DEBUGOUT("Divider E source wrong %d \r\n", clk_in);
274  return 3;
275  }
276  DEBUGOUT("Divider E source set to Main PLL \r\n");
277 
278  /*
279  * Divider E divider is used for SPIFI, divider value should be
280  * between 3 and 5 set in SysInit code.
281  * Read Divider E divider value & verify it
282  */
284  if ( (dive_value < 3) && (dive_value > 5)) {
285  DEBUGOUT("Divider E divider wrong %d \r\n", dive_value);
286  return 4;
287  }
288 
289  DEBUGOUT("Divider E divider value: %d \r\n", dive_value);
290  DEBUGOUT("=========================================== \r\n");
291 
292  /*
293  * Read the frequencies of the input clock sources,
294  * print it on UART prompt
295  */
296  DEBUGOUT("=========================================== \r\n");
297  DEBUGOUT("Input clock frequencies \r\n");
298  DEBUGOUT("=========================================== \r\n");
299  for ( i = 0; i < (sizeof(clkin_info) / sizeof(CLKIN_NAME_T)); i++) {
300  clkin_frq = Chip_Clock_GetClockInputHz(clkin_info[i].clk_in);
301  DEBUGOUT(" %s Frequency : %d Hz \r\n", clkin_info[i].clkin_name, clkin_frq);
302  }
303  DEBUGOUT("=========================================== \r\n");
304 
305  /*
306  * Read the base clock settings & print on UART
307  */
308  DEBUGOUT("=========================================== \r\n");
309  DEBUGOUT("Base Clock Setting Information \r\n");
310  DEBUGOUT("=========================================== \r\n");
311  for ( i = 0; i < (sizeof(baseclk_info) / sizeof(BASECLK_INFO_T)); i++) {
312  /* Read Base clock info, only if base clock is enabled */
313  bool_status = Chip_Clock_IsBaseClockEnabled(baseclk_info[i].clock);
314  if ( bool_status == true) {
315  Chip_Clock_GetBaseClockOpts(baseclk_info[i].clock, &base_input,
316  &autoblocken, &powerdn);
317  /* Read Frequency of the base clock */
318  baseclk_frq = Chip_Clock_GetBaseClocktHz(baseclk_info[i].clock);
319 
320  /* Print details on UART */
321  DEBUGOUT("%s Input Clk: %d Base Clk Frq : %d Hz Auto block: %d Power down: %d \r\n",
322  baseclk_info[i].clock_name, base_input, baseclk_frq, autoblocken, powerdn);
323  }
324  }
325  DEBUGOUT("=========================================== \r\n");
326 
327  /*
328  * Read the peripheral clock rate & print on UART
329  */
330  DEBUGOUT("=========================================== \r\n");
331  DEBUGOUT("Peripheral Clock Rates \r\n");
332  DEBUGOUT("=========================================== \r\n");
333  for ( i = 0; i < (sizeof(ccu_clk_info) / sizeof(CCUCLK_INFO_T)); i++) {
334  /* Read Frequency of the peripheral clock */
335  perclk_frq = Chip_Clock_GetRate(ccu_clk_info[i].per_clk);
336  /* Print the per clock only if it is enabled */
337  if (perclk_frq) {
338  /* Print details on UART */
339  DEBUGOUT("%s Per Frq : %d Hz \r\n", ccu_clk_info[i].clock_name,
340  perclk_frq);
341  }
342  }
343  DEBUGOUT("=========================================== \r\n");
344 
345  while (k) ;
346 
347  return 0;
348 }
349