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ccan_001.h
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1 /*
2  * @brief CCAN registers and control functions
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2012
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #ifndef __CCAN_001_H_
33 #define __CCAN_001_H_
34 
35 #include "sys_config.h"
36 #include "cmsis.h"
37 
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41 
50 typedef struct {
52  union {
55  };
56 
66  __I uint32_t RESERVED[13];
68 
72 typedef struct {
73  __IO uint32_t CNTL;
74  __IO uint32_t STAT;
75  __I uint32_t EC;
76  __IO uint32_t BT;
77  __I uint32_t INT;
78  __IO uint32_t TEST;
79  __IO uint32_t BRPE;
82  __I uint32_t RESERVED2[8];
85  __I uint32_t RESERVED3[6];
86  __I uint32_t ND1;
87  __I uint32_t ND2;
88  __I uint32_t RESERVED4[6];
89  __I uint32_t IR1;
90  __I uint32_t IR2;
91  __I uint32_t RESERVED5[6];
94  __I uint32_t RESERVED6[6];
97 
98 typedef enum IP_CCAN_TEST_MODE {
103 
104 typedef enum IP_CCAN_INT {
105  CCAN_MODULE_INT = 1 << 1,
107  CCAN_ERR_INT = 1 << 3
108 } IP_CCAN_INT_T;
109 
113 typedef struct {
116  uint8_t data[8];
118 typedef enum IP_CCAN_MSG_INTERFACE {
119  IF1 = 0x00,
120  IF2 = 1,
122 typedef enum IP_CCAN_STATUS {
123  CCAN_STAT_LEC = (0x7 << 0),
124  CCAN_STAT_TXOK = (1 << 3),
125  CCAN_STAT_RXOK = (1 << 4),
126  CCAN_STAT_EPASS = (1 << 5),
127  CCAN_STAT_EWARN = (1 << 6),
128  CCAN_STAT_BOFF = (1 << 7)
130 
134 typedef enum IP_CCAN_TRX_MODE {
138 /* Private Macros ---------------------------------------------------------- */
139 #ifndef __GNUC__
140 /* Macro for reading and writing to CCAN IF registers */
141 #define CCAN_IF_Read(LPCx, reg, IFsel) (( ## LPCx ## ->IF ## [IFsel] ## . ## IF ## _ ## reg))
142 #define CCAN_IF_Write(LPCx, reg, IFsel, val) (( ## LPCx ## ->IF ## [IFsel] ## . ## IF ## _ ## reg) = (val))
143 #else
144 #define CCAN_IF_Read(LPCx, reg, IFsel) (LPCx->IF[IFsel].IF ## _ ## reg)
145 #define CCAN_IF_Write(LPCx, reg, IFsel, val) (LPCx->IF[IFsel].IF ## _ ## reg = val)
146 #endif
147 
148 #define CCAN_STATUS_INT 0x8000
149 
150 #define CCAN_TX_DIR 1UL
151 #define CCAN_RX_DIR 0UL
152 
153 /* bit field of IF command mask register */
154 #define CCAN_DATAB (1 << 0) /* 1 is transfer data byte 4-7 to message object, 0 is not */
155 #define CCAN_DATAA (1 << 1) /* 1 is transfer data byte 0-3 to message object, 0 is not */
156 #define CCAN_NEWDAT (1 << 2) /* Clear NEWDAT bit in the message object */
157 #define CCAN_CLRINTPND (1 << 3)
158 #define CCAN_CTRL (1 << 4) /* 1 is transfer the CTRL bit to the message object, 0 is not */
159 #define CCAN_ARB (1 << 5) /* 1 is transfer the ARB bits to the message object, 0 is not */
160 #define CCAN_MASK (1 << 6) /* 1 is transfer the MASK bit to the message object, 0 is not */
161 #define CCAN_RW(n) (((n) & 1UL) << 7) /* 0 is READ, 1 is WRITE */
162 #define CCAN_WR 1UL
163 #define CCAN_RD 0UL
164 
165 /* bit field of IF mask 2 register */
166 #define CCAN_MASK_MXTD (1 << 15) /* 1 extended identifier bit is used in the RX filter unit, 0 is not */
167 #define CCAN_MASK_MDIR(n) (((n) & 0x01) << 14) /* 1 direction bit is used in the RX filter unit, 0 is not */
168 
169 /* bit field of IF identifier 2 register */
170 #define CCAN_ID_MVAL (1 << 15) /* Message valid bit, 1 is valid in the MO handler, 0 is ignored */
171 #define CCAN_ID_MTD (1 << 14) /* 1 extended identifier bit is used in the RX filter unit, 0 is not */
172 #define CCAN_ID_DIR(n) (((n) & 0x01) << 13) /* 1 direction bit is used in the RX filter unit, 0 is not */
173 
174 /* bit field of IF message control register */
175 #define CCAN_NEWD (1 << 15) /* 1 indicates new data is in the message buffer. */
176 #define CCAN_MLST (1 << 14) /* 1 indicates a message loss. */
177 #define CCAN_INTP (1 << 13) /* 1 indicates message object is an interrupt source */
178 #define CCAN_UMSK (1 << 12) /* 1 is to use the mask for the receive filter mask. */
179 #define CCAN_TXIE (1 << 11) /* 1 is TX interrupt enabled */
180 #define CCAN_RXIE (1 << 10) /* 1 is RX interrupt enabled */
181 
182 #define CCAN_RMTEN(n) (((n) & 1UL) << 9) /* 1 is remote frame enabled */
183 
184 #define CCAN_TXRQ (1 << 8) /* 1 is TxRqst enabled */
185 #define CCAN_EOB (1 << 7) /* End of buffer, always write to 1 */
186 #define CCAN_DLC 0x000F /* bit mask for DLC */
187 
188 #define CCAN_ID_STD_MASK 0x07FF
189 #define CCAN_ID_EXT_MASK 0x1FFFFFFF
190 #define CCAN_DLC_MASK 0x0F
191 
192 /* bit field of IF command request n register */
193 #define CCAN_IFCREQ_BUSY 0x8000 /* 1 is writing is progress, cleared when
194  RD/WR done */
195 /* CAN CTRL register */
196 #define CCAN_CTRL_INIT (1 << 0)
197 #define CCAN_CTRL_IE (1 << 1)
198 #define CCAN_CTRL_SIE (1 << 2)
199 #define CCAN_CTRL_EIE (1 << 3)
200 #define CCAN_CTRL_DAR (1 << 5)
201 #define CCAN_CTRL_CCE (1 << 6)
202 #define CCAN_CTRL_TEST (1 << 7)
203 
214 void IP_CCAN_TimingCfg (IP_CCAN_001_T *pCCAN,
215  uint32_t ClkDiv,
216  uint32_t BaudRatePrescaler,
217  uint8_t SynJumpWidth,
218  uint8_t Tseg1,
219  uint8_t Tseg2);
220 
227 void IP_CCAN_SWInit (IP_CCAN_001_T *pCCAN, FunctionalState NewState);
228 
236 void IP_CCAN_IntEnable (IP_CCAN_001_T *pCCAN, IP_CCAN_INT_T Int_type, FunctionalState NewState);
237 
245 
253 
260 
267 void IP_CCAN_SetStatus (IP_CCAN_001_T *pCCAN, uint32_t val);
268 
275 
284 
292 void IP_CCAN_ClearIntPend (IP_CCAN_001_T *pCCAN, IP_CCAN_MSG_INTERFACE_T IFsel, uint8_t msg_num);
293 
301 void IP_CCAN_Clear_NewDataFlag (IP_CCAN_001_T *pCCAN, IP_CCAN_MSG_INTERFACE_T IFsel, uint8_t msg_num);
302 
311 void IP_CCAN_SetValidMsg(IP_CCAN_001_T *pCCAN, IP_CCAN_MSG_INTERFACE_T IFsel, uint8_t msg_num, FunctionalState NewState);
312 
319 
326 
339  uint8_t direction,
340  uint32_t RemoteEnable,
341  uint8_t msg_num,
342  const message_object *msg_ptr);
343 
354  uint8_t msg_num,
355  message_object *msg_buf);
356 
361 #ifdef __cplusplus
362 }
363 #endif
364 
365 #endif /* __CCAN_001_H_ */