cmsis.h

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/*
 * @brief Basic CMSIS include file
 *
 * @note
 * Copyright(C) NXP Semiconductors, 2012
 * All rights reserved.
 *
 * @par
 * Software that is described herein is for illustrative purposes only
 * which provides customers with programming information regarding the
 * LPC products.  This software is supplied "AS IS" without any warranties of
 * any kind, and NXP Semiconductors and its licensor disclaim any and
 * all warranties, express or implied, including all implied warranties of
 * merchantability, fitness for a particular purpose and non-infringement of
 * intellectual property rights.  NXP Semiconductors assumes no responsibility
 * or liability for the use of the software, conveys no license or rights under any
 * patent, copyright, mask work right, or any other intellectual property rights in
 * or to any products. NXP Semiconductors reserves the right to make changes
 * in the software without notification. NXP Semiconductors also makes no
 * representation or warranty that such application will be suitable for the
 * specified use without further testing or modification.
 *
 * @par
 * Permission to use, copy, modify, and distribute this software and its
 * documentation is hereby granted, under NXP Semiconductors' and its
 * licensor's relevant copyrights in the software, without fee, provided that it
 * is used in conjunction with NXP Semiconductors microcontrollers.  This
 * copyright, permission, and disclaimer notice must appear in all copies of
 * this code.
 */

#ifndef __CMSIS_H_
#define __CMSIS_H_

#include "lpc_types.h"
#include "sys_config.h"

#ifdef __cplusplus
extern "C" {
#endif

#if defined(__ARMCC_VERSION)
// Kill warning "#pragma push with no matching #pragma pop"
  #pragma diag_suppress 2525
  #pragma push
  #pragma anon_unions
#elif defined(__CWCC__)
  #pragma push
  #pragma cpp_extensions on
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
//  #pragma push // FIXME not usable for IAR
  #pragma language=extended
#else
  #error Not supported compiler type
#endif

/*
 * ==========================================================================
 * ---------- Interrupt Number Definition -----------------------------------
 * ==========================================================================
 */
#if defined(CHIP_LPC1343)

typedef enum IRQn {
 Reset_IRQn                    = -15, 
 NonMaskableInt_IRQn           = -14, 
 MemoryManagement_IRQn         = -12, 
 BusFault_IRQn                 = -11, 
 UsageFault_IRQn               = -10, 
 SVCall_IRQn                   = -5,  
 DebugMonitor_IRQn             = -4,  
 PendSV_IRQn                   = -2,  
 SysTick_IRQn                  = -1,  
 /******  LPC13xx Specific Interrupt Numbers *******************************************************/
 WAKEUP0_IRQn                  = 0,  
 WAKEUP1_IRQn                  = 1,  
 WAKEUP2_IRQn                  = 2,
 WAKEUP3_IRQn                  = 3,
 WAKEUP4_IRQn                  = 4,
 WAKEUP5_IRQn                  = 5,
 WAKEUP6_IRQn                  = 6,
 WAKEUP7_IRQn                  = 7,
 WAKEUP8_IRQn                  = 8,
 WAKEUP9_IRQn                  = 9,
 WAKEUP10_IRQn                 = 10,
 WAKEUP11_IRQn                 = 11,
 WAKEUP12_IRQn                 = 12,
 WAKEUP13_IRQn                 = 13,
 WAKEUP14_IRQn                 = 14,
 WAKEUP15_IRQn                 = 15,
 WAKEUP16_IRQn                 = 16,
 WAKEUP17_IRQn                 = 17,
 WAKEUP18_IRQn                 = 18,
 WAKEUP19_IRQn                 = 19,
 WAKEUP20_IRQn                 = 20,
 WAKEUP21_IRQn                 = 21,
 WAKEUP22_IRQn                 = 22,
 WAKEUP23_IRQn                 = 23,
 WAKEUP24_IRQn                 = 24,
 WAKEUP25_IRQn                 = 25,
 WAKEUP26_IRQn                 = 26,
 WAKEUP27_IRQn                 = 27,
 WAKEUP28_IRQn                 = 28,
 WAKEUP29_IRQn                 = 29,
 WAKEUP30_IRQn                 = 30,
 WAKEUP31_IRQn                 = 31,
 WAKEUP32_IRQn                 = 32,
 WAKEUP33_IRQn                 = 33,
 WAKEUP34_IRQn                 = 34,
 WAKEUP35_IRQn                 = 35,
 WAKEUP36_IRQn                 = 36,
 WAKEUP37_IRQn                 = 37,
 WAKEUP38_IRQn                 = 38,
 WAKEUP39_IRQn                 = 39,
 I2C0_IRQn                     = 40,  
 TIMER_16_0_IRQn               = 41,  
 TIMER_16_1_IRQn               = 42,  
 TIMER_32_0_IRQn               = 43,  
 TIMER_32_1_IRQn               = 44,  
 SSP0_IRQn                     = 45,  
 UART0_IRQn                    = 46,  
 USB0_IRQn                     = 47,  
 USB0_FIQ_IRQn                 = 48,  
 ADC_IRQn                      = 49,  
 WDT_IRQn                      = 50,  
 BOD_IRQn                      = 51,  
 EINT3_IRQn                    = 53,  
 EINT2_IRQn                    = 54,  
 EINT1_IRQn                    = 55,  
 EINT0_IRQn                    = 56,  
 SSP1_IRQn                     = 57,  
} IRQn_Type;

#elif defined(CHIP_LPC1347)

typedef enum IRQn {
 Reset_IRQn                    = -15,
 NonMaskableInt_IRQn           = -14,
 HardFault_IRQn                = -13,
 MemoryManagement_IRQn         = -12,
 BusFault_IRQn                 = -11,
 UsageFault_IRQn               = -10,
 SVCall_IRQn                   = -5, 
 DebugMonitor_IRQn             = -4, 
 PendSV_IRQn                   = -2, 
 SysTick_IRQn                  = -1, 
 /******  LPC1347 Specific Interrupt Numbers *******************************************************/
 PIN_INT0_IRQn                 = 0, 
 PIN_INT1_IRQn                 = 1, 
 PIN_INT2_IRQn                 = 2, 
 PIN_INT3_IRQn                 = 3, 
 PIN_INT4_IRQn                 = 4, 
 PIN_INT5_IRQn                 = 5, 
 PIN_INT6_IRQn                 = 6, 
 PIN_INT7_IRQn                 = 7, 
 GINT0_IRQn                    = 8, 
 GINT1_IRQn                    = 9, 
 Reserved0_IRQn                = 10, 
 Reserved1_IRQn                = 11, 
 RIT_IRQn                      = 12, 
 Reserved2_IRQn                = 13, 
 SSP1_IRQn                     = 14, 
 I2C0_IRQn                     = 15, 
 TIMER_16_0_IRQn               = 16, 
 TIMER_16_1_IRQn               = 17, 
 TIMER_32_0_IRQn               = 18, 
 TIMER_32_1_IRQn               = 19, 
 SSP0_IRQn                     = 20, 
 UART0_IRQn                    = 21, 
 USB0_IRQn                     = 22, 
 USB0_FIQ_IRQn                 = 23, 
 ADC_IRQn                      = 24, 
 WDT_IRQn                      = 25, 
 BOD_IRQn                      = 26, 
 FMC_IRQn                      = 27, 
 Reserved3_IRQn                = 28, 
 Reserved4_IRQn                = 29, 
 USB_WAKEUP_IRQn               = 30, 
 Reserved5_IRQn                = 31, 
} IRQn_Type;

#else
#error Incorrect or missing device variant (CHIP_1343 or CHIP_1347)
#endif

/*
 * ==========================================================================
 * ----------- Processor and Core Peripheral Section ------------------------
 * ==========================================================================
 */

#if defined(CHIP_LPC1343)

/* Configuration of the Cortex-M3 Processor and Core Peripherals */
#define __MPU_PRESENT             0   
#define __NVIC_PRIO_BITS          3   
#define __Vendor_SysTickConfig    0   
#elif defined(CHIP_LPC1347)

/* Configuration of the Cortex-M3 Processor and Core Peripherals */
#define __CM3_REV              0x0201  
#define __MPU_PRESENT             0   
#define __NVIC_PRIO_BITS          3   
#define __Vendor_SysTickConfig    0   
#endif

#include "core_cm3.h"      /* Cortex-M3 processor and core peripherals           */

#ifdef __cplusplus
}
#endif

#endif /* __CMSIS_H_ */