clock_11xx.h File Reference

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Macros
#define	SYSCTL_IRC_FREQ   (12000000)

Enumerations
enum	CHIP_SYSCTL_PLLCLKSRC_T {   SYSCTL_PLLCLKSRC_IRC = 0, SYSCTL_PLLCLKSRC_MAINOSC, SYSCTL_PLLCLKSRC_RESERVED1, SYSCTL_PLLCLKSRC_RESERVED2,   SYSCTL_PLLCLKSRC_IRC = 0, SYSCTL_PLLCLKSRC_SYSOSC, SYSCTL_PLLCLKSRC_RESERVED1, SYSCTL_PLLCLKSRC_RESERVED2,   SYSCTL_PLLCLKSRC_IRC, SYSCTL_PLLCLKSRC_MAINOSC, SYSCTL_PLLCLKSRC_RESERVED1, SYSCTL_PLLCLKSRC_RESERVED2,   SYSCTL_PLLCLKSRC_IRC = 0, SYSCTL_PLLCLKSRC_SYSOSC, SYSCTL_PLLCLKSRC_RESERVED, SYSCTL_PLLCLKSRC_EXT_CLKIN }
enum	CHIP_WDTLFO_OSC_T {   WDTLFO_OSC_ILLEGAL, WDTLFO_OSC_0_60, WDTLFO_OSC_1_05, WDTLFO_OSC_1_40,   WDTLFO_OSC_1_75, WDTLFO_OSC_2_10, WDTLFO_OSC_2_40, WDTLFO_OSC_2_70,   WDTLFO_OSC_3_00, WDTLFO_OSC_3_25, WDTLFO_OSC_3_50, WDTLFO_OSC_3_75,   WDTLFO_OSC_4_00, WDTLFO_OSC_4_20, WDTLFO_OSC_4_40, WDTLFO_OSC_4_60,   WDTLFO_OSC_ILLEGAL, WDTLFO_OSC_0_60, WDTLFO_OSC_1_05, WDTLFO_OSC_1_40,   WDTLFO_OSC_1_75, WDTLFO_OSC_2_10, WDTLFO_OSC_2_40, WDTLFO_OSC_2_70,   WDTLFO_OSC_3_00, WDTLFO_OSC_3_25, WDTLFO_OSC_3_50, WDTLFO_OSC_3_75,   WDTLFO_OSC_4_00, WDTLFO_OSC_4_20, WDTLFO_OSC_4_40, WDTLFO_OSC_4_60,   WDTLFO_OSC_ILLEGAL, WDTLFO_OSC_0_60, WDTLFO_OSC_1_05, WDTLFO_OSC_1_40,   WDTLFO_OSC_1_75, WDTLFO_OSC_2_10, WDTLFO_OSC_2_40, WDTLFO_OSC_2_70,   WDTLFO_OSC_3_00, WDTLFO_OSC_3_25, WDTLFO_OSC_3_50, WDTLFO_OSC_3_75,   WDTLFO_OSC_4_00, WDTLFO_OSC_4_20, WDTLFO_OSC_4_40, WDTLFO_OSC_4_60 }
enum	CHIP_SYSCTL_MAINCLKSRC_T {   SYSCTL_MAINCLKSRC_IRC = 0, SYSCTL_MAINCLKSRC_PLLIN, SYSCTL_MAINCLKSRC_LFOSC, SYSCTL_MAINCLKSRC_WDTOSC = SYSCTL_MAINCLKSRC_LFOSC,   SYSCTL_MAINCLKSRC_PLLOUT, SYSCTL_MAINCLKSRC_IRC = 0, SYSCTL_MAINCLKSRC_PLLIN, SYSCTL_MAINCLKSRC_WDTOSC,   SYSCTL_MAINCLKSRC_PLLOUT, SYSCTL_MAINCLKSRC_IRC = 0, SYSCTL_MAINCLKSRC_PLLIN, SYSCTL_MAINCLKSRC_WDTOSC,   SYSCTL_MAINCLKSRC_PLLOUT }
enum	CHIP_SYSCTL_CLOCK_T {   SYSCTL_CLOCK_SYS = 0, SYSCTL_CLOCK_ROM, SYSCTL_CLOCK_RAM, SYSCTL_CLOCK_FLASHREG,   SYSCTL_CLOCK_FLASHARRAY, SYSCTL_CLOCK_I2C, SYSCTL_CLOCK_GPIO, SYSCTL_CLOCK_CT16B0,   SYSCTL_CLOCK_CT16B1, SYSCTL_CLOCK_CT32B0, SYSCTL_CLOCK_CT32B1, SYSCTL_CLOCK_SSP0,   SYSCTL_CLOCK_UART0, SYSCTL_CLOCK_ADC, SYSCTL_CLOCK_RESERVED14, SYSCTL_CLOCK_WDT,   SYSCTL_CLOCK_IOCON, SYSCTL_CLOCK_RESERVED17, SYSCTL_CLOCK_SSP1, SYSCTL_CLOCK_PINT,   SYSCTL_CLOCK_RESERVED20, SYSCTL_CLOCK_RESERVED21, SYSCTL_CLOCK_RESERVED22, SYSCTL_CLOCK_P0INT,   SYSCTL_CLOCK_GROUP0INT = SYSCTL_CLOCK_P0INT, SYSCTL_CLOCK_P1INT, SYSCTL_CLOCK_GROUP1INT = SYSCTL_CLOCK_P1INT, SYSCTL_CLOCK_RESERVED25,   SYSCTL_CLOCK_RESERVED26, SYSCTL_CLOCK_RESERVED27, SYSCTL_CLOCK_SYS = 0, SYSCTL_CLOCK_ROM,   SYSCTL_CLOCK_RAM, SYSCTL_CLOCK_FLASHREG, SYSCTL_CLOCK_FLASHARRAY, SYSCTL_CLOCK_I2C,   SYSCTL_CLOCK_GPIO, SYSCTL_CLOCK_CT16B0, SYSCTL_CLOCK_CT16B1, SYSCTL_CLOCK_CT32B0,   SYSCTL_CLOCK_CT32B1, SYSCTL_CLOCK_SSP0, SYSCTL_CLOCK_UART0, SYSCTL_CLOCK_ADC,   SYSCTL_CLOCK_USB, SYSCTL_CLOCK_WDT, SYSCTL_CLOCK_IOCON, SYSCTL_CLOCK_RESERVED17,   SYSCTL_CLOCK_SSP1, SYSCTL_CLOCK_LCD, SYSCTL_CLOCK_TIMER0, SYSCTL_CLOCK_TIMER1,   SYSCTL_CLOCK_UART0, SYSCTL_CLOCK_UART1, SYSCTL_CLOCK_PWM0, SYSCTL_CLOCK_PWM1,   SYSCTL_CLOCK_I2C0, SYSCTL_CLOCK_UART4, SYSCTL_CLOCK_RTC, SYSCTL_CLOCK_SSP1,   SYSCTL_CLOCK_EMC, SYSCTL_CLOCK_ADC, SYSCTL_CLOCK_CAN1, SYSCTL_CLOCK_CAN2,   SYSCTL_CLOCK_GPIO, SYSCTL_CLOCK_SPIFI, SYSCTL_CLOCK_MCPWM, SYSCTL_CLOCK_QEI,   SYSCTL_CLOCK_I2C1, SYSCTL_CLOCK_SSP2, SYSCTL_CLOCK_SSP0, SYSCTL_CLOCK_TIMER2,   SYSCTL_CLOCK_TIMER3, SYSCTL_CLOCK_UART2, SYSCTL_CLOCK_UART3, SYSCTL_CLOCK_I2C2,   SYSCTL_CLOCK_I2S, SYSCTL_CLOCK_SDC, SYSCTL_CLOCK_GPDMA, SYSCTL_CLOCK_ENET,   SYSCTL_CLOCK_USB, SYSCTL_CLOCK_RSVD32, SYSCTL_CLOCK_RSVD33, SYSCTL_CLOCK_RSVD34,   SYSCTL_CLOCK_RSVD35, SYSCTL_CLOCK_SYS = 0, SYSCTL_CLOCK_ROM, SYSCTL_CLOCK_RAM,   SYSCTL_CLOCK_FLASHREG, SYSCTL_CLOCK_FLASH, SYSCTL_CLOCK_I2C, SYSCTL_CLOCK_GPIO,   SYSCTL_CLOCK_SWM, SYSCTL_CLOCK_SCT, SYSCTL_CLOCK_WKT, SYSCTL_CLOCK_MRT,   SYSCTL_CLOCK_SPI0, SYSCTL_CLOCK_SPI1, SYSCTL_CLOCK_CRC, SYSCTL_CLOCK_UART0,   SYSCTL_CLOCK_UART1, SYSCTL_CLOCK_UART2, SYSCTL_CLOCK_WWDT, SYSCTL_CLOCK_IOCON,   SYSCTL_CLOCK_ACOMP }
enum	CHIP_SYSCTL_CLKOUTSRC_T {   SYSCTL_CLKOUTSRC_IRC = 0, SYSCTL_CLKOUTSRC_MAINOSC, SYSCTL_CLKOUTSRC_WDTOSC, SYSCTL_CLKOUTSRC_LFOSC = SYSCTL_CLKOUTSRC_WDTOSC,   SYSCTL_CLKOUTSRC_MAINSYSCLK, SYSCTL_CLKOUTSRC_IRC = 0, SYSCTL_CLKOUTSRC_SYSOSC, SYSCTL_CLKOUTSRC_WDTOSC,   SYSCTL_CLKOUTSRC_MAINSYSCLK, SYSCTL_CLKOUTSRC_CPU, SYSCTL_CLKOUTSRC_MAINOSC, SYSCTL_CLKOUTSRC_IRC,   SYSCTL_CLKOUTSRC_USB, SYSCTL_CLKOUTSRC_RTC, SYSCTL_CLKOUTSRC_SPIFI, SYSCTL_CLKOUTSRC_WATCHDOGOSC,   SYSCTL_CLKOUTSRC_RESERVED3, SYSCTL_CLKOUTSRC_IRC = 0, SYSCTL_CLKOUTSRC_SYSOSC, SYSCTL_CLKOUTSRC_WDTOSC,   SYSCTL_CLKOUTSRC_MAINSYSCLK }

Functions
STATIC INLINE void	Chip_Clock_SetupSystemPLL (uint8_t msel, uint8_t psel)
	Set System PLL divider values.
STATIC INLINE bool	Chip_Clock_IsSystemPLLLocked (void)
	Read System PLL lock status.
void	Chip_Clock_SetSystemPllSource (CHIP_SYSCTL_PLLCLKSRC_T src)
	Set System PLL clock source.
void	Chip_Clock_SetPLLBypass (bool bypass, bool highfr)
	Bypass System Oscillator and set oscillator frequency range.
STATIC INLINE void	Chip_Clock_SetWDTOSC (CHIP_WDTLFO_OSC_T wdtclk, uint8_t div)
	Setup Watchdog oscillator rate and divider.
void	Chip_Clock_SetMainClockSource (CHIP_SYSCTL_MAINCLKSRC_T src)
	Set main system clock source.
STATIC INLINE CHIP_SYSCTL_MAINCLKSRC_T	Chip_Clock_GetMainClockSource (void)
	Returns the main clock source.
STATIC INLINE void	Chip_Clock_SetSysClockDiv (uint32_t div)
	Set system clock divider.
STATIC INLINE void	Chip_Clock_EnablePeriphClock (CHIP_SYSCTL_CLOCK_T clk)
	Enable a system or peripheral clock.
STATIC INLINE void	Chip_Clock_DisablePeriphClock (CHIP_SYSCTL_CLOCK_T clk)
	Disable a system or peripheral clock.
STATIC INLINE void	Chip_Clock_SetSSP0ClockDiv (uint32_t div)
	Set SSP0 divider.
STATIC INLINE uint32_t	Chip_Clock_GetSSP0ClockDiv (void)
	Return SSP0 divider.
STATIC INLINE void	Chip_Clock_SetUARTClockDiv (uint32_t div)
	Set UART divider clock.
STATIC INLINE uint32_t	Chip_Clock_GetUARTClockDiv (void)
	Return UART divider.
void	Chip_Clock_SetCLKOUTSource (CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div)
	Set CLKOUT clock source and divider.
STATIC INLINE uint32_t	Chip_Clock_GetMainOscRate (void)
	Returns the main oscillator clock rate.
STATIC INLINE uint32_t	Chip_Clock_GetIntOscRate (void)
	Returns the internal oscillator (IRC) clock rate.
uint32_t	Chip_Clock_GetWDTOSCRate (void)
	Return estimated watchdog oscillator rate.
uint32_t	Chip_Clock_GetSystemPllInClockRate (void)
	Return System PLL input clock rate.
uint32_t	Chip_Clock_GetSystemPllOutClockRate (void)
	Return System PLL output clock rate.
uint32_t	Chip_Clock_GetMainClockRate (void)
	Return main clock rate.
uint32_t	Chip_Clock_GetSystemClockRate (void)
	Return system clock rate.