clock_13xx.h

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/*
 * @brief LPC13XX Clock control functions
 *
 * @note
 * Copyright(C) NXP Semiconductors, 2012
 * All rights reserved.
 *
 * @par
 * Software that is described herein is for illustrative purposes only
 * which provides customers with programming information regarding the
 * LPC products.  This software is supplied "AS IS" without any warranties of
 * any kind, and NXP Semiconductors and its licensor disclaim any and
 * all warranties, express or implied, including all implied warranties of
 * merchantability, fitness for a particular purpose and non-infringement of
 * intellectual property rights.  NXP Semiconductors assumes no responsibility
 * or liability for the use of the software, conveys no license or rights under any
 * patent, copyright, mask work right, or any other intellectual property rights in
 * or to any products. NXP Semiconductors reserves the right to make changes
 * in the software without notification. NXP Semiconductors also makes no
 * representation or warranty that such application will be suitable for the
 * specified use without further testing or modification.
 *
 * @par
 * Permission to use, copy, modify, and distribute this software and its
 * documentation is hereby granted, under NXP Semiconductors' and its
 * licensor's relevant copyrights in the software, without fee, provided that it
 * is used in conjunction with NXP Semiconductors microcontrollers.  This
 * copyright, permission, and disclaimer notice must appear in all copies of
 * this code.
 */

#ifndef __CLOCK_13XX_H_
#define __CLOCK_13XX_H_

#ifdef __cplusplus
extern "C" {
#endif

#define SYSCTL_IRC_FREQ (12000000)

STATIC INLINE void Chip_Clock_SetupSystemPLL(uint8_t msel, uint8_t psel)
{
 LPC_SYSCTL->SYSPLLCTRL = (msel & 0x1F) | ((psel & 0x3) << 5);
}

STATIC INLINE bool Chip_Clock_IsSystemPLLLocked(void)
{
 return (bool) ((LPC_SYSCTL->SYSPLLSTAT & 1) != 0);
}

typedef enum CHIP_SYSCTL_PLLCLKSRC {
 SYSCTL_PLLCLKSRC_IRC = 0,  
 SYSCTL_PLLCLKSRC_SYSOSC,  
 SYSCTL_PLLCLKSRC_RESERVED1, 
 SYSCTL_PLLCLKSRC_RESERVED2, 
} CHIP_SYSCTL_PLLCLKSRC_T;

void Chip_Clock_SetSystemPllSource(CHIP_SYSCTL_PLLCLKSRC_T src);

STATIC INLINE void Chip_Clock_SetupUSBPLL(uint8_t msel, uint8_t psel)
{
 LPC_SYSCTL->USBPLLCTRL = (msel & 0x1F) | ((psel & 0x3) << 5);
}

STATIC INLINE bool Chip_Clock_IsUSBPLLLocked(void)
{
 return (bool) ((LPC_SYSCTL->USBPLLSTAT & 1) != 0);
}

void Chip_Clock_SetUSBPllSource(CHIP_SYSCTL_PLLCLKSRC_T src);

void Chip_Clock_SetPLLBypass(bool bypass, bool highfr);

typedef enum CHIP_WDTLFO_OSC {
 WDTLFO_OSC_ILLEGAL,
 WDTLFO_OSC_0_60, 
 WDTLFO_OSC_1_05, 
 WDTLFO_OSC_1_40, 
 WDTLFO_OSC_1_75, 
 WDTLFO_OSC_2_10, 
 WDTLFO_OSC_2_40, 
 WDTLFO_OSC_2_70, 
 WDTLFO_OSC_3_00, 
 WDTLFO_OSC_3_25, 
 WDTLFO_OSC_3_50, 
 WDTLFO_OSC_3_75, 
 WDTLFO_OSC_4_00, 
 WDTLFO_OSC_4_20, 
 WDTLFO_OSC_4_40, 
 WDTLFO_OSC_4_60  
} CHIP_WDTLFO_OSC_T;

STATIC INLINE void Chip_Clock_SetWDTOSC(CHIP_WDTLFO_OSC_T wdtclk, uint8_t div)
{
 LPC_SYSCTL->WDTOSCCTRL  = (((uint32_t) wdtclk) << 5) | ((div >> 1) - 1);
}

typedef enum CHIP_SYSCTL_MAINCLKSRC{
 SYSCTL_MAINCLKSRC_IRC = 0,  
 SYSCTL_MAINCLKSRC_PLLIN,  
 SYSCTL_MAINCLKSRC_WDTOSC,  
 SYSCTL_MAINCLKSRC_PLLOUT,  
} CHIP_SYSCTL_MAINCLKSRC_T;

void Chip_Clock_SetMainClockSource(CHIP_SYSCTL_MAINCLKSRC_T src);

STATIC INLINE CHIP_SYSCTL_MAINCLKSRC_T Chip_Clock_GetMainClockSource(void)
{
 return (CHIP_SYSCTL_MAINCLKSRC_T) (LPC_SYSCTL->MAINCLKSEL);
}

STATIC INLINE void Chip_Clock_SetSysClockDiv(uint32_t div)
{
 LPC_SYSCTL->SYSAHBCLKDIV  = div;
}

typedef enum CHIP_SYSCTL_CLOCK{
 SYSCTL_CLOCK_SYS = 0,    
 SYSCTL_CLOCK_ROM,     
 SYSCTL_CLOCK_RAM,     
 SYSCTL_CLOCK_FLASHREG,    
 SYSCTL_CLOCK_FLASHARRAY,   
 SYSCTL_CLOCK_I2C,     
 SYSCTL_CLOCK_GPIO,     
 SYSCTL_CLOCK_CT16B0,    
 SYSCTL_CLOCK_CT16B1,    
 SYSCTL_CLOCK_CT32B0,    
 SYSCTL_CLOCK_CT32B1,    
 SYSCTL_CLOCK_SSP0,     
 SYSCTL_CLOCK_UART0,     
 SYSCTL_CLOCK_ADC,     
 SYSCTL_CLOCK_USB,     
 SYSCTL_CLOCK_WDT,     
 SYSCTL_CLOCK_IOCON,     
 SYSCTL_CLOCK_RESERVED17,   
 SYSCTL_CLOCK_SSP1,     
#if defined(CHIP_LPC1347)
 SYSCTL_CLOCK_PINT,     
 SYSCTL_CLOCK_RESERVED20,   
 SYSCTL_CLOCK_RESERVED21,   
 SYSCTL_CLOCK_RESERVED22,   
 SYSCTL_CLOCK_GROUP0INT,    
 SYSCTL_CLOCK_GROUP1INT,    
 SYSCTL_CLOCK_RESERVED25,   
 SYSCTL_CLOCK_RAM1,     
 SYSCTL_CLOCK_USBRAM,    
#endif
} CHIP_SYSCTL_CLOCK_T;

STATIC INLINE void Chip_Clock_EnablePeriphClock(CHIP_SYSCTL_CLOCK_T clk)
{
 LPC_SYSCTL->SYSAHBCLKCTRL |= (1 << clk);
}

STATIC INLINE void Chip_Clock_DisablePeriphClock(CHIP_SYSCTL_CLOCK_T clk)
{
 LPC_SYSCTL->SYSAHBCLKCTRL &= ~(1 << clk);
}

STATIC INLINE void Chip_Clock_SetSSP0ClockDiv(uint32_t div)
{
 LPC_SYSCTL->SSP0CLKDIV  = div;
}

STATIC INLINE uint32_t Chip_Clock_GetSSP0ClockDiv(void)
{
 return LPC_SYSCTL->SSP0CLKDIV;
}

STATIC INLINE void Chip_Clock_SetUARTClockDiv(uint32_t div)
{
 LPC_SYSCTL->USARTCLKDIV  = div;
}

STATIC INLINE uint32_t Chip_Clock_GetUARTClockDiv(void)
{
 return LPC_SYSCTL->USARTCLKDIV;
}

STATIC INLINE void Chip_Clock_SetSSP1ClockDiv(uint32_t div)
{
 LPC_SYSCTL->SSP1CLKDIV  = div;
}

STATIC INLINE uint32_t Chip_Clock_GetSSP1ClockDiv(void)
{
 return LPC_SYSCTL->SSP1CLKDIV;
}

STATIC INLINE void Chip_Clock_SetTraceClockDiv(uint32_t div)
{
 LPC_SYSCTL->TRACECLKDIV  = div;
}

STATIC INLINE uint32_t Chip_Clock_GetTraceClockDiv(void)
{
 return LPC_SYSCTL->TRACECLKDIV;
}

STATIC INLINE void Chip_Clock_SetSystickClockDiv(uint32_t div)
{
 LPC_SYSCTL->SYSTICKCLKDIV  = div;
}

STATIC INLINE uint32_t Chip_Clock_GetSystickClockDiv(void)
{
 return LPC_SYSCTL->SYSTICKCLKDIV;
}

typedef enum CHIP_SYSCTL_USBCLKSRC{
 SYSCTL_USBCLKSRC_PLLOUT = 0, 
 SYSCTL_USBCLKSRC_MAINSYSCLK, 
} CHIP_SYSCTL_USBCLKSRC_T;

void Chip_Clock_SetUSBClockSource(CHIP_SYSCTL_USBCLKSRC_T src, uint32_t div);

#if defined(CHIP_LPC1343)

typedef enum CHIP_SYSCTL_WDTCLKSRC{
 SYSCTL_WDTCLKSRC_IRC = 0,  
 SYSCTL_WDTCLKSRC_MAINSYSCLK, 
 SYSCTL_WDTCLKSRC_WDTOSC,  
} CHIP_SYSCTL_WDTCLKSRC_T;

void Chip_Clock_SetWDTClockSource(CHIP_SYSCTL_WDTCLKSRC_T src, uint32_t div);

#endif

typedef enum CHIP_SYSCTL_CLKOUTSRC{
 SYSCTL_CLKOUTSRC_IRC = 0,  
 SYSCTL_CLKOUTSRC_SYSOSC,  
 SYSCTL_CLKOUTSRC_WDTOSC,  
 SYSCTL_CLKOUTSRC_MAINSYSCLK, 
} CHIP_SYSCTL_CLKOUTSRC_T;

void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div);

STATIC INLINE uint32_t Chip_Clock_GetMainOscRate(void)
{
 return CRYSTAL_MAIN_FREQ_IN;
}

STATIC INLINE uint32_t Chip_Clock_GetIntOscRate(void)
{
 return SYSCTL_IRC_FREQ;
}

uint32_t Chip_Clock_GetWDTOSCRate(void);

uint32_t Chip_Clock_GetSystemPllInClockRate(void);

uint32_t Chip_Clock_GetSystemPllOutClockRate(void);

uint32_t Chip_Clock_GetUSBPllInClockRate(void);

uint32_t Chip_Clock_GetUSBPllOutClockRate(void);

uint32_t Chip_Clock_GetMainClockRate(void);

uint32_t Chip_Clock_GetSystemClockRate(void);

#ifdef __cplusplus
}
#endif

#endif /* __CLOCK_13XX_H_ */