clock_17xx_40xx.h File Reference

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Macros
#define	SYSCTL_OSCRANGE_15_25   (1 << 4)
#define	SYSCTL_OSCEC   (1 << 5)
#define	SYSCTL_OSCSTAT   (1 << 6)
#define	SYSCTL_IRC_FREQ   (12000000)
#define	SYSCTL_PLL_ENABLE   (1 << 0)
#define	SYSCTL_PLLSTS_ENABLED   (1 << 8)
#define	SYSCTL_PLLSTS_LOCKED   (1 << 10)

Enumerations
enum	CHIP_SYSCTL_CLOCK_T {   SYSCTL_CLOCK_SYS = 0, SYSCTL_CLOCK_ROM, SYSCTL_CLOCK_RAM, SYSCTL_CLOCK_FLASHREG,   SYSCTL_CLOCK_FLASHARRAY, SYSCTL_CLOCK_I2C, SYSCTL_CLOCK_GPIO, SYSCTL_CLOCK_CT16B0,   SYSCTL_CLOCK_CT16B1, SYSCTL_CLOCK_CT32B0, SYSCTL_CLOCK_CT32B1, SYSCTL_CLOCK_SSP0,   SYSCTL_CLOCK_UART0, SYSCTL_CLOCK_ADC, SYSCTL_CLOCK_RESERVED14, SYSCTL_CLOCK_WDT,   SYSCTL_CLOCK_IOCON, SYSCTL_CLOCK_RESERVED17, SYSCTL_CLOCK_SSP1, SYSCTL_CLOCK_PINT,   SYSCTL_CLOCK_RESERVED20, SYSCTL_CLOCK_RESERVED21, SYSCTL_CLOCK_RESERVED22, SYSCTL_CLOCK_P0INT,   SYSCTL_CLOCK_GROUP0INT = SYSCTL_CLOCK_P0INT, SYSCTL_CLOCK_P1INT, SYSCTL_CLOCK_GROUP1INT = SYSCTL_CLOCK_P1INT, SYSCTL_CLOCK_RESERVED25,   SYSCTL_CLOCK_RESERVED26, SYSCTL_CLOCK_RESERVED27, SYSCTL_CLOCK_SYS = 0, SYSCTL_CLOCK_ROM,   SYSCTL_CLOCK_RAM, SYSCTL_CLOCK_FLASHREG, SYSCTL_CLOCK_FLASHARRAY, SYSCTL_CLOCK_I2C,   SYSCTL_CLOCK_GPIO, SYSCTL_CLOCK_CT16B0, SYSCTL_CLOCK_CT16B1, SYSCTL_CLOCK_CT32B0,   SYSCTL_CLOCK_CT32B1, SYSCTL_CLOCK_SSP0, SYSCTL_CLOCK_UART0, SYSCTL_CLOCK_ADC,   SYSCTL_CLOCK_USB, SYSCTL_CLOCK_WDT, SYSCTL_CLOCK_IOCON, SYSCTL_CLOCK_RESERVED17,   SYSCTL_CLOCK_SSP1, SYSCTL_CLOCK_LCD, SYSCTL_CLOCK_TIMER0, SYSCTL_CLOCK_TIMER1,   SYSCTL_CLOCK_UART0, SYSCTL_CLOCK_UART1, SYSCTL_CLOCK_PWM0, SYSCTL_CLOCK_PWM1,   SYSCTL_CLOCK_I2C0, SYSCTL_CLOCK_UART4, SYSCTL_CLOCK_RTC, SYSCTL_CLOCK_SSP1,   SYSCTL_CLOCK_EMC, SYSCTL_CLOCK_ADC, SYSCTL_CLOCK_CAN1, SYSCTL_CLOCK_CAN2,   SYSCTL_CLOCK_GPIO, SYSCTL_CLOCK_SPIFI, SYSCTL_CLOCK_MCPWM, SYSCTL_CLOCK_QEI,   SYSCTL_CLOCK_I2C1, SYSCTL_CLOCK_SSP2, SYSCTL_CLOCK_SSP0, SYSCTL_CLOCK_TIMER2,   SYSCTL_CLOCK_TIMER3, SYSCTL_CLOCK_UART2, SYSCTL_CLOCK_UART3, SYSCTL_CLOCK_I2C2,   SYSCTL_CLOCK_I2S, SYSCTL_CLOCK_SDC, SYSCTL_CLOCK_GPDMA, SYSCTL_CLOCK_ENET,   SYSCTL_CLOCK_USB, SYSCTL_CLOCK_RSVD32, SYSCTL_CLOCK_RSVD33, SYSCTL_CLOCK_RSVD34,   SYSCTL_CLOCK_RSVD35, SYSCTL_CLOCK_SYS = 0, SYSCTL_CLOCK_ROM, SYSCTL_CLOCK_RAM,   SYSCTL_CLOCK_FLASHREG, SYSCTL_CLOCK_FLASH, SYSCTL_CLOCK_I2C, SYSCTL_CLOCK_GPIO,   SYSCTL_CLOCK_SWM, SYSCTL_CLOCK_SCT, SYSCTL_CLOCK_WKT, SYSCTL_CLOCK_MRT,   SYSCTL_CLOCK_SPI0, SYSCTL_CLOCK_SPI1, SYSCTL_CLOCK_CRC, SYSCTL_CLOCK_UART0,   SYSCTL_CLOCK_UART1, SYSCTL_CLOCK_UART2, SYSCTL_CLOCK_WWDT, SYSCTL_CLOCK_IOCON,   SYSCTL_CLOCK_ACOMP }
enum	CHIP_SYSCTL_EMC_DIV_T { SYSCTL_EMC_DIV1 = 0, SYSCTL_EMC_DIV2 = 1 }
enum	CHIP_SYSCTL_CCLKSRC_T { SYSCTL_CCLKSRC_SYSCLK, SYSCTL_CCLKSRC_MAINPLL }
enum	CHIP_SYSCTL_USBCLKSRC_T {   SYSCTL_USBCLKSRC_PLLOUT = 0, SYSCTL_USBCLKSRC_MAINSYSCLK, SYSCTL_USBCLKSRC_SYSCLK, SYSCTL_USBCLKSRC_MAINPLL,   SYSCTL_USBCLKSRC_USBPLL, SYSCTL_USBCLKSRC_RESERVED }
enum	CHIP_SYSCTL_PLLCLKSRC_T {   SYSCTL_PLLCLKSRC_IRC = 0, SYSCTL_PLLCLKSRC_MAINOSC, SYSCTL_PLLCLKSRC_RESERVED1, SYSCTL_PLLCLKSRC_RESERVED2,   SYSCTL_PLLCLKSRC_IRC = 0, SYSCTL_PLLCLKSRC_SYSOSC, SYSCTL_PLLCLKSRC_RESERVED1, SYSCTL_PLLCLKSRC_RESERVED2,   SYSCTL_PLLCLKSRC_IRC, SYSCTL_PLLCLKSRC_MAINOSC, SYSCTL_PLLCLKSRC_RESERVED1, SYSCTL_PLLCLKSRC_RESERVED2,   SYSCTL_PLLCLKSRC_IRC = 0, SYSCTL_PLLCLKSRC_SYSOSC, SYSCTL_PLLCLKSRC_RESERVED, SYSCTL_PLLCLKSRC_EXT_CLKIN }
enum	CHIP_SYSCTL_SPIFICLKSRC_T { SYSCTL_SPIFICLKSRC_SYSCLK, SYSCTL_SPIFICLKSRC_MAINPLL, SYSCTL_SPIFICLKSRC_USBPLL, SYSCTL_SPIFICLKSRC_RESERVED }
enum	CHIP_SYSCTL_CLKOUTSRC_T {   SYSCTL_CLKOUTSRC_IRC = 0, SYSCTL_CLKOUTSRC_MAINOSC, SYSCTL_CLKOUTSRC_WDTOSC, SYSCTL_CLKOUTSRC_LFOSC = SYSCTL_CLKOUTSRC_WDTOSC,   SYSCTL_CLKOUTSRC_MAINSYSCLK, SYSCTL_CLKOUTSRC_IRC = 0, SYSCTL_CLKOUTSRC_SYSOSC, SYSCTL_CLKOUTSRC_WDTOSC,   SYSCTL_CLKOUTSRC_MAINSYSCLK, SYSCTL_CLKOUTSRC_CPU, SYSCTL_CLKOUTSRC_MAINOSC, SYSCTL_CLKOUTSRC_IRC,   SYSCTL_CLKOUTSRC_USB, SYSCTL_CLKOUTSRC_RTC, SYSCTL_CLKOUTSRC_SPIFI, SYSCTL_CLKOUTSRC_WATCHDOGOSC,   SYSCTL_CLKOUTSRC_RESERVED3, SYSCTL_CLKOUTSRC_IRC = 0, SYSCTL_CLKOUTSRC_SYSOSC, SYSCTL_CLKOUTSRC_WDTOSC,   SYSCTL_CLKOUTSRC_MAINSYSCLK }

Functions
void	Chip_Clock_EnablePLL (CHIP_SYSCTL_PLL_T pllNum, uint32_t flags)
	Enables or connects a PLL.
void	Chip_Clock_DisablePLL (CHIP_SYSCTL_PLL_T pllNum, uint32_t flags)
	Disables or disconnects a PLL.
void	Chip_Clock_SetupPLL (CHIP_SYSCTL_PLL_T pllNum, uint32_t msel, uint32_t psel)
	Sets up a PLL.
STATIC INLINE uint32_t	Chip_Clock_GetPLLStatus (CHIP_SYSCTL_PLL_T pllNum)
	Returns PLL status.
STATIC INLINE bool	Chip_Clock_IsMainPLLEnabled (void)
	Read PLL0 enable status.
STATIC INLINE bool	Chip_Clock_IsUSBPLLEnabled (void)
	Read PLL1 enable status.
STATIC INLINE bool	Chip_Clock_IsMainPLLLocked (void)
	Read PLL0 lock status.
STATIC INLINE bool	Chip_Clock_IsUSBPLLLocked (void)
	Read PLL1 lock status.
STATIC INLINE void	Chip_Clock_FeedPLL (CHIP_SYSCTL_PLL_T pllNum)
	Feeds a PLL.
void	Chip_Clock_EnablePeriphClock (CHIP_SYSCTL_CLOCK_T clk)
	Enables power and clocking for a peripheral.
void	Chip_Clock_DisablePeriphClock (CHIP_SYSCTL_CLOCK_T clk)
	Disables power and clocking for a peripheral.
bool	Chip_Clock_IsPeripheralClockEnabled (CHIP_SYSCTL_CLOCK_T clk)
	Returns power enables state for a peripheral.
STATIC INLINE void	Chip_Clock_SetEMCClockDiv (CHIP_SYSCTL_EMC_DIV_T emcDiv)
	Selects a EMC divider rate.
STATIC INLINE uint32_t	Chip_Clock_GetEMCClockDiv (void)
	Get EMC divider rate.
void	Chip_Clock_SetCPUClockSource (CHIP_SYSCTL_CCLKSRC_T src)
	Sets the current CPU clock source.
CHIP_SYSCTL_CCLKSRC_T	Chip_Clock_GetCPUClockSource (void)
	Returns the current CPU clock source.
void	Chip_Clock_SetCPUClockDiv (uint32_t div)
	Sets the CPU clock divider.
uint32_t	Chip_Clock_GetCPUClockDiv (void)
	Gets the CPU clock divider.
void	Chip_Clock_SetUSBClockSource (CHIP_SYSCTL_USBCLKSRC_T src)
	Sets the USB clock divider source.
STATIC INLINE CHIP_SYSCTL_USBCLKSRC_T	Chip_Clock_GetUSBClockSource (void)
	Gets the USB clock divider source.
void	Chip_Clock_SetUSBClockDiv (uint32_t div)
	Sets the USB clock divider.
uint32_t	Chip_Clock_GetUSBClockDiv (void)
	Gets the USB clock divider.
STATIC INLINE void	Chip_Clock_SetMainPllSource (CHIP_SYSCTL_PLLCLKSRC_T src)
	Selects a input clock source for SYSCLK.
STATIC INLINE CHIP_SYSCTL_PLLCLKSRC_T	Chip_Clock_GetMainPllSource (void)
	Returns the input clock source for SYSCLK.
STATIC INLINE void	Chip_Clock_SetPCLKDiv (uint32_t div)
	Sets a clock divider for all peripherals.
STATIC INLINE uint32_t	Chip_Clock_GetPCLKDiv (void)
	Gets the clock divider for all peripherals.
void	Chip_Clock_SetSPIFIClockSource (CHIP_SYSCTL_SPIFICLKSRC_T src)
	Sets the SPIFI clock divider source.
STATIC INLINE CHIP_SYSCTL_SPIFICLKSRC_T	Chip_Clock_GetSPIFIClockSource (void)
	Gets the SPIFI clock divider source.
void	Chip_Clock_SetSPIFIClockDiv (uint32_t div)
	Sets the SPIFI clock divider.
STATIC INLINE uint32_t	Chip_Clock_GetSPIFIClockDiv (void)
	Gets the SPIFI clock divider.
STATIC INLINE void	Chip_Clock_SetLCDClockDiv (uint32_t div)
	Set the LCD clock prescaler.
STATIC INLINE uint32_t	Chip_Clock_GetLCDClockDiv (void)
	Get the LCD clock prescaler.
void	Chip_Clock_SetCLKOUTSource (CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div)
	Selects a source clock and divider rate for the CLKOUT pin.
STATIC INLINE void	Chip_Clock_EnableCLKOUT (void)
	Enables the clock on the CLKOUT pin.
STATIC INLINE void	Chip_Clock_DisableCLKOUT (void)
	Disables the clock on the CLKOUT pin.
STATIC INLINE bool	Chip_Clock_IsCLKOUTEnabled (void)
	Returns the CLKOUT activity indication status.
STATIC INLINE uint32_t	Chip_Clock_GetMainOscRate (void)
	Returns the main oscillator clock rate.
STATIC INLINE uint32_t	Chip_Clock_GetIntOscRate (void)
	Returns the internal oscillator (IRC) clock rate.
STATIC INLINE uint32_t	Chip_Clock_GetRTCOscRate (void)
	Returns the RTC oscillator clock rate.
uint32_t	Chip_Clock_GetSYSCLKRate (void)
	Returns the current SYSCLK clock rate.
STATIC INLINE uint32_t	Chip_Clock_GetMainPllInClockRate (void)
	Return Main PLL (PLL0) input clock rate.
uint32_t	Chip_Clock_GetMainPllOutClockRate (void)
	Return PLL0 (Main PLL) output clock rate.
STATIC INLINE uint32_t	Chip_Clock_GetUSBPllInClockRate (void)
	Return USB PLL input clock rate.
uint32_t	Chip_Clock_GetUSBPllOutClockRate (void)
	Return USB PLL output clock rate.
uint32_t	Chip_Clock_GetMainClockRate (void)
	Return main clock rate.
uint32_t	Chip_Clock_GetSystemClockRate (void)
	Return system clock rate.
uint32_t	Chip_Clock_GetUSBClockRate (void)
	Gets the USB clock (USB_CLK) rate.
uint32_t	Chip_Clock_GetSPIFIClockRate (void)
	Returns the SPIFI clock rate.
STATIC INLINE uint32_t	Chip_Clock_GetEMCClockRate (void)
	Returns clock rate for EMC.
uint32_t	Chip_Clock_GetPeripheralClockRate (CHIP_SYSCTL_PCLK_T clk)
	Returns clock rate for a peripheral (from peripheral clock)
STATIC INLINE uint32_t	Chip_Clock_GetRTCClockRate (void)
	Returns clock rate for RTC.
STATIC INLINE uint32_t	Chip_Clock_GetENETClockRate (void)
	Returns clock rate for Ethernet.
STATIC INLINE uint32_t	Chip_Clock_GetGPDMAClockRate (void)
	Returns clock rate for GPDMA.