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clock_17xx_40xx.h
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1 /*
2  * @brief LPC17XX/40XX Clock control functions
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2012
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #ifndef __CLOCK_17XX_40XX_H_
33 #define __CLOCK_17XX_40XX_H_
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
62 #define SYSCTL_OSCRANGE_15_25 (1 << 4)
63 #define SYSCTL_OSCEC (1 << 5)
64 #define SYSCTL_OSCSTAT (1 << 6)
67 #if defined(CHIP_LPC175X_6X)
68 #define SYSCTL_IRC_FREQ (4000000)
69 #else
70 #define SYSCTL_IRC_FREQ (12000000)
71 #endif
72 
73 #define SYSCTL_PLL_ENABLE (1 << 0)
74 #if defined(CHIP_LPC175X_6X)
75 #define SYSCTL_PLL_CONNECT (1 << 1)
76 #endif
77 
86 void Chip_Clock_EnablePLL(CHIP_SYSCTL_PLL_T pllNum, uint32_t flags);
87 
96 void Chip_Clock_DisablePLL(CHIP_SYSCTL_PLL_T pllNum, uint32_t flags);
97 
109 void Chip_Clock_SetupPLL(CHIP_SYSCTL_PLL_T pllNum, uint32_t msel, uint32_t psel);
110 
111 #if defined(CHIP_LPC175X_6X)
112 #define SYSCTL_PLL0STS_ENABLED (1 << 24)
113 #define SYSCTL_PLL0STS_CONNECTED (1 << 25)
114 #define SYSCTL_PLL0STS_LOCKED (1 << 26)
115 #define SYSCTL_PLL1STS_ENABLED (1 << 8)
116 #define SYSCTL_PLL1STS_CONNECTED (1 << 9)
117 #define SYSCTL_PLL1STS_LOCKED (1 << 10)
118 #else
119 #define SYSCTL_PLLSTS_ENABLED (1 << 8)
120 #define SYSCTL_PLLSTS_LOCKED (1 << 10)
121 #endif
122 
129 STATIC INLINE uint32_t Chip_Clock_GetPLLStatus(CHIP_SYSCTL_PLL_T pllNum)
130 {
131  return LPC_SYSCTL->PLL[pllNum].PLLSTAT;
132 }
133 
138 STATIC INLINE bool Chip_Clock_IsMainPLLEnabled(void)
139 {
140 #if defined(CHIP_LPC175X_6X)
141  return (bool) ((LPC_SYSCTL->PLL[0].PLLSTAT & SYSCTL_PLL0STS_ENABLED) != 0);
142 #else
143  return (bool) ((LPC_SYSCTL->PLL[0].PLLSTAT & SYSCTL_PLLSTS_ENABLED) != 0);
144 #endif
145 }
146 
151 STATIC INLINE bool Chip_Clock_IsUSBPLLEnabled(void)
152 {
153 #if defined(CHIP_LPC175X_6X)
154  return (bool) ((LPC_SYSCTL->PLL[1].PLLSTAT & SYSCTL_PLL1STS_ENABLED) != 0);
155 #else
156  return (bool) ((LPC_SYSCTL->PLL[1].PLLSTAT & SYSCTL_PLLSTS_ENABLED) != 0);
157 #endif
158 }
159 
164 STATIC INLINE bool Chip_Clock_IsMainPLLLocked(void)
165 {
166 #if defined(CHIP_LPC175X_6X)
167  return (bool) ((LPC_SYSCTL->PLL[0].PLLSTAT & SYSCTL_PLL0STS_LOCKED) != 0);
168 #else
169  return (bool) ((LPC_SYSCTL->PLL[0].PLLSTAT & SYSCTL_PLLSTS_LOCKED) != 0);
170 #endif
171 }
172 
177 STATIC INLINE bool Chip_Clock_IsUSBPLLLocked(void)
178 {
179 #if defined(CHIP_LPC175X_6X)
180  return (bool) ((LPC_SYSCTL->PLL[1].PLLSTAT & SYSCTL_PLL1STS_LOCKED) != 0);
181 #else
182  return (bool) ((LPC_SYSCTL->PLL[1].PLLSTAT & SYSCTL_PLLSTS_LOCKED) != 0);
183 #endif
184 }
185 
186 #if defined(CHIP_LPC175X_6X)
187 
191 STATIC INLINE bool Chip_Clock_IsMainPLLConnected(void)
192 {
193  return (bool) ((LPC_SYSCTL->PLL[0].PLLSTAT & SYSCTL_PLL0STS_CONNECTED) != 0);
194 }
195 
200 STATIC INLINE bool Chip_Clock_IsUSBPLLConnected(void)
201 {
202  return (bool) ((LPC_SYSCTL->PLL[1].PLLSTAT & SYSCTL_PLL1STS_CONNECTED) != 0);
203 }
204 
205 #endif
206 
212 STATIC INLINE void Chip_Clock_FeedPLL(CHIP_SYSCTL_PLL_T pllNum)
213 {
214  LPC_SYSCTL->PLL[pllNum].PLLFEED = 0xAA;
215  LPC_SYSCTL->PLL[pllNum].PLLFEED = 0x55;
216 }
217 
221 typedef enum CHIP_SYSCTL_CLOCK {
222 #if defined(CHIP_LPC175X_6X)
223  SYSCTL_CLOCK_RSVD0,
224 #else
225  SYSCTL_CLOCK_LCD,
226 #endif
227  SYSCTL_CLOCK_TIMER0,
228  SYSCTL_CLOCK_TIMER1,
229  SYSCTL_CLOCK_UART0,
230  SYSCTL_CLOCK_UART1,
231 #if defined(CHIP_LPC175X_6X)
232  SYSCTL_CLOCK_RSVD5,
233 #else
234  SYSCTL_CLOCK_PWM0,
235 #endif
236  SYSCTL_CLOCK_PWM1,
237  SYSCTL_CLOCK_I2C0,
238 #if defined(CHIP_LPC175X_6X)
239  SYSCTL_CLOCK_SPI,
240 #else
241  SYSCTL_CLOCK_UART4,
242 #endif
243  SYSCTL_CLOCK_RTC,
244  SYSCTL_CLOCK_SSP1,
245 #if defined(CHIP_LPC175X_6X)
246  SYSCTL_CLOCK_RSVD11,
247 #else
248  SYSCTL_CLOCK_EMC,
249 #endif
250  SYSCTL_CLOCK_ADC,
251  SYSCTL_CLOCK_CAN1,
252  SYSCTL_CLOCK_CAN2,
253  SYSCTL_CLOCK_GPIO,
254 #if defined(CHIP_LPC175X_6X)
255  SYSCTL_CLOCK_RIT,
256 #else
257  SYSCTL_CLOCK_SPIFI,
258 #endif
259  SYSCTL_CLOCK_MCPWM,
260  SYSCTL_CLOCK_QEI,
261  SYSCTL_CLOCK_I2C1,
262 #if defined(CHIP_LPC175X_6X)
263  SYSCTL_CLOCK_RSVD20,
264 #else
265  SYSCTL_CLOCK_SSP2,
266 #endif
267  SYSCTL_CLOCK_SSP0,
268  SYSCTL_CLOCK_TIMER2,
269  SYSCTL_CLOCK_TIMER3,
270  SYSCTL_CLOCK_UART2,
271  SYSCTL_CLOCK_UART3,
272  SYSCTL_CLOCK_I2C2,
273  SYSCTL_CLOCK_I2S,
274 #if defined(CHIP_LPC175X_6X)
275  SYSCTL_CLOCK_RSVD28,
276 #else
277  SYSCTL_CLOCK_SDC,
278 #endif
279  SYSCTL_CLOCK_GPDMA,
280  SYSCTL_CLOCK_ENET,
281  SYSCTL_CLOCK_USB,
282  SYSCTL_CLOCK_RSVD32,
283  SYSCTL_CLOCK_RSVD33,
284  SYSCTL_CLOCK_RSVD34,
285 #if defined(CHIP_LPC407X_8X)
286  SYSCTL_CLOCK_CMP,
287 #else
288  SYSCTL_CLOCK_RSVD35,
289 #endif
290 } CHIP_SYSCTL_CLOCK_T;
291 
301 void Chip_Clock_EnablePeriphClock(CHIP_SYSCTL_CLOCK_T clk);
302 
312 void Chip_Clock_DisablePeriphClock(CHIP_SYSCTL_CLOCK_T clk);
313 
319 bool Chip_Clock_IsPeripheralClockEnabled(CHIP_SYSCTL_CLOCK_T clk);
320 
321 #if !defined(CHIP_LPC175X_6X)
322 
325 typedef enum CHIP_SYSCTL_EMC_DIV {
326  SYSCTL_EMC_DIV1 = 0,
327  SYSCTL_EMC_DIV2 = 1,
328 } CHIP_SYSCTL_EMC_DIV_T;
329 
340 STATIC INLINE void Chip_Clock_SetEMCClockDiv(CHIP_SYSCTL_EMC_DIV_T emcDiv)
341 {
342  LPC_SYSCTL->EMCCLKSEL = (uint32_t) emcDiv;
343 }
344 
349 STATIC INLINE uint32_t Chip_Clock_GetEMCClockDiv(void)
350 {
351  return ((uint32_t) LPC_SYSCTL->EMCCLKSEL) + 1;
352 }
353 
354 #endif
355 
359 typedef enum CHIP_SYSCTL_CCLKSRC {
360  SYSCTL_CCLKSRC_SYSCLK,
361  SYSCTL_CCLKSRC_MAINPLL,
362 } CHIP_SYSCTL_CCLKSRC_T;
363 
371 void Chip_Clock_SetCPUClockSource(CHIP_SYSCTL_CCLKSRC_T src);
372 
379 CHIP_SYSCTL_CCLKSRC_T Chip_Clock_GetCPUClockSource(void);
380 
390 void Chip_Clock_SetCPUClockDiv(uint32_t div);
391 
400 uint32_t Chip_Clock_GetCPUClockDiv(void);
401 
402 #if !defined(CHIP_LPC175X_6X)
403 
407 typedef enum CHIP_SYSCTL_USBCLKSRC {
408  SYSCTL_USBCLKSRC_SYSCLK,
409  SYSCTL_USBCLKSRC_MAINPLL,
410  SYSCTL_USBCLKSRC_USBPLL,
411  SYSCTL_USBCLKSRC_RESERVED
412 } CHIP_SYSCTL_USBCLKSRC_T;
413 
422 void Chip_Clock_SetUSBClockSource(CHIP_SYSCTL_USBCLKSRC_T src);
423 
428 STATIC INLINE CHIP_SYSCTL_USBCLKSRC_T Chip_Clock_GetUSBClockSource(void)
429 {
430  return (CHIP_SYSCTL_USBCLKSRC_T) ((LPC_SYSCTL->USBCLKSEL >> 8) & 0x3);
431 }
432 
433 #endif /* !defined(CHIP_LPC175X_6X)*/
434 
441 void Chip_Clock_SetUSBClockDiv(uint32_t div);
442 
448 uint32_t Chip_Clock_GetUSBClockDiv(void);
449 
453 typedef enum CHIP_SYSCTL_PLLCLKSRC {
454  SYSCTL_PLLCLKSRC_IRC,
455  SYSCTL_PLLCLKSRC_MAINOSC,
456 #if defined(CHIP_LPC175X_6X)
457  SYSCTL_PLLCLKSRC_RTC,
458 #else
459  SYSCTL_PLLCLKSRC_RESERVED1,
460 #endif
461  SYSCTL_PLLCLKSRC_RESERVED2
462 } CHIP_SYSCTL_PLLCLKSRC_T;
463 
471 STATIC INLINE void Chip_Clock_SetMainPllSource(CHIP_SYSCTL_PLLCLKSRC_T src)
472 {
473  LPC_SYSCTL->CLKSRCSEL = src;
474 }
475 
480 STATIC INLINE CHIP_SYSCTL_PLLCLKSRC_T Chip_Clock_GetMainPllSource(void)
481 {
482  return (CHIP_SYSCTL_PLLCLKSRC_T) (LPC_SYSCTL->CLKSRCSEL & 0x3);
483 }
484 
485 #if defined(CHIP_LPC175X_6X)
486 
490 typedef enum {
491  SYSCTL_CLKDIV_4,
492  SYSCTL_CLKDIV_1,
493  SYSCTL_CLKDIV_2,
494  SYSCTL_CLKDIV_8,
495  SYSCTL_CLKDIV_6_CCAN = SYSCTL_CLKDIV_8
496 } CHIP_SYSCTL_CLKDIV_T;
497 
502 typedef enum {
503  SYSCTL_PCLK_WDT,
504  SYSCTL_PCLK_TIMER0,
505  SYSCTL_PCLK_TIMER1,
506  SYSCTL_PCLK_UART0,
507  SYSCTL_PCLK_UART1,
508  SYSCTL_PCLK_RSVD5,
509  SYSCTL_PCLK_PWM1,
510  SYSCTL_PCLK_I2C0,
511  SYSCTL_PCLK_SPI,
512  SYSCTL_PCLK_RSVD9,
513  SYSCTL_PCLK_SSP1,
514  SYSCTL_PCLK_DAC,
515  SYSCTL_PCLK_ADC,
516  SYSCTL_PCLK_CAN1,
517  SYSCTL_PCLK_CAN2,
518  SYSCTL_PCLK_ACF,
519  SYSCTL_PCLK_QEI,
520  SYSCTL_PCLK_GPIOINT,
521  SYSCTL_PCLK_PCB,
522  SYSCTL_PCLK_I2C1,
523  SYSCTL_PCLK_RSVD20,
524  SYSCTL_PCLK_SSP0,
525  SYSCTL_PCLK_TIMER2,
526  SYSCTL_PCLK_TIMER3,
527  SYSCTL_PCLK_UART2,
528  SYSCTL_PCLK_UART3,
529  SYSCTL_PCLK_I2C2,
530  SYSCTL_PCLK_I2S,
531  SYSCTL_PCLK_RSVD28,
532  SYSCTL_PCLK_RIT,
533  SYSCTL_PCLK_SYSCON,
534  SYSCTL_PCLK_MCPWM
535 } CHIP_SYSCTL_PCLK_T;
536 
548 void Chip_Clock_SetPCLKDiv(CHIP_SYSCTL_PCLK_T clk, CHIP_SYSCTL_CLKDIV_T div);
549 
560 uint32_t Chip_Clock_GetPCLKDiv(CHIP_SYSCTL_PCLK_T clk);
561 
562 #else
563 
571 STATIC INLINE void Chip_Clock_SetPCLKDiv(uint32_t div)
572 {
573  LPC_SYSCTL->PCLKSEL = div;
574 }
575 
582 STATIC INLINE uint32_t Chip_Clock_GetPCLKDiv(void)
583 {
584  return LPC_SYSCTL->PCLKSEL & 0x1F;
585 }
586 
587 #endif
588 
589 #if !defined(CHIP_LPC175X_6X)
590 
593 typedef enum CHIP_SYSCTL_SPIFICLKSRC {
594  SYSCTL_SPIFICLKSRC_SYSCLK,
595  SYSCTL_SPIFICLKSRC_MAINPLL,
596  SYSCTL_SPIFICLKSRC_USBPLL,
597  SYSCTL_SPIFICLKSRC_RESERVED
598 } CHIP_SYSCTL_SPIFICLKSRC_T;
599 
605 void Chip_Clock_SetSPIFIClockSource(CHIP_SYSCTL_SPIFICLKSRC_T src);
606 
611 STATIC INLINE CHIP_SYSCTL_SPIFICLKSRC_T Chip_Clock_GetSPIFIClockSource(void)
612 {
613  return (CHIP_SYSCTL_SPIFICLKSRC_T) ((LPC_SYSCTL->SPIFICLKSEL >> 8) & 0x3);
614 }
615 
622 void Chip_Clock_SetSPIFIClockDiv(uint32_t div);
623 
629 STATIC INLINE uint32_t Chip_Clock_GetSPIFIClockDiv(void)
630 {
631  return LPC_SYSCTL->SPIFICLKSEL & 0x1F;
632 }
633 
639 STATIC INLINE void Chip_Clock_SetLCDClockDiv(uint32_t div)
640 {
641  LPC_SYSCTL->LCD_CFG = (div - 1);
642 }
643 
648 STATIC INLINE uint32_t Chip_Clock_GetLCDClockDiv(void)
649 {
650  return (LPC_SYSCTL->LCD_CFG & 0x1F) + 1;
651 }
652 
653 #endif
654 
658 typedef enum {
659  SYSCTL_CLKOUTSRC_CPU,
660  SYSCTL_CLKOUTSRC_MAINOSC,
661  SYSCTL_CLKOUTSRC_IRC,
662  SYSCTL_CLKOUTSRC_USB,
663  SYSCTL_CLKOUTSRC_RTC,
664 #if defined(CHIP_LPC175X_6X)
665  SYSCTL_CLKOUTSRC_RESERVED1,
666  SYSCTL_CLKOUTSRC_RESERVED2,
667 #else
668  SYSCTL_CLKOUTSRC_SPIFI,
669  SYSCTL_CLKOUTSRC_WATCHDOGOSC,
670 #endif
671  SYSCTL_CLKOUTSRC_RESERVED3
672 } CHIP_SYSCTL_CLKOUTSRC_T;
673 
683 void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div);
684 
689 STATIC INLINE void Chip_Clock_EnableCLKOUT(void)
690 {
691  LPC_SYSCTL->CLKOUTCFG |= (1 << 8);
692 }
693 
698 STATIC INLINE void Chip_Clock_DisableCLKOUT(void)
699 {
700  LPC_SYSCTL->CLKOUTCFG &= ~(1 << 8);
701 }
702 
710 STATIC INLINE bool Chip_Clock_IsCLKOUTEnabled(void)
711 {
712  return (bool) ((LPC_SYSCTL->CLKOUTCFG & (1 << 9)) != 0);
713 }
714 
719 STATIC INLINE uint32_t Chip_Clock_GetMainOscRate(void)
720 {
721  return CRYSTAL_MAIN_FREQ_IN;
722 }
723 
728 STATIC INLINE uint32_t Chip_Clock_GetIntOscRate(void)
729 {
730  return SYSCTL_IRC_FREQ;
731 }
732 
737 STATIC INLINE uint32_t Chip_Clock_GetRTCOscRate(void)
738 {
739  return CRYSTAL_32K_FREQ_IN;
740 }
741 
748 uint32_t Chip_Clock_GetSYSCLKRate(void);
749 
754 STATIC INLINE uint32_t Chip_Clock_GetMainPllInClockRate(void)
755 {
756  return Chip_Clock_GetSYSCLKRate();
757 }
758 
763 uint32_t Chip_Clock_GetMainPllOutClockRate(void);
764 
769 STATIC INLINE uint32_t Chip_Clock_GetUSBPllInClockRate(void)
770 {
771  return Chip_Clock_GetMainOscRate();
772 }
773 
778 uint32_t Chip_Clock_GetUSBPllOutClockRate(void);
779 
784 uint32_t Chip_Clock_GetMainClockRate(void);
785 
790 uint32_t Chip_Clock_GetSystemClockRate(void);
791 
797 uint32_t Chip_Clock_GetUSBClockRate(void);
798 
799 #if !defined(CHIP_LPC175X_6X)
800 
805 uint32_t Chip_Clock_GetSPIFIClockRate(void);
806 
811 STATIC INLINE uint32_t Chip_Clock_GetEMCClockRate(void)
812 {
813  return Chip_Clock_GetSystemClockRate() / Chip_Clock_GetEMCClockDiv();
814 }
815 
816 #endif
817 
818 #if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC407X_8X)
819 
828 uint32_t Chip_Clock_GetPeripheralClockRate(void);
829 
830 #else
831 
840 uint32_t Chip_Clock_GetPeripheralClockRate(CHIP_SYSCTL_PCLK_T clk);
841 
846 STATIC INLINE uint32_t Chip_Clock_GetRTCClockRate(void)
847 {
848  return Chip_Clock_GetSystemClockRate() / 8;
849 }
850 
851 #endif
852 
857 STATIC INLINE uint32_t Chip_Clock_GetENETClockRate(void)
858 {
859  return Chip_Clock_GetSystemClockRate();
860 }
861 
866 STATIC INLINE uint32_t Chip_Clock_GetGPDMAClockRate(void)
867 {
868  return Chip_Clock_GetSystemClockRate();
869 }
870 
875 #ifdef __cplusplus
876 }
877 #endif
878 
879 #endif /* __CLOCK_17XX_40XX_H_ */