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crc_001.h
Go to the documentation of this file.
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/*
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* @brief Cyclic Redundancy Check (CRC) registers and driver functions
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __CRC_001_H_
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#define __CRC_001_H_
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#include "sys_config.h"
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#include "cmsis.h"
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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typedef
struct
{
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__IO
uint32_t
MODE
;
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__IO
uint32_t
SEED
;
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union
{
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__I
uint32_t
SUM
;
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__O
uint32_t
WRDATA32
;
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__O uint16_t
WRDATA16
;
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__O uint8_t
WRDATA8
;
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};
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}
IP_CRC_001_T
;
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#define CRC_MODE_POLY_BITMASK ((0x03))
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#define CRC_MODE_POLY_CCITT (0x00)
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#define CRC_MODE_POLY_CRC16 (0x01)
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#define CRC_MODE_POLY_CRC32 (0x02)
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#define CRC_MODE_WRDATA_BITMASK (0x03 << 2)
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#define CRC_MODE_WRDATA_BIT_RVS (1 << 2)
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#define CRC_MODE_WRDATA_CMPL (1 << 3)
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#define CRC_MODE_SUM_BITMASK (0x03 << 4)
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#define CRC_MODE_SUM_BIT_RVS (1 << 4)
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#define CRC_MODE_SUM_CMPL (1 << 5)
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#define MODE_CFG_CCITT (0x00)
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#define MODE_CFG_CRC16 (0x15)
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#define MODE_CFG_CRC32 (0x36)
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#define CRC_SEED_CCITT (0x0000FFFF)
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#define CRC_SEED_CRC16 (0x00000000)
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#define CRC_SEED_CRC32 (0xFFFFFFFF)
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/*
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* @brief CRC polynomial
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*/
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typedef
enum
IP_CRC_001_POLY {
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CRC_POLY_CCITT
=
CRC_MODE_POLY_CCITT
,
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CRC_POLY_CRC16
=
CRC_MODE_POLY_CRC16
,
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CRC_POLY_CRC32
=
CRC_MODE_POLY_CRC32
,
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CRC_POLY_LAST
,
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}
IP_CRC_001_POLY_T
;
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STATIC
INLINE
void
IP_CRC_Init
(
IP_CRC_001_T
*pCRC) {}
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STATIC
INLINE
void
IP_CRC_DeInit
(
IP_CRC_001_T
*pCRC) {}
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STATIC
INLINE
void
IP_CRC_SetPoly
(
IP_CRC_001_T
*pCRC,
IP_CRC_001_POLY_T
poly,
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uint32_t
flags)
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{
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pCRC->
MODE
= (
uint32_t
) poly | flags;
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}
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void
IP_CRC_UseDefaultConfig
(
IP_CRC_001_T
*pCRC,
IP_CRC_001_POLY_T
poly);
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STATIC
INLINE
uint32_t
IP_CRC_GetMode
(
IP_CRC_001_T
*pCRC)
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{
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return
pCRC->
MODE
;
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}
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STATIC
INLINE
void
IP_CRC_SetMode
(
IP_CRC_001_T
*pCRC,
uint32_t
mode)
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{
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pCRC->
MODE
= mode;
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}
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STATIC
INLINE
void
IP_CRC_SetSeed
(
IP_CRC_001_T
*pCRC,
uint32_t
Seed)
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{
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pCRC->
SEED
= Seed;
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}
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STATIC
INLINE
uint32_t
IP_CRC_GetSeed
(
IP_CRC_001_T
*pCRC)
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{
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return
pCRC->
SEED
;
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}
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STATIC
INLINE
void
IP_CRC_Write8
(
IP_CRC_001_T
*pCRC, uint8_t data)
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{
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pCRC->
WRDATA8
= data;
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}
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STATIC
INLINE
void
IP_CRC_Write16
(
IP_CRC_001_T
*pCRC, uint16_t data)
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{
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pCRC->
WRDATA16
= (
uint32_t
) data;
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}
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STATIC
INLINE
void
IP_CRC_Write32
(
IP_CRC_001_T
*pCRC,
uint32_t
data)
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{
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pCRC->
WRDATA32
= data;
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}
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STATIC
INLINE
uint32_t
IP_CRC_ReadSum
(
IP_CRC_001_T
*pCRC)
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{
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return
pCRC->
SUM
;
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}
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uint32_t
IP_CRC_CRC8
(
IP_CRC_001_T
*pCRC,
const
uint8_t *data,
uint32_t
bytes
);
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uint32_t
IP_CRC_CRC16
(
IP_CRC_001_T
*pCRC,
const
uint16_t *data,
uint32_t
hwords);
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uint32_t
IP_CRC_CRC32
(
IP_CRC_001_T
*pCRC,
const
uint32_t
*data,
uint32_t
words
);
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#ifdef __cplusplus
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}
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#endif
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#endif
/* __CRC_001_H_ */
software
lpc_core
lpc_ip
crc_001.h
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