LPCOpen Platform  v1.03
LPCOpen Platform for NXP LPC Microcontrollers
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Data Structures | Macros | Functions
CHIP: LPC18xx/43xx General Purpose DMA driver
LPC18xx/43xx chip specific drivers

Detailed Description

Data Structures

struct  DMA_ChannelHandle_t
 DMA channel handle structure. More...
 
struct  DMA_TransferDescriptor_t
 Transfer Descriptor structure typedef. More...
 

Macros

#define GPDMA_NUMBER_CHANNELS   8
 Number of channels on GPDMA.
 
#define GPDMA_CONN_MEMORY   ((0UL))
 GPDMA request connections.
 
#define GPDMA_CONN_MAT0_0   ((1UL))
 
#define GPDMA_CONN_UART0_Tx   ((2UL))
 
#define GPDMA_CONN_MAT0_1   ((3UL))
 
#define GPDMA_CONN_UART0_Rx   ((4UL))
 
#define GPDMA_CONN_MAT1_0   ((5UL))
 
#define GPDMA_CONN_UART1_Tx   ((6UL))
 
#define GPDMA_CONN_MAT1_1   ((7UL))
 
#define GPDMA_CONN_UART1_Rx   ((8UL))
 
#define GPDMA_CONN_MAT2_0   ((9UL))
 
#define GPDMA_CONN_UART2_Tx   ((10UL))
 
#define GPDMA_CONN_MAT2_1   ((11UL))
 
#define GPDMA_CONN_UART2_Rx   ((12UL))
 
#define GPDMA_CONN_MAT3_0   ((13UL))
 
#define GPDMA_CONN_UART3_Tx   ((14UL))
 
#define GPDMA_CONN_SCT_0   ((15UL))
 
#define GPDMA_CONN_MAT3_1   ((16UL))
 
#define GPDMA_CONN_UART3_Rx   ((17UL))
 
#define GPDMA_CONN_SCT_1   ((18UL))
 
#define GPDMA_CONN_SSP0_Rx   ((19UL))
 
#define GPDMA_CONN_I2S_Tx_Channel_0   ((20UL))
 
#define GPDMA_CONN_SSP0_Tx   ((21UL))
 
#define GPDMA_CONN_I2S_Rx_Channel_1   ((22UL))
 
#define GPDMA_CONN_SSP1_Rx   ((23UL))
 
#define GPDMA_CONN_SSP1_Tx   ((24UL))
 
#define GPDMA_CONN_ADC_0   ((25UL))
 
#define GPDMA_CONN_ADC_1   ((26UL))
 
#define GPDMA_CONN_DAC   ((27UL))
 
#define GPDMA_CONN_I2S_Tx_Channel_1   ((28UL))
 
#define GPDMA_CONN_I2S_Rx_Channel_0   ((29UL))
 
#define GPDMA_BSIZE_1   ((0UL))
 GPDMA Burst size in Source and Destination definitions.
 
#define GPDMA_BSIZE_4   ((1UL))
 
#define GPDMA_BSIZE_8   ((2UL))
 
#define GPDMA_BSIZE_16   ((3UL))
 
#define GPDMA_BSIZE_32   ((4UL))
 
#define GPDMA_BSIZE_64   ((5UL))
 
#define GPDMA_BSIZE_128   ((6UL))
 
#define GPDMA_BSIZE_256   ((7UL))
 
#define GPDMA_WIDTH_BYTE   ((0UL))
 Width in Source transfer width and Destination transfer width definitions.
 
#define GPDMA_WIDTH_HALFWORD   ((1UL))
 
#define GPDMA_WIDTH_WORD   ((2UL))
 
#define DMA_CONTROLLER   0
 Flow control definitions.
 
#define SRC_PER_CONTROLLER   1
 
#define DST_PER_CONTROLLER   2
 

Functions

STATIC INLINE IntStatus Chip_GPDMA_IntGetStatus (LPC_GPDMA_T *pGPDMA, IP_GPDMA_STATUS_T type, uint8_t channel)
 Read the status from different registers according to the type.
 
STATIC INLINE void Chip_GPDMA_ClearIntPending (LPC_GPDMA_T *pGPDMA, IP_GPDMA_STATECLEAR_T type, uint8_t channel)
 Clear the Interrupt Flag from different registers according to the type.
 
STATIC INLINE void Chip_GPDMA_ChannelCmd (LPC_GPDMA_T *pGPDMA, uint8_t channelNum, FunctionalState NewState)
 Enable or Disable the GPDMA Channel.
 
void Chip_GPDMA_Init (LPC_GPDMA_T *pGPDMA)
 Initialize the GPDMA.
 
void Chip_GPDMA_DeInit (LPC_GPDMA_T *pGPDMA)
 Shutdown the GPDMA.
 
void Chip_DMA_Stop (LPC_GPDMA_T *pGPDMA, uint8_t ChannelNum)
 Stop a stream DMA transfer.
 
Status Chip_DMA_Interrupt (LPC_GPDMA_T *pGPDMA, uint8_t ChannelNum)
 The GPDMA stream interrupt status checking.
 
uint8_t Chip_DMA_GetFreeChannel (LPC_GPDMA_T *pGPDMA, uint32_t PeripheralConnection_ID)
 Get a free GPDMA channel for one DMA connection.
 
Status Chip_DMA_Transfer (LPC_GPDMA_T *pGPDMA, uint8_t ChannelNum, uint32_t src, uint32_t dst, IP_GPDMA_FLOW_CONTROL_T TransferType, uint32_t Size)
 Do a DMA transfer M2M, M2P,P2M or P2P.
 
Status Chip_DMA_SGTransfer (LPC_GPDMA_T *pGPDMA, uint8_t ChannelNum, const DMA_TransferDescriptor_t *DMADescriptor, IP_GPDMA_FLOW_CONTROL_T TransferType)
 Do a DMA transfer using linked list of descriptors.
 
Status Chip_DMA_PrepareDescriptor (LPC_GPDMA_T *pGPDMA, DMA_TransferDescriptor_t *DMADescriptor, uint32_t src, uint32_t dst, uint32_t Size, IP_GPDMA_FLOW_CONTROL_T TransferType, const DMA_TransferDescriptor_t *NextDescriptor)
 Prepare a single DMA descriptor.
 
int Chip_DMA_InitChannelCfg (LPC_GPDMA_T *pGPDMA, GPDMA_Channel_CFG_T *GPDMACfg, uint8_t ChannelNum, uint32_t src, uint32_t dst, uint32_t Size, IP_GPDMA_FLOW_CONTROL_T TransferType)
 Initialize channel configuration strucutre.
 

Macro Definition Documentation

#define DMA_CONTROLLER   0

Flow control definitions.

Flow control is DMA controller

Definition at line 105 of file gpdma_18xx_43xx.h.

#define DST_PER_CONTROLLER   2

Flow control is Destination peripheral controller

Definition at line 107 of file gpdma_18xx_43xx.h.

#define GPDMA_BSIZE_1   ((0UL))

GPDMA Burst size in Source and Destination definitions.

Burst size = 1

Definition at line 86 of file gpdma_18xx_43xx.h.

#define GPDMA_BSIZE_128   ((6UL))

Burst size = 128

Definition at line 92 of file gpdma_18xx_43xx.h.

#define GPDMA_BSIZE_16   ((3UL))

Burst size = 16

Definition at line 89 of file gpdma_18xx_43xx.h.

#define GPDMA_BSIZE_256   ((7UL))

Burst size = 256

Definition at line 93 of file gpdma_18xx_43xx.h.

#define GPDMA_BSIZE_32   ((4UL))

Burst size = 32

Definition at line 90 of file gpdma_18xx_43xx.h.

#define GPDMA_BSIZE_4   ((1UL))

Burst size = 4

Definition at line 87 of file gpdma_18xx_43xx.h.

#define GPDMA_BSIZE_64   ((5UL))

Burst size = 64

Definition at line 91 of file gpdma_18xx_43xx.h.

#define GPDMA_BSIZE_8   ((2UL))

Burst size = 8

Definition at line 88 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_ADC_0   ((25UL))

ADC 0

Definition at line 77 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_ADC_1   ((26UL))

ADC 1

Definition at line 78 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_DAC   ((27UL))

DAC

Definition at line 79 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_I2S_Rx_Channel_0   ((29UL))

I2S channel 0

Definition at line 81 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_I2S_Rx_Channel_1   ((22UL))

I2S channel 1

Definition at line 74 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_I2S_Tx_Channel_0   ((20UL))

I2S channel 0

Definition at line 72 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_I2S_Tx_Channel_1   ((28UL))

I2S channel 0

Definition at line 80 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_MAT0_0   ((1UL))

MAT0.0

Definition at line 53 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_MAT0_1   ((3UL))

MAT0.1

Definition at line 55 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_MAT1_0   ((5UL))

MAT1.0

Definition at line 57 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_MAT1_1   ((7UL))

MAT1.1

Definition at line 59 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_MAT2_0   ((9UL))

MAT2.0

Definition at line 61 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_MAT2_1   ((11UL))

MAT2.1

Definition at line 63 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_MAT3_0   ((13UL))

MAT3.0

Definition at line 65 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_MAT3_1   ((16UL))

MAT3.1

Definition at line 68 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_MEMORY   ((0UL))

GPDMA request connections.

MEMORY

Definition at line 52 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_SCT_0   ((15UL))

SCT timer channel 0

Definition at line 67 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_SCT_1   ((18UL))

SCT timer channel 1

Definition at line 70 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_SSP0_Rx   ((19UL))

SSP0 Rx

Definition at line 71 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_SSP0_Tx   ((21UL))

SSP0 Tx

Definition at line 73 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_SSP1_Rx   ((23UL))

SSP1 Rx

Definition at line 75 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_SSP1_Tx   ((24UL))

SSP1 Tx

Definition at line 76 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_UART0_Rx   ((4UL))

UART0 Rx

Definition at line 56 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_UART0_Tx   ((2UL))

UART0 Tx

Definition at line 54 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_UART1_Rx   ((8UL))

UART1 Rx

Definition at line 60 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_UART1_Tx   ((6UL))

UART1 Tx

Definition at line 58 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_UART2_Rx   ((12UL))

UART2 Rx

Definition at line 64 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_UART2_Tx   ((10UL))

UART2 Tx

Definition at line 62 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_UART3_Rx   ((17UL))

UART3 Rx

Definition at line 69 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_UART3_Tx   ((14UL))

UART3 Tx

Definition at line 66 of file gpdma_18xx_43xx.h.

#define GPDMA_NUMBER_CHANNELS   8

Number of channels on GPDMA.

Definition at line 47 of file gpdma_18xx_43xx.h.

#define GPDMA_WIDTH_BYTE   ((0UL))

Width in Source transfer width and Destination transfer width definitions.

Width = 1 byte

Definition at line 98 of file gpdma_18xx_43xx.h.

#define GPDMA_WIDTH_HALFWORD   ((1UL))

Width = 2 bytes

Definition at line 99 of file gpdma_18xx_43xx.h.

#define GPDMA_WIDTH_WORD   ((2UL))

Width = 4 bytes

Definition at line 100 of file gpdma_18xx_43xx.h.

#define SRC_PER_CONTROLLER   1

Flow control is Source peripheral controller

Definition at line 106 of file gpdma_18xx_43xx.h.

Function Documentation

uint8_t Chip_DMA_GetFreeChannel ( LPC_GPDMA_T *  pGPDMA,
uint32_t  PeripheralConnection_ID 
)

Get a free GPDMA channel for one DMA connection.

Parameters
pGPDMA: The base of GPDMA on the chip
PeripheralConnection_ID: Some chip fix each peripheral DMA connection on a specified channel ( have not used in 18xx/43xx )
Returns
The channel number which is selected
Parameters
pGPDMA: The base of GPDMA on the chip
PeripheralConnection_ID: Some chip fix each peripheral DMA connection on a specified channel ( have not used in 17xx/40xx )
Returns
The channel number which is selected

Definition at line 517 of file gpdma_17xx_40xx.c.

int Chip_DMA_InitChannelCfg ( LPC_GPDMA_T *  pGPDMA,
GPDMA_Channel_CFG_T *  GPDMACfg,
uint8_t  ChannelNum,
uint32_t  src,
uint32_t  dst,
uint32_t  Size,
IP_GPDMA_FLOW_CONTROL_T  TransferType 
)

Initialize channel configuration strucutre.

Parameters
pGPDMA: The base of GPDMA on the chip
GPDMACfg: Pointer to configuration structure to be initialized
ChannelNum: Channel used for transfer must be obtained using Chip_DMA_GetFreeChannel()
src: Address of Memory or one of PeripheralConnection_ID , which is the source
dst: Address of Memory or one of PeripheralConnection_ID , which is the destination
Size: The number of DMA transfers
TransferType: Select the transfer controller and the type of transfer. (See, IP_GPDMA_FLOW_CONTROL_T)
Returns
ERROR on error, SUCCESS on success

Definition at line 336 of file gpdma_17xx_40xx.c.

Status Chip_DMA_Interrupt ( LPC_GPDMA_T *  pGPDMA,
uint8_t  ChannelNum 
)

The GPDMA stream interrupt status checking.

Parameters
pGPDMA: The base of GPDMA on the chip
ChannelNum: Channel Number to be checked on interruption
Returns
Status:
  • SUCCESS : DMA transfer success
  • ERROR : DMA transfer failed

Definition at line 314 of file gpdma_17xx_40xx.c.

Status Chip_DMA_PrepareDescriptor ( LPC_GPDMA_T *  pGPDMA,
DMA_TransferDescriptor_t *  DMADescriptor,
uint32_t  src,
uint32_t  dst,
uint32_t  Size,
IP_GPDMA_FLOW_CONTROL_T  TransferType,
const DMA_TransferDescriptor_t *  NextDescriptor 
)

Prepare a single DMA descriptor.

Parameters
pGPDMA: The base of GPDMA on the chip
DMADescriptor: DMA Descriptor to be initialized
src: Address of Memory or one of PeripheralConnection_ID , which is the source
dst: Address of Memory or one of PeripheralConnection_ID , which is the destination
Size: The number of DMA transfers
TransferType: Select the transfer controller and the type of transfer. (See, IP_GPDMA_FLOW_CONTROL_T)
NextDescriptor: Pointer to next descriptor (0 if no more descriptors available)
Returns
ERROR on error, SUCCESS on success

Definition at line 433 of file gpdma_17xx_40xx.c.

Status Chip_DMA_SGTransfer ( LPC_GPDMA_T *  pGPDMA,
uint8_t  ChannelNum,
const DMA_TransferDescriptor_t *  DMADescriptor,
IP_GPDMA_FLOW_CONTROL_T  TransferType 
)

Do a DMA transfer using linked list of descriptors.

Parameters
pGPDMA: The base of GPDMA on the chip
ChannelNum: Channel used for transfer must be obtained using Chip_DMA_GetFreeChannel()
DMADescriptor: First node in the linked list of descriptors
TransferType: Select the transfer controller and the type of transfer. (See, IP_GPDMA_FLOW_CONTROL_T)
Returns
ERROR on error, SUCCESS on success

Definition at line 476 of file gpdma_17xx_40xx.c.

void Chip_DMA_Stop ( LPC_GPDMA_T *  pGPDMA,
uint8_t  ChannelNum 
)

Stop a stream DMA transfer.

Parameters
pGPDMA: The base of GPDMA on the chip
ChannelNum: Channel Number to be closed
Returns
Nothing

Definition at line 298 of file gpdma_17xx_40xx.c.

Status Chip_DMA_Transfer ( LPC_GPDMA_T *  pGPDMA,
uint8_t  ChannelNum,
uint32_t  src,
uint32_t  dst,
IP_GPDMA_FLOW_CONTROL_T  TransferType,
uint32_t  Size 
)

Do a DMA transfer M2M, M2P,P2M or P2P.

Parameters
pGPDMA: The base of GPDMA on the chip
ChannelNum: Channel used for transfer
src: Address of Memory or PeripheralConnection_ID which is the source
dst: Address of Memory or PeripheralConnection_ID which is the destination
TransferType,:Select the transfer controller and the type of transfer. Should be:
  • GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA
  • GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA
  • GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA
  • GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA
  • GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL
  • GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL
  • GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL
  • GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL
Size: The number of DMA transfers
Returns
ERROR on error, SUCCESS on success

Definition at line 387 of file gpdma_17xx_40xx.c.

STATIC INLINE void Chip_GPDMA_ChannelCmd ( LPC_GPDMA_T *  pGPDMA,
uint8_t  channelNum,
FunctionalState  NewState 
)

Enable or Disable the GPDMA Channel.

Parameters
pGPDMA: The base of GPDMA on the chip
channelNum: The GPDMA channel : 0 - 7
NewState: ENABLE to enable GPDMA or DISABLE to disable GPDMA
Returns
Nothing

Definition at line 165 of file gpdma_18xx_43xx.h.

STATIC INLINE void Chip_GPDMA_ClearIntPending ( LPC_GPDMA_T *  pGPDMA,
IP_GPDMA_STATECLEAR_T  type,
uint8_t  channel 
)

Clear the Interrupt Flag from different registers according to the type.

Parameters
pGPDMA: The base of GPDMA on the chip
type: Flag mode, should be:
  • GPDMA_STATCLR_INTTC : GPDMA Interrupt Terminal Count Request
  • GPDMA_STATCLR_INTERR : GPDMA Interrupt Error
channel: The GPDMA channel : 0 - 7
Returns
Nothing

Definition at line 153 of file gpdma_18xx_43xx.h.

void Chip_GPDMA_DeInit ( LPC_GPDMA_T *  pGPDMA)

Shutdown the GPDMA.

Parameters
pGPDMA: The base of GPDMA on the chip
Returns
Nothing

Definition at line 292 of file gpdma_17xx_40xx.c.

void Chip_GPDMA_Init ( LPC_GPDMA_T *  pGPDMA)

Initialize the GPDMA.

Parameters
pGPDMA: The base of GPDMA on the chip
Returns
Nothing

Definition at line 276 of file gpdma_17xx_40xx.c.

STATIC INLINE IntStatus Chip_GPDMA_IntGetStatus ( LPC_GPDMA_T *  pGPDMA,
IP_GPDMA_STATUS_T  type,
uint8_t  channel 
)

Read the status from different registers according to the type.

Parameters
pGPDMA: The base of GPDMA on the chip
type: Status mode, should be:
  • GPDMA_STAT_INT : GPDMA Interrupt Status
  • GPDMA_STAT_INTTC : GPDMA Interrupt Terminal Count Request Status
  • GPDMA_STAT_INTERR : GPDMA Interrupt Error Status
  • GPDMA_STAT_RAWINTTC : GPDMA Raw Interrupt Terminal Count Status
  • GPDMA_STAT_RAWINTERR : GPDMA Raw Error Interrupt Status
  • GPDMA_STAT_ENABLED_CH : GPDMA Enabled Channel Status
channel: The GPDMA channel : 0 - 7
Returns
SET is interrupt is pending or RESET if not pending

Definition at line 139 of file gpdma_18xx_43xx.h.