Detailed Description

General Purpose DMA

Data Structures
struct	IP_GPDMA_001_CH_T
	GPDMA Channel register block structure. More...

struct	IP_GPDMA_001_T
	GPDMA register block. More...

struct	GPDMA_Channel_CFG_T
	GPDMA structure using for DMA configuration. More...

Macros
#define	GPDMA_CHANNELS 8

#define	GPDMA_DMACCxControl_TransferSize(n) (((n & 0xFFF) << 0))
	Macro defines for DMA channel control registers.

#define	GPDMA_DMACCxControl_SBSize(n) (((n & 0x07) << 12))

#define	GPDMA_DMACCxControl_DBSize(n) (((n & 0x07) << 15))

#define	GPDMA_DMACCxControl_SWidth(n) (((n & 0x07) << 18))

#define	GPDMA_DMACCxControl_DWidth(n) (((n & 0x07) << 21))

#define	GPDMA_DMACCxControl_SI ((1UL << 26))

#define	GPDMA_DMACCxControl_DI ((1UL << 27))

#define	GPDMA_DMACCxControl_SrcTransUseAHBMaster1 0

#define	GPDMA_DMACCxControl_DestTransUseAHBMaster1 0

#define	GPDMA_DMACCxControl_Prot1 ((1UL << 28))

#define	GPDMA_DMACCxControl_Prot2 ((1UL << 29))

#define	GPDMA_DMACCxControl_Prot3 ((1UL << 30))

#define	GPDMA_DMACCxControl_I ((1UL << 31))

#define	GPDMA_DMACConfig_E ((0x01))
	Macro defines for DMA Configuration register.

#define	GPDMA_DMACConfig_M ((0x02))

#define	GPDMA_DMACConfig_BITMASK ((0x03))

#define	GPDMA_DMACCxConfig_E ((1UL << 0))
	Macro defines for DMA Channel Configuration registers.

#define	GPDMA_DMACCxConfig_SrcPeripheral(n) (((n & 0x1F) << 1))

#define	GPDMA_DMACCxConfig_DestPeripheral(n) (((n & 0x1F) << 6))

#define	GPDMA_DMACCxConfig_TransferType(n) (((n & 0x7) << 11))

#define	GPDMA_DMACCxConfig_IE ((1UL << 14))

#define	GPDMA_DMACCxConfig_ITC ((1UL << 15))

#define	GPDMA_DMACCxConfig_L ((1UL << 16))

#define	GPDMA_DMACCxConfig_A ((1UL << 17))

#define	GPDMA_DMACCxConfig_H ((1UL << 18))

Enumerations
enum	IP_GPDMA_STATECLEAR_T { GPDMA_STATCLR_INTTC, GPDMA_STATCLR_INTERR }
	GPDMA Interrupt Clear Status. More...

enum	IP_GPDMA_STATUS_T { GPDMA_STAT_INT, GPDMA_STAT_INTTC, GPDMA_STAT_INTERR, GPDMA_STAT_RAWINTTC, GPDMA_STAT_RAWINTERR, GPDMA_STAT_ENABLED_CH }
	GPDMA Type of Interrupt Status. More...

enum	IP_GPDMA_FLOW_CONTROL_T { GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA = ((0UL)), GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA = ((1UL)), GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA = ((2UL)), GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA = ((3UL)), GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL = ((4UL)), GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL = ((5UL)), GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL = ((6UL)), GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL = ((7UL)) }
	GPDMA Type of DMA controller. More...

Functions
void	IP_GPDMA_Init (IP_GPDMA_001_T *pGPDMA)
	Initialize the GPDMA.

uint32_t	IP_GPDMA_MakeCtrlWord (const GPDMA_Channel_CFG_T *GPDMAChannelConfig, uint32_t GPDMA_LUTPerBurstSrcConn, uint32_t GPDMA_LUTPerBurstDstConn, uint32_t GPDMA_LUTPerWidSrcConn, uint32_t GPDMA_LUTPerWidDstConn)
	Create the Control word based on given parameters.

Status	IP_GPDMA_Setup (IP_GPDMA_001_T pGPDMA, GPDMA_Channel_CFG_T GPDMAChannelConfig, uint32_t CtrlWord, uint32_t LinkListItem, uint8_t SrcPeripheral, uint8_t DstPeripheral)
	Set up the GPDMA according to the specification configuration details.

IntStatus	IP_GPDMA_IntGetStatus (IP_GPDMA_001_T *pGPDMA, IP_GPDMA_STATUS_T type, uint8_t channel)
	Read the status from different registers according to the type.

void	IP_GPDMA_ClearIntPending (IP_GPDMA_001_T *pGPDMA, IP_GPDMA_STATECLEAR_T type, uint8_t channel)
	Clear the Interrupt Flag from different registers according to the type.

void	IP_GPDMA_ChannelCmd (IP_GPDMA_001_T *pGPDMA, uint8_t channelNum, FunctionalState NewState)
	Enable or Disable the GPDMA Channel.

Macro Definition Documentation

#define GPDMA_CHANNELS 8

Definition at line 60 of file gpdma_001.h.

#define GPDMA_DMACConfig_BITMASK ((0x03))

Definition at line 111 of file gpdma_001.h.

#define GPDMA_DMACConfig_E ((0x01))

Macro defines for DMA Configuration register.

DMA Controller enable

Definition at line 109 of file gpdma_001.h.

#define GPDMA_DMACConfig_M ((0x02))

AHB Master endianness configuration

Definition at line 110 of file gpdma_001.h.

#define GPDMA_DMACCxConfig_A ((1UL << 17))

Active

Definition at line 123 of file gpdma_001.h.

#define GPDMA_DMACCxConfig_DestPeripheral ( n ) (((n & 0x1F) << 6))

Destination peripheral

Definition at line 118 of file gpdma_001.h.

#define GPDMA_DMACCxConfig_E ((1UL << 0))

Macro defines for DMA Channel Configuration registers.

DMA control enable

Definition at line 116 of file gpdma_001.h.

#define GPDMA_DMACCxConfig_H ((1UL << 18))

Halt

Definition at line 124 of file gpdma_001.h.

#define GPDMA_DMACCxConfig_IE ((1UL << 14))

Interrupt error mask

Definition at line 120 of file gpdma_001.h.

#define GPDMA_DMACCxConfig_ITC ((1UL << 15))

Terminal count interrupt mask

Definition at line 121 of file gpdma_001.h.

#define GPDMA_DMACCxConfig_L ((1UL << 16))

Lock

Definition at line 122 of file gpdma_001.h.

#define GPDMA_DMACCxConfig_SrcPeripheral ( n ) (((n & 0x1F) << 1))

Source peripheral

Definition at line 117 of file gpdma_001.h.

#define GPDMA_DMACCxConfig_TransferType ( n ) (((n & 0x7) << 11))

This value indicates the type of transfer

Definition at line 119 of file gpdma_001.h.

#define GPDMA_DMACCxControl_DBSize ( n ) (((n & 0x07) << 15))

Destination burst size

Definition at line 89 of file gpdma_001.h.

#define GPDMA_DMACCxControl_DestTransUseAHBMaster1 0

Definition at line 99 of file gpdma_001.h.

#define GPDMA_DMACCxControl_DI ((1UL << 27))

Destination increment

Definition at line 93 of file gpdma_001.h.

#define GPDMA_DMACCxControl_DWidth ( n ) (((n & 0x07) << 21))

Destination transfer width

Definition at line 91 of file gpdma_001.h.

#define GPDMA_DMACCxControl_I ((1UL << 31))

Terminal count interrupt enable bit

Definition at line 104 of file gpdma_001.h.

#define GPDMA_DMACCxControl_Prot1 ((1UL << 28))

Indicates that the access is in user mode or privileged mode

Definition at line 101 of file gpdma_001.h.

#define GPDMA_DMACCxControl_Prot2 ((1UL << 29))

Indicates that the access is bufferable or not bufferable

Definition at line 102 of file gpdma_001.h.

#define GPDMA_DMACCxControl_Prot3 ((1UL << 30))

Indicates that the access is cacheable or not cacheable

Definition at line 103 of file gpdma_001.h.

#define GPDMA_DMACCxControl_SBSize ( n ) (((n & 0x07) << 12))

Source burst size

Definition at line 88 of file gpdma_001.h.

#define GPDMA_DMACCxControl_SI ((1UL << 26))

Source increment

Definition at line 92 of file gpdma_001.h.

#define GPDMA_DMACCxControl_SrcTransUseAHBMaster1 0

Definition at line 98 of file gpdma_001.h.

#define GPDMA_DMACCxControl_SWidth ( n ) (((n & 0x07) << 18))

Source transfer width

Definition at line 90 of file gpdma_001.h.

#define GPDMA_DMACCxControl_TransferSize ( n ) (((n & 0xFFF) << 0))

Macro defines for DMA channel control registers.

Transfer size

Definition at line 87 of file gpdma_001.h.

Enumeration Type Documentation

enum IP_GPDMA_FLOW_CONTROL_T

GPDMA Type of DMA controller.

Enumerator:

GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA	Memory to memory - DMA control
GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA	Memory to peripheral - DMA control
GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA	Peripheral to memory - DMA control
GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA	Source peripheral to destination peripheral - DMA control
GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL	Source peripheral to destination peripheral - destination peripheral control
GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL	Memory to peripheral - peripheral control
GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL	Peripheral to memory - peripheral control
GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL	Source peripheral to destination peripheral - source peripheral control

Definition at line 149 of file gpdma_001.h.

enum IP_GPDMA_STATECLEAR_T

GPDMA Interrupt Clear Status.

Enumerator:

GPDMA_STATCLR_INTTC	GPDMA Interrupt Terminal Count Request Clear
GPDMA_STATCLR_INTERR	GPDMA Interrupt Error Clear

Definition at line 129 of file gpdma_001.h.

enum IP_GPDMA_STATUS_T

GPDMA Type of Interrupt Status.

Enumerator:

GPDMA_STAT_INT	GPDMA Interrupt Status
GPDMA_STAT_INTTC	GPDMA Interrupt Terminal Count Request Status
GPDMA_STAT_INTERR	GPDMA Interrupt Error Status
GPDMA_STAT_RAWINTTC	GPDMA Raw Interrupt Terminal Count Status
GPDMA_STAT_RAWINTERR	GPDMA Raw Error Interrupt Status
GPDMA_STAT_ENABLED_CH	GPDMA Enabled Channel Status

Definition at line 137 of file gpdma_001.h.

Function Documentation

void IP_GPDMA_ChannelCmd	(	IP_GPDMA_001_T *	pGPDMA,
		uint8_t	channelNum,
		FunctionalState	NewState
	)

Enable or Disable the GPDMA Channel.

Parameters

pGPDMA	: The Base Address of GPDMA on the chip
channelNum	: The GPDMA channel : 0 - 7
NewState	: ENABLE to enable GPDMA or DISABLE to disable GPDMA

Returns: Nothing

Definition at line 102 of file gpdma_001.c.

void IP_GPDMA_ClearIntPending	(	IP_GPDMA_001_T *	pGPDMA,
		IP_GPDMA_STATECLEAR_T	type,
		uint8_t	channel
	)

Clear the Interrupt Flag from different registers according to the type.

Parameters

pGPDMA	: The Base Address of GPDMA on the chip
type	: Flag mode, should be: GPDMA_STATCLR_INTTC : GPDMA Interrupt Terminal Count Request GPDMA_STATCLR_INTERR : GPDMA Interrupt Error
channel	: The GPDMA channel : 0 - 7

Returns: Nothing

Definition at line 90 of file gpdma_001.c.

void IP_GPDMA_Init ( IP_GPDMA_001_T * pGPDMA )

Initialize the GPDMA.

Parameters

pGPDMA : The Base Address of GPDMA on the chip

Returns: Nothing

Definition at line 51 of file gpdma_001.c.

IntStatus IP_GPDMA_IntGetStatus	(	IP_GPDMA_001_T *	pGPDMA,
		IP_GPDMA_STATUS_T	type,
		uint8_t	channel
	)

Read the status from different registers according to the type.

Parameters

pGPDMA	: The Base Address of GPDMA on the chip
type	: Status mode, should be: GPDMA_STAT_INT : GPDMA Interrupt Status GPDMA_STAT_INTTC : GPDMA Interrupt Terminal Count Request Status GPDMA_STAT_INTERR : GPDMA Interrupt Error Status GPDMA_STAT_RAWINTTC : GPDMA Raw Interrupt Terminal Count Status GPDMA_STAT_RAWINTERR : GPDMA Raw Error Interrupt Status GPDMA_STAT_ENABLED_CH : GPDMA Enabled Channel Status
channel	: The GPDMA channel : 0 - 7

Returns: SET is interrupt is pending or RESET if not pending

TODO check the channel <=8 type is exited

Definition at line 64 of file gpdma_001.c.

uint32_t IP_GPDMA_MakeCtrlWord	(	const GPDMA_Channel_CFG_T *	GPDMAChannelConfig,
		uint32_t	GPDMA_LUTPerBurstSrcConn,
		uint32_t	GPDMA_LUTPerBurstDstConn,
		uint32_t	GPDMA_LUTPerWidSrcConn,
		uint32_t	GPDMA_LUTPerWidDstConn
	)

Create the Control word based on given parameters.

Parameters

GPDMAChannelConfig	: Configuration struct
GPDMA_LUTPerBurstSrcConn	: Peripheral Source burst size
GPDMA_LUTPerBurstDstConn	: Peripheral Destination burst size
GPDMA_LUTPerWidSrcConn	: Peripheral Source transfer width
GPDMA_LUTPerWidDstConn	: Peripheral Destination transfer width

Returns: 32-bit unsigned control value, can be used while calling IP_GPDMA_Setup(), ERROR if the transfer type specified in GPDMAChannelConfig is invalid

Note: Control Word is a 32-bit unsigned value that provides the transfer information like the peripheral number, transfer size etc.,

< Burst size = 32

Definition at line 116 of file gpdma_001.c.

Status IP_GPDMA_Setup	(	IP_GPDMA_001_T *	pGPDMA,
		GPDMA_Channel_CFG_T *	GPDMAChannelConfig,
		uint32_t	CtrlWord,
		uint32_t	LinkListItem,
		uint8_t	SrcPeripheral,
		uint8_t	DstPeripheral
	)

Set up the GPDMA according to the specification configuration details.

Parameters

pGPDMA	: The Base Address of GPDMA on the chip
GPDMAChannelConfig	: Pointer to Configuration struct
CtrlWord	: Control Word can be obtained using IP_GPDMA_MakeCtrlWord()
LinkListItem	: Pointer to next descriptor [0 if no linked list is used]
SrcPeripheral	: Peripheral Source ID
DstPeripheral	: Peripheral Destination ID

Returns: SUCCESS or ERROR on setup failure

Definition at line 183 of file gpdma_001.c.

Detailed Description

Data Structures

Macros

Enumerations

Functions

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation