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Data Structures | Macros | Enumerations | Functions
IP: I2S register block and driver
IP drivers: Common drivers used on multiple NXP devices

Detailed Description

Data Structures

struct  IP_I2S_001_T
 I2S register block structure. More...
 

Macros

#define I2S_WORDWIDTH_8   (0UL << 0)
 I2S configuration parameter defines.
 
#define I2S_WORDWIDTH_16   (1UL << 0)
 
#define I2S_WORDWIDTH_32   (3UL << 0)
 
#define I2S_STEREO   (0UL << 2)
 
#define I2S_MONO   (1UL << 2)
 
#define I2S_MASTER_MODE   (0UL << 5)
 
#define I2S_SLAVE_MODE   (1UL << 5)
 
#define I2S_STOP_ENABLE   (0UL << 3)
 
#define I2S_STOP_DISABLE   (1UL << 3)
 
#define I2S_RESET_ENABLE   (1UL << 4)
 
#define I2S_RESET_DISABLE   (0UL << 4)
 
#define I2S_MUTE_ENABLE   (1UL << 15)
 
#define I2S_MUTE_DISABLE   (0UL << 15)
 
#define I2S_DAO_WORDWIDTH_8   ((uint32_t) (0))
 Macro defines for DAO-Digital Audio Output register.
 
#define I2S_DAO_WORDWIDTH_16   ((uint32_t) (1))
 
#define I2S_DAO_WORDWIDTH_32   ((uint32_t) (3))
 
#define I2S_DAO_WORDWIDTH_MASK   ((uint32_t) (3))
 
#define I2S_DAO_MONO   ((uint32_t) (1 << 2))
 
#define I2S_DAO_STOP   ((uint32_t) (1 << 3))
 
#define I2S_DAO_RESET   ((uint32_t) (1 << 4))
 
#define I2S_DAO_SLAVE   ((uint32_t) (1 << 5))
 
#define I2S_DAO_WS_HALFPERIOD(n)   ((uint32_t) ((n & 0x1FF) << 6))
 
#define I2S_DAO_WS_HALFPERIOD_MASK   ((uint32_t) ((0x1FF) << 6))
 
#define I2S_DAO_MUTE   ((uint32_t) (1 << 15))
 
#define I2S_DAI_WORDWIDTH_8   ((uint32_t) (0))
 Macro defines for DAI-Digital Audio Input register.
 
#define I2S_DAI_WORDWIDTH_16   ((uint32_t) (1))
 
#define I2S_DAI_WORDWIDTH_32   ((uint32_t) (3))
 
#define I2S_DAI_WORDWIDTH_MASK   ((uint32_t) (3))
 
#define I2S_DAI_MONO   ((uint32_t) (1 << 2))
 
#define I2S_DAI_STOP   ((uint32_t) (1 << 3))
 
#define I2S_DAI_RESET   ((uint32_t) (1 << 4))
 
#define I2S_DAI_SLAVE   ((uint32_t) (1 << 5))
 
#define I2S_DAI_WS_HALFPERIOD(n)   ((uint32_t) ((n & 0x1FF) << 6))
 
#define I2S_DAI_WS_HALFPERIOD_MASK   ((uint32_t) ((0x1FF) << 6))
 
#define I2S_STATE_IRQ   ((uint32_t) (1))
 Macro defines for STAT register (Status Feedback register)
 
#define I2S_STATE_DMA1   ((uint32_t) (1 << 1))
 
#define I2S_STATE_DMA2   ((uint32_t) (1 << 2))
 
#define I2S_STATE_RX_LEVEL(n)   ((uint32_t) ((n & 1F) << 8))
 
#define I2S_STATE_TX_LEVEL(n)   ((uint32_t) ((n & 1F) << 16))
 
#define I2S_DMA1_RX_ENABLE   ((uint32_t) (1))
 Macro defines for DMA1 register (DMA1 Configuration register)
 
#define I2S_DMA1_TX_ENABLE   ((uint32_t) (1 << 1))
 
#define I2S_DMA1_RX_DEPTH(n)   ((uint32_t) ((n & 0x1F) << 8))
 
#define I2S_DMA1_TX_DEPTH(n)   ((uint32_t) ((n & 0x1F) << 16))
 
#define I2S_DMA2_RX_ENABLE   ((uint32_t) (1))
 Macro defines for DMA2 register (DMA2 Configuration register)
 
#define I2S_DMA2_TX_ENABLE   ((uint32_t) (1 << 1))
 
#define I2S_DMA2_RX_DEPTH(n)   ((uint32_t) ((n & 0x1F) << 8))
 
#define I2S_DMA2_TX_DEPTH(n)   ((uint32_t) ((n & 0x1F) << 16))
 
#define I2S_IRQ_RX_ENABLE   ((uint32_t) (1))
 Macro defines for IRQ register (Interrupt Request Control register)
 
#define I2S_IRQ_TX_ENABLE   ((uint32_t) (1 << 1))
 
#define I2S_IRQ_RX_DEPTH(n)   ((uint32_t) ((n & 0x0F) << 8))
 
#define I2S_IRQ_RX_DEPTH_MASK   ((uint32_t) ((0x0F) << 8))
 
#define I2S_IRQ_TX_DEPTH(n)   ((uint32_t) ((n & 0x0F) << 16))
 
#define I2S_IRQ_TX_DEPTH_MASK   ((uint32_t) ((0x0F) << 16))
 
#define I2S_TXRATE_Y_DIVIDER(n)   ((uint32_t) (n & 0xFF))
 Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register)
 
#define I2S_TXRATE_X_DIVIDER(n)   ((uint32_t) ((n & 0xFF) << 8))
 
#define I2S_RXRATE_Y_DIVIDER(n)   ((uint32_t) (n & 0xFF))
 
#define I2S_RXRATE_X_DIVIDER(n)   ((uint32_t) ((n & 0xFF) << 8))
 
#define I2S_TXBITRATE(n)   ((uint32_t) (n & 0x3F))
 Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register)
 
#define I2S_RXBITRATE(n)   ((uint32_t) (n & 0x3F))
 
#define I2S_TXMODE_CLKSEL(n)   ((uint32_t) (n & 0x03))
 Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register)
 
#define I2S_TXMODE_4PIN_ENABLE   ((uint32_t) (1 << 2))
 
#define I2S_TXMODE_MCENA   ((uint32_t) (1 << 3))
 
#define I2S_RXMODE_CLKSEL(n)   ((uint32_t) (n & 0x03))
 
#define I2S_RXMODE_4PIN_ENABLE   ((uint32_t) (1 << 2))
 
#define I2S_RXMODE_MCENA   ((uint32_t) (1 << 3))
 

Enumerations

enum  IP_I2S_TRxMode_T { I2S_TX_MODE, I2S_RX_MODE }
 I2S transmit/receive mode for configuration. More...
 
enum  IP_I2S_DMARequestNumber_T { IP_I2S_DMA_REQUEST_NUMBER_1, IP_I2S_DMA_REQUEST_NUMBER_2 }
 I2S DMA request channel define. More...
 

Functions

void IP_I2S_Init (IP_I2S_001_T *pI2S)
 Initialize for I2S.
 
void IP_I2S_DeInit (IP_I2S_001_T *pI2S)
 Shutdown I2S.
 
void IP_I2S_SetWordWidth (IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t wordwidth)
 Set the data width for the specified mode.
 
void IP_I2S_SetMono (IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t mono)
 Set I2S data format to mono or stereo.
 
void IP_I2S_SetMasterSlaveMode (IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t mode)
 Set I2S interface in master/slave mode.
 
void IP_I2S_SetBitRate (IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t mclk_divider)
 Set the clock frequency for I2S interface.
 
void IP_I2S_SetXYDivider (IP_I2S_001_T *pI2S, uint8_t TRMode, uint8_t x_divider, uint8_t y_devider)
 Set the MCLK rate by using a fractional rate generator, dividing down the frequency of PCLK.
 
void IP_I2S_SetWS_Halfperiod (IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t ws_halfperiod)
 Set word select (WS) half period.
 
void IP_I2S_ModeConfig (IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t clksel, uint32_t fpin, uint32_t mcena)
 Set the I2S operating modes.
 
uint8_t IP_I2S_GetLevel (IP_I2S_001_T *pI2S, uint8_t TRMode)
 Get the current level of the Transmit/Receive FIFO.
 
void IP_I2S_Send (IP_I2S_001_T *pI2S, uint32_t data)
 Send a 32-bit data to TXFIFO for transmition.
 
uint32_t IP_I2S_Receive (IP_I2S_001_T *pI2S)
 Get received data from RXFIFO.
 
void IP_I2S_Start (IP_I2S_001_T *pI2S, uint8_t TRMode)
 Start the I2S.
 
void IP_I2S_Pause (IP_I2S_001_T *pI2S, uint8_t TRMode)
 Disables accesses on FIFOs, places the transmit channel in mute mode.
 
STATIC INLINE void IP_I2S_EnableMute (IP_I2S_001_T *pI2S)
 Transmit channel sends only zeroes.
 
STATIC INLINE void IP_I2S_DisableMute (IP_I2S_001_T *pI2S)
 Un-Mute the I2S channel.
 
void IP_I2S_Stop (IP_I2S_001_T *pI2S, uint8_t TRMode)
 Stop I2S asynchronously.
 
void IP_I2S_SetFIFODepthDMA (IP_I2S_001_T *pI2S, uint8_t TRMode, IP_I2S_DMARequestNumber_T DMANum, uint32_t depth)
 Set the FIFO level on which to create an DMA request.
 
void IP_I2S_DMACmd (IP_I2S_001_T *pI2S, IP_I2S_DMARequestNumber_T DMANum, uint8_t TRMode, FunctionalState NewState)
 Enable/Disable DMA for the I2S.
 
void IP_I2S_InterruptCmd (IP_I2S_001_T *pI2S, uint8_t TRMode, FunctionalState NewState)
 Enable/Disable interrupt for the I2S.
 
void IP_I2S_SetFIFODepthIRQ (IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t depth)
 Set the FIFO level on which to create an irq request.
 
Status IP_I2S_GetIntStatus (IP_I2S_001_T *pI2S, uint8_t TRMode)
 Get the status of I2S interrupt.
 

Macro Definition Documentation

#define I2S_DAI_MONO   ((uint32_t) (1 << 2))

I2S control mono or stereo format DAI mono mode mask

Definition at line 133 of file i2s_001.h.

#define I2S_DAI_RESET   ((uint32_t) (1 << 4))

I2S control reset mode DAI reset bit mask

Definition at line 139 of file i2s_001.h.

#define I2S_DAI_SLAVE   ((uint32_t) (1 << 5))

I2S control master/slave mode DAI slave mode mask

Definition at line 142 of file i2s_001.h.

#define I2S_DAI_STOP   ((uint32_t) (1 << 3))

I2S control stop mode DAI stop bit mask

Definition at line 136 of file i2s_001.h.

#define I2S_DAI_WORDWIDTH_16   ((uint32_t) (1))

DAI 16 bit

Definition at line 128 of file i2s_001.h.

#define I2S_DAI_WORDWIDTH_32   ((uint32_t) (3))

DAI 32 bit

Definition at line 129 of file i2s_001.h.

#define I2S_DAI_WORDWIDTH_8   ((uint32_t) (0))

Macro defines for DAI-Digital Audio Input register.

I2S wordwide - the number of bytes in data DAI 8 bit

Definition at line 127 of file i2s_001.h.

#define I2S_DAI_WORDWIDTH_MASK   ((uint32_t) (3))

DAI word wide mask

Definition at line 130 of file i2s_001.h.

#define I2S_DAI_WS_HALFPERIOD (   n)    ((uint32_t) ((n & 0x1FF) << 6))

I2S word select half period minus one (9 bits) DAI Word select set macro

Definition at line 145 of file i2s_001.h.

#define I2S_DAI_WS_HALFPERIOD_MASK   ((uint32_t) ((0x1FF) << 6))

DAI Word select mask

Definition at line 146 of file i2s_001.h.

#define I2S_DAO_MONO   ((uint32_t) (1 << 2))

I2S control mono or stereo format DAO mono audio mask

Definition at line 105 of file i2s_001.h.

#define I2S_DAO_MUTE   ((uint32_t) (1 << 15))

I2S control mute mode DAO mute mask

Definition at line 121 of file i2s_001.h.

#define I2S_DAO_RESET   ((uint32_t) (1 << 4))

I2S control reset mode DAO reset mask

Definition at line 111 of file i2s_001.h.

#define I2S_DAO_SLAVE   ((uint32_t) (1 << 5))

I2S control master/slave mode DAO slave mode mask

Definition at line 114 of file i2s_001.h.

#define I2S_DAO_STOP   ((uint32_t) (1 << 3))

I2S control stop mode DAO stop mask

Definition at line 108 of file i2s_001.h.

#define I2S_DAO_WORDWIDTH_16   ((uint32_t) (1))

DAO 16 bit

Definition at line 100 of file i2s_001.h.

#define I2S_DAO_WORDWIDTH_32   ((uint32_t) (3))

DAO 32 bit

Definition at line 101 of file i2s_001.h.

#define I2S_DAO_WORDWIDTH_8   ((uint32_t) (0))

Macro defines for DAO-Digital Audio Output register.

I2S wordwide - the number of bytes in data DAO 8 bit

Definition at line 99 of file i2s_001.h.

#define I2S_DAO_WORDWIDTH_MASK   ((uint32_t) (3))

Definition at line 102 of file i2s_001.h.

#define I2S_DAO_WS_HALFPERIOD (   n)    ((uint32_t) ((n & 0x1FF) << 6))

I2S word select half period minus one DAO Word select set macro

Definition at line 117 of file i2s_001.h.

#define I2S_DAO_WS_HALFPERIOD_MASK   ((uint32_t) ((0x1FF) << 6))

DAO Word select mask

Definition at line 118 of file i2s_001.h.

#define I2S_DMA1_RX_DEPTH (   n)    ((uint32_t) ((n & 0x1F) << 8))

I2S set FIFO level that trigger a receive DMA request on DMA1

Definition at line 162 of file i2s_001.h.

#define I2S_DMA1_RX_ENABLE   ((uint32_t) (1))

Macro defines for DMA1 register (DMA1 Configuration register)

I2S control DMA1 for I2S receive

Definition at line 160 of file i2s_001.h.

#define I2S_DMA1_TX_DEPTH (   n)    ((uint32_t) ((n & 0x1F) << 16))

I2S set FIFO level that trigger a transmit DMA request on DMA1

Definition at line 163 of file i2s_001.h.

#define I2S_DMA1_TX_ENABLE   ((uint32_t) (1 << 1))

I2S control DMA1 for I2S transmit

Definition at line 161 of file i2s_001.h.

#define I2S_DMA2_RX_DEPTH (   n)    ((uint32_t) ((n & 0x1F) << 8))

I2S set FIFO level that trigger a receive DMA request on DMA1

Definition at line 170 of file i2s_001.h.

#define I2S_DMA2_RX_ENABLE   ((uint32_t) (1))

Macro defines for DMA2 register (DMA2 Configuration register)

I2S control DMA2 for I2S receive

Definition at line 168 of file i2s_001.h.

#define I2S_DMA2_TX_DEPTH (   n)    ((uint32_t) ((n & 0x1F) << 16))

I2S set FIFO level that trigger a transmit DMA request on DMA1

Definition at line 171 of file i2s_001.h.

#define I2S_DMA2_TX_ENABLE   ((uint32_t) (1 << 1))

I2S control DMA1 for I2S transmit

Definition at line 169 of file i2s_001.h.

#define I2S_IRQ_RX_DEPTH (   n)    ((uint32_t) ((n & 0x0F) << 8))

I2S set the FIFO level on which to create an irq request

Definition at line 179 of file i2s_001.h.

#define I2S_IRQ_RX_DEPTH_MASK   ((uint32_t) ((0x0F) << 8))

Definition at line 180 of file i2s_001.h.

#define I2S_IRQ_RX_ENABLE   ((uint32_t) (1))

Macro defines for IRQ register (Interrupt Request Control register)

I2S control I2S receive interrupt

Definition at line 177 of file i2s_001.h.

#define I2S_IRQ_TX_DEPTH (   n)    ((uint32_t) ((n & 0x0F) << 16))

I2S set the FIFO level on which to create an irq request

Definition at line 181 of file i2s_001.h.

#define I2S_IRQ_TX_DEPTH_MASK   ((uint32_t) ((0x0F) << 16))

Definition at line 182 of file i2s_001.h.

#define I2S_IRQ_TX_ENABLE   ((uint32_t) (1 << 1))

I2S control I2S transmit interrupt

Definition at line 178 of file i2s_001.h.

#define I2S_MASTER_MODE   (0UL << 5)

I2S Master/Slave mode bit I2S in master mode

Definition at line 80 of file i2s_001.h.

#define I2S_MONO   (1UL << 2)

Mono audio

Definition at line 77 of file i2s_001.h.

#define I2S_MUTE_DISABLE   (0UL << 15)

I2S mute disbale mask

Definition at line 93 of file i2s_001.h.

#define I2S_MUTE_ENABLE   (1UL << 15)

I2S Mute bit I2S mute enable mask

Definition at line 92 of file i2s_001.h.

#define I2S_RESET_DISABLE   (0UL << 4)

I2S reset disable mask

Definition at line 89 of file i2s_001.h.

#define I2S_RESET_ENABLE   (1UL << 4)

I2S Reset bit I2S reset enable mask

Definition at line 88 of file i2s_001.h.

#define I2S_RXBITRATE (   n)    ((uint32_t) (n & 0x3F))

Definition at line 196 of file i2s_001.h.

#define I2S_RXMODE_4PIN_ENABLE   ((uint32_t) (1 << 2))

I2S Receive control 4-pin mode

Definition at line 205 of file i2s_001.h.

#define I2S_RXMODE_CLKSEL (   n)    ((uint32_t) (n & 0x03))

I2S Receive select clock source

Definition at line 204 of file i2s_001.h.

#define I2S_RXMODE_MCENA   ((uint32_t) (1 << 3))

I2S Receive control the TX_MCLK output

Definition at line 206 of file i2s_001.h.

#define I2S_RXRATE_X_DIVIDER (   n)    ((uint32_t) ((n & 0xFF) << 8))

I2S Receive MCLK rate denominator

Definition at line 190 of file i2s_001.h.

#define I2S_RXRATE_Y_DIVIDER (   n)    ((uint32_t) (n & 0xFF))

I2S Receive MCLK rate denominator

Definition at line 189 of file i2s_001.h.

#define I2S_SLAVE_MODE   (1UL << 5)

I2S in slave mode

Definition at line 81 of file i2s_001.h.

#define I2S_STATE_DMA1   ((uint32_t) (1 << 1))

I2S Status Receive or Transmit DMA1

Definition at line 152 of file i2s_001.h.

#define I2S_STATE_DMA2   ((uint32_t) (1 << 2))

I2S Status Receive or Transmit DMA2

Definition at line 153 of file i2s_001.h.

#define I2S_STATE_IRQ   ((uint32_t) (1))

Macro defines for STAT register (Status Feedback register)

I2S Status Receive or Transmit Interrupt

Definition at line 151 of file i2s_001.h.

#define I2S_STATE_RX_LEVEL (   n)    ((uint32_t) ((n & 1F) << 8))

I2S Status Current level of the Receive FIFO (5 bits)

Definition at line 154 of file i2s_001.h.

#define I2S_STATE_TX_LEVEL (   n)    ((uint32_t) ((n & 1F) << 16))

I2S Status Current level of the Transmit FIFO (5 bits)

Definition at line 155 of file i2s_001.h.

#define I2S_STEREO   (0UL << 2)

I2S Channel bit Stereo audio

Definition at line 76 of file i2s_001.h.

#define I2S_STOP_DISABLE   (1UL << 3)

I2S stop disable mask

Definition at line 85 of file i2s_001.h.

#define I2S_STOP_ENABLE   (0UL << 3)

I2S Stop bit I2S stop enable mask

Definition at line 84 of file i2s_001.h.

#define I2S_TXBITRATE (   n)    ((uint32_t) (n & 0x3F))

Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register)

Definition at line 195 of file i2s_001.h.

#define I2S_TXMODE_4PIN_ENABLE   ((uint32_t) (1 << 2))

I2S Transmit control 4-pin mode

Definition at line 202 of file i2s_001.h.

#define I2S_TXMODE_CLKSEL (   n)    ((uint32_t) (n & 0x03))

Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register)

I2S Transmit select clock source (2 bits)

Definition at line 201 of file i2s_001.h.

#define I2S_TXMODE_MCENA   ((uint32_t) (1 << 3))

I2S Transmit control the TX_MCLK output

Definition at line 203 of file i2s_001.h.

#define I2S_TXRATE_X_DIVIDER (   n)    ((uint32_t) ((n & 0xFF) << 8))

I2S Transmit MCLK rate denominator

Definition at line 188 of file i2s_001.h.

#define I2S_TXRATE_Y_DIVIDER (   n)    ((uint32_t) (n & 0xFF))

Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register)

I2S Transmit MCLK rate denominator

Definition at line 187 of file i2s_001.h.

#define I2S_WORDWIDTH_16   (1UL << 0)

16 bit word

Definition at line 72 of file i2s_001.h.

#define I2S_WORDWIDTH_32   (3UL << 0)

32 bit word

Definition at line 73 of file i2s_001.h.

#define I2S_WORDWIDTH_8   (0UL << 0)

I2S configuration parameter defines.

I2S Wordwidth bit 8 bit Word

Definition at line 71 of file i2s_001.h.

Enumeration Type Documentation

enum IP_I2S_DMARequestNumber_T

I2S DMA request channel define.

Enumerator:
IP_I2S_DMA_REQUEST_NUMBER_1 

DMA request channel 1

IP_I2S_DMA_REQUEST_NUMBER_2 

DMA request channel 2

Definition at line 219 of file i2s_001.h.

enum IP_I2S_TRxMode_T

I2S transmit/receive mode for configuration.

Enumerator:
I2S_TX_MODE 

Transmit mode

I2S_RX_MODE 

Receive mode

Definition at line 211 of file i2s_001.h.

Function Documentation

void IP_I2S_DeInit ( IP_I2S_001_T *  pI2S)

Shutdown I2S.

Parameters
pI2S: The base of I2S peripheral on the chip
Returns
Nothing
Note
Reset all relative registers (DMA, transmit/receive control, interrupt) to default value

Definition at line 55 of file i2s_001.c.

STATIC INLINE void IP_I2S_DisableMute ( IP_I2S_001_T *  pI2S)

Un-Mute the I2S channel.

Returns
Nothing

Definition at line 395 of file i2s_001.h.

void IP_I2S_DMACmd ( IP_I2S_001_T *  pI2S,
IP_I2S_DMARequestNumber_T  DMANum,
uint8_t  TRMode,
FunctionalState  NewState 
)

Enable/Disable DMA for the I2S.

Parameters
pI2S: The base of I2S peripheral on the chip
TRMode: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
DMANum: I2S DMA request number, should be
  • IP_I2S_DMA_REQUEST_NUMBER_1
  • IP_I2S_DMA_REQUEST_NUMBER_2
NewState: ENABLE or DISABLE DMA
Returns
Nothing

Definition at line 219 of file i2s_001.c.

STATIC INLINE void IP_I2S_EnableMute ( IP_I2S_001_T *  pI2S)

Transmit channel sends only zeroes.

Parameters
pI2S: The base of I2S peripheral on the chip
Returns
Nothing
Note
The data output from I2S transmit channel is always zeroes

Definition at line 386 of file i2s_001.h.

Status IP_I2S_GetIntStatus ( IP_I2S_001_T *  pI2S,
uint8_t  TRMode 
)

Get the status of I2S interrupt.

Parameters
pI2S: The base of I2S peripheral on the chip
TRMode: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
Returns
I2S interrupt status, SET or RESET

Definition at line 313 of file i2s_001.c.

uint8_t IP_I2S_GetLevel ( IP_I2S_001_T *  pI2S,
uint8_t  TRMode 
)

Get the current level of the Transmit/Receive FIFO.

Parameters
pI2S: The base of I2S peripheral on the chip
TRMode: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
Returns
Current level of the Transmit/Receive FIFO

Definition at line 158 of file i2s_001.c.

void IP_I2S_Init ( IP_I2S_001_T *  pI2S)

Initialize for I2S.

Parameters
pI2S: The base of I2S peripheral on the chip
Returns
Nothing

Definition at line 51 of file i2s_001.c.

void IP_I2S_InterruptCmd ( IP_I2S_001_T *  pI2S,
uint8_t  TRMode,
FunctionalState  NewState 
)

Enable/Disable interrupt for the I2S.

Parameters
pI2S: The base of I2S peripheral on the chip
TRMode: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
NewState: ENABLE or DISABLE Interrupt
Returns
Nothing
Note
Interrupt request is generated when rx_depth_irq <= rx_level or tx_depth_irq >= tx_level

Definition at line 287 of file i2s_001.c.

void IP_I2S_ModeConfig ( IP_I2S_001_T *  pI2S,
uint8_t  TRMode,
uint32_t  clksel,
uint32_t  fpin,
uint32_t  mcena 
)

Set the I2S operating modes.

Parameters
pI2S: The base of I2S peripheral on the chip
TRMode: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
clksel: Clock source selection for the receive bit clock divider
fpin: Receive 4-pin mode selection
mcena: Enable for the RX_MCLK output
Returns
Nothing
Note
In addition to master and slave modes, which are independently configurable for the transmitter and the receiver, several different clock sources are possible, including variations that share the clock and/or WS between the transmitter and receiver. It also allows using I2S with fewer pins, typically four.

Definition at line 147 of file i2s_001.c.

void IP_I2S_Pause ( IP_I2S_001_T *  pI2S,
uint8_t  TRMode 
)

Disables accesses on FIFOs, places the transmit channel in mute mode.

Parameters
pI2S: The base of I2S peripheral on the chip
TRMode: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
Returns
Nothing

Definition at line 194 of file i2s_001.c.

uint32_t IP_I2S_Receive ( IP_I2S_001_T *  pI2S)

Get received data from RXFIFO.

Parameters
pI2S: The base of I2S peripheral on the chip
Returns
Data received in RXFIFO
Note
The function reads from RXFIFO without checking any condition.

Definition at line 177 of file i2s_001.c.

void IP_I2S_Send ( IP_I2S_001_T *  pI2S,
uint32_t  data 
)

Send a 32-bit data to TXFIFO for transmition.

Parameters
pI2S: The base of I2S peripheral on the chip
data: Data to be transmited
Returns
Nothing
Note
The function writes to TXFIFO without checking any condition.

Definition at line 171 of file i2s_001.c.

void IP_I2S_SetBitRate ( IP_I2S_001_T *  pI2S,
uint8_t  TRMode,
uint32_t  mclk_divider 
)

Set the clock frequency for I2S interface.

Parameters
pI2S: The base of I2S peripheral on the chip
TRMode: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
mclk_divider: Clock divider. This value plus one is used to divide MCLK to produce the clock frequency for I2S interface
Returns
Nothing
Note
The value depends on the audio sample rate desired and the data size and format(stereo/mono) used. For example, a 48 kHz sample rate for 16-bit stereo data requires a bit rate of 48 000 x 16 x 2 = 1.536 MHz. So the mclk_divider should be MCLK/1.536 MHz

Definition at line 111 of file i2s_001.c.

void IP_I2S_SetFIFODepthDMA ( IP_I2S_001_T *  pI2S,
uint8_t  TRMode,
IP_I2S_DMARequestNumber_T  DMANum,
uint32_t  depth 
)

Set the FIFO level on which to create an DMA request.

Parameters
pI2S: The base of I2S peripheral on the chip
TRMode: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
DMANum: I2S DMA request number, should be
  • IP_I2S_DMA_REQUEST_NUMBER_1
  • IP_I2S_DMA_REQUEST_NUMBER_2
depth: FIFO level on which to create an DMA request
Returns
Nothing
Note
DMA request is generated when rx_depth_dma <= rx_level or tx_depth_dma >= tx_level

Definition at line 260 of file i2s_001.c.

void IP_I2S_SetFIFODepthIRQ ( IP_I2S_001_T *  pI2S,
uint8_t  TRMode,
uint32_t  depth 
)

Set the FIFO level on which to create an irq request.

Parameters
pI2S: The base of I2S peripheral on the chip
TRMode: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
depth: FIFO level on which to create an irq request
Returns
Nothing

Definition at line 298 of file i2s_001.c.

void IP_I2S_SetMasterSlaveMode ( IP_I2S_001_T *  pI2S,
uint8_t  TRMode,
uint32_t  mode 
)

Set I2S interface in master/slave mode.

Parameters
pI2S: The base of I2S peripheral on the chip
TRMode: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
mode: Interface mode, should be
  • I2S_MASTER_MODE
  • I2S_SLAVE_MODE
Returns
Nothing

Definition at line 97 of file i2s_001.c.

void IP_I2S_SetMono ( IP_I2S_001_T *  pI2S,
uint8_t  TRMode,
uint32_t  mono 
)

Set I2S data format to mono or stereo.

Parameters
pI2S: The base of I2S peripheral on the chip
TRMode: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
mono: Data channel, should be
  • I2S_STEREO
  • I2S_MONO
Returns
Nothing

Definition at line 83 of file i2s_001.c.

void IP_I2S_SetWordWidth ( IP_I2S_001_T *  pI2S,
uint8_t  TRMode,
uint32_t  wordwidth 
)

Set the data width for the specified mode.

Parameters
pI2S: The base of I2S peripheral on the chip
TRMode: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
wordwidth: Data width, should be :
  • I2S_WORDWIDTH_8
  • I2S_WORDWIDTH_16
  • I2S_WORDWIDTH_32
Returns
Nothing

Definition at line 69 of file i2s_001.c.

void IP_I2S_SetWS_Halfperiod ( IP_I2S_001_T *  pI2S,
uint8_t  TRMode,
uint32_t  ws_halfperiod 
)

Set word select (WS) half period.

Parameters
pI2S: The base of I2S peripheral on the chip
TRMode: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
ws_halfperiod: I2S word select half period minus one
Returns
Nothing
Note
The Word Select period is configured separately for I2S input and I2S output. For example: if the WS is 64clk period -> ws_halfperiod = 31

Definition at line 133 of file i2s_001.c.

void IP_I2S_SetXYDivider ( IP_I2S_001_T *  pI2S,
uint8_t  TRMode,
uint8_t  x_divider,
uint8_t  y_devider 
)

Set the MCLK rate by using a fractional rate generator, dividing down the frequency of PCLK.

Parameters
pI2S: The base of I2S peripheral on the chip
TRMode: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
x_divider: I2S transmit MCLK rate numerator
y_devider: I2S transmit MCLK rate denominator
Returns
Nothing
Note
Values of the numerator (X) and the denominator (Y) must be chosen to produce a frequency twice that desired for the transmitter MCLK, which must be an integer multiple of the transmitter bit clock rate. The equation for the fractional rate generator is: MCLK = PCLK * (X/Y) /2 Note: If the value of X or Y is 0, then no clock is generated. Also, the value of Y must be greater than or equal to X.

Definition at line 122 of file i2s_001.c.

void IP_I2S_Start ( IP_I2S_001_T *  pI2S,
uint8_t  TRMode 
)

Start the I2S.

Parameters
pI2S: The base of I2S peripheral on the chip
TRMode: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
Returns
Nothing

Definition at line 183 of file i2s_001.c.

void IP_I2S_Stop ( IP_I2S_001_T *  pI2S,
uint8_t  TRMode 
)

Stop I2S asynchronously.

Parameters
pI2S: The base of I2S peripheral on the chip
TRMode: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
Returns
Nothing
Note
Pause, resets the transmit channel and FIFO asynchronously

Definition at line 205 of file i2s_001.c.