i2c_001.h

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/*
 * @brief I2C registers and driver functions
 *
 * @note
 * Copyright(C) NXP Semiconductors, 2012
 * All rights reserved.
 *
 * @par
 * Software that is described herein is for illustrative purposes only
 * which provides customers with programming information regarding the
 * LPC products.  This software is supplied "AS IS" without any warranties of
 * any kind, and NXP Semiconductors and its licensor disclaim any and
 * all warranties, express or implied, including all implied warranties of
 * merchantability, fitness for a particular purpose and non-infringement of
 * intellectual property rights.  NXP Semiconductors assumes no responsibility
 * or liability for the use of the software, conveys no license or rights under any
 * patent, copyright, mask work right, or any other intellectual property rights in
 * or to any products. NXP Semiconductors reserves the right to make changes
 * in the software without notification. NXP Semiconductors also makes no
 * representation or warranty that such application will be suitable for the
 * specified use without further testing or modification.
 *
 * @par
 * Permission to use, copy, modify, and distribute this software and its
 * documentation is hereby granted, under NXP Semiconductors' and its
 * licensor's relevant copyrights in the software, without fee, provided that it
 * is used in conjunction with NXP Semiconductors microcontrollers.  This
 * copyright, permission, and disclaimer notice must appear in all copies of
 * this code.
 */

#ifndef __I2C_001_H_
#define __I2C_001_H_

#include "sys_config.h"
#include "cmsis.h"

#ifdef __cplusplus
extern "C" {
#endif

typedef struct {    /* I2C0 Structure         */
 __IO uint32_t CONSET;  
 __I  uint32_t STAT;   
 __IO uint32_t DAT;   
 __IO uint32_t ADR0;   
 __IO uint32_t SCLH;   
 __IO uint32_t SCLL;   
 __O  uint32_t CONCLR;  
 __IO uint32_t MMCTRL;  
 __IO uint32_t ADR1;   
 __IO uint32_t ADR2;   
 __IO uint32_t ADR3;   
 __I  uint32_t DATA_BUFFER; 
 __IO uint32_t MASK[4];  
} IP_I2C_001_T;

#define RET_SLAVE_TX    6 
#define RET_SLAVE_RX    5 
#define RET_SLAVE_IDLE  2 
#define RET_SLAVE_BUSY  0 
#define I2C_STA_STO_RECV            0x20

/*
 * @brief I2C Control Set register description
 */
#define I2C_I2CONSET_AA             ((0x04))
#define I2C_I2CONSET_SI             ((0x08))
#define I2C_I2CONSET_STO            ((0x10))
#define I2C_I2CONSET_STA            ((0x20))
#define I2C_I2CONSET_I2EN           ((0x40))
/*
 * @brief I2C Control Clear register description
 */
#define I2C_I2CONCLR_AAC            ((1 << 2)) 
#define I2C_I2CONCLR_SIC            ((1 << 3)) 
#define I2C_I2CONCLR_STOC           ((1 << 4)) 
#define I2C_I2CONCLR_STAC           ((1 << 5)) 
#define I2C_I2CONCLR_I2ENC          ((1 << 6)) 
/*
 * @brief I2C Common Control register description
 */
#define I2C_CON_AA            (1UL << 2) 
#define I2C_CON_SI            (1UL << 3) 
#define I2C_CON_STO           (1UL << 4) 
#define I2C_CON_STA           (1UL << 5) 
#define I2C_CON_I2EN          (1UL << 6) 
/*
 * @brief I2C Status Code definition (I2C Status register)
 */
#define I2C_STAT_CODE_BITMASK       ((0xF8))
#define I2C_STAT_CODE_ERROR         ((0xFF))
/*
 * @brief I2C return status code definitions
 */
#define I2C_I2STAT_NO_INF                       ((0xF8))
#define I2C_I2STAT_BUS_ERROR                    ((0x00))
/*
 * @brief I2C Master transmit mode
 */
#define I2C_I2STAT_M_TX_START                   ((0x08))
#define I2C_I2STAT_M_TX_RESTART                 ((0x10))
#define I2C_I2STAT_M_TX_SLAW_ACK                ((0x18))
#define I2C_I2STAT_M_TX_SLAW_NACK               ((0x20))
#define I2C_I2STAT_M_TX_DAT_ACK                 ((0x28))
#define I2C_I2STAT_M_TX_DAT_NACK                ((0x30))
#define I2C_I2STAT_M_TX_ARB_LOST                ((0x38))
/*
 * @brief I2C Master receive mode
 */
#define I2C_I2STAT_M_RX_START                   ((0x08))
#define I2C_I2STAT_M_RX_RESTART                 ((0x10))
#define I2C_I2STAT_M_RX_ARB_LOST                ((0x38))
#define I2C_I2STAT_M_RX_SLAR_ACK                ((0x40))
#define I2C_I2STAT_M_RX_SLAR_NACK               ((0x48))
#define I2C_I2STAT_M_RX_DAT_ACK                 ((0x50))
#define I2C_I2STAT_M_RX_DAT_NACK                ((0x58))
/*
 * @brief I2C Slave receive mode
 */
#define I2C_I2STAT_S_RX_SLAW_ACK                ((0x60))
#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA          ((0x68))
// #define I2C_I2STAT_S_RX_SLAW_ACK    ((0x68)) 
#define I2C_I2STAT_S_RX_GENCALL_ACK             ((0x70))
#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL      ((0x78))
// #define I2C_I2STAT_S_RX_GENCALL_ACK    ((0x78)) 
#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK         ((0x80))
#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK        ((0x88))
#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK     ((0x90))
#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK    ((0x98))
#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX   ((0xA0))
/*
 * @brief I2C Slave transmit mode
 */
#define I2C_I2STAT_S_TX_SLAR_ACK                ((0xA8))
#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA          ((0xB0))
// #define I2C_I2STAT_S_TX_SLAR_ACK    ((0xB0)) 
#define I2C_I2STAT_S_TX_DAT_ACK                 ((0xB8))
#define I2C_I2STAT_S_TX_DAT_NACK                ((0xC0))
#define I2C_I2STAT_S_TX_LAST_DAT_ACK            ((0xC8))
#define I2C_SLAVE_TIME_OUT                      0x10000000UL
/*
 * @brief I2C Data register definition
 */
#define I2C_I2DAT_BITMASK           ((0xFF))
#define I2C_I2DAT_IDLE_CHAR         (0xFF) 
/*
 * @brief I2C Monitor mode control register description
 */
#define I2C_I2MMCTRL_MM_ENA         ((1 << 0))   
#define I2C_I2MMCTRL_ENA_SCL        ((1 << 1))   
#define I2C_I2MMCTRL_MATCH_ALL      ((1 << 2))   
#define I2C_I2MMCTRL_BITMASK        ((0x07))  
/*
 * @brief I2C Data buffer register description
 */
#define I2DATA_BUFFER_BITMASK       ((0xFF))
/*
 * @brief I2C Slave Address registers definition
 */
#define I2C_I2ADR_GC                ((1 << 0)) 
#define I2C_I2ADR_BITMASK           ((0xFF))
/*
 * @brief I2C Mask Register definition
 */
#define I2C_I2MASK_MASK(n)          ((n & 0xFE))
/*
 * @brief I2C SCL HIGH duty cycle Register definition
 */
#define I2C_I2SCLH_BITMASK          ((0xFFFF)) 
/*
 * @brief I2C SCL LOW duty cycle Register definition
 */
#define I2C_I2SCLL_BITMASK          ((0xFFFF)) 
/*
 * @brief I2C status values
 */
#define I2C_SETUP_STATUS_ARBF   (1 << 8) 
#define I2C_SETUP_STATUS_NOACKF (1 << 9) 
#define I2C_SETUP_STATUS_DONE   (1 << 10) 
/*
 * @brief I2C state handle return values
 */
#define I2C_OK                      0x00
#define I2C_BYTE_SENT               0x01
#define I2C_BYTE_RECV               0x02
#define I2C_LAST_BYTE_RECV          0x04
#define I2C_SEND_END                0x08
#define I2C_RECV_END                0x10
#define I2C_STA_STO_RECV            0x20

#define I2C_ERR                     (0x10000000)
#define I2C_NAK_RECV                (0x10000000 | 0x01)

#define I2C_CheckError(ErrorCode)   (ErrorCode & 0x10000000)

/*
 * @brief I2C monitor control configuration defines
 */
#define I2C_MONITOR_CFG_SCL_OUTPUT  I2C_I2MMCTRL_ENA_SCL  
#define I2C_MONITOR_CFG_MATCHALL    I2C_I2MMCTRL_MATCH_ALL  
typedef enum {
 I2C_SLAVE_GENERAL, 
 I2C_SLAVE_0,  
 I2C_SLAVE_1,  
 I2C_SLAVE_2,  
 I2C_SLAVE_3,  
 I2C_SLAVE_NUM_INTERFACE 
} I2C_SLAVE_ID;

typedef enum {
 I2C_STATUS_DONE, 
 I2C_STATUS_NAK,  
 I2C_STATUS_ARBLOST, 
 I2C_STATUS_BUSERR, 
 I2C_STATUS_BUSY, 
} I2C_STATUS_T;

typedef struct {
 uint8_t slaveAddr;  
 const uint8_t *txBuff; 
 int     txSz;   
 uint8_t *rxBuff;  
 int     rxSz;   
 I2C_STATUS_T status; 
} I2C_XFER_T;

STATIC INLINE void IP_I2C_Init(IP_I2C_001_T *pI2C)
{
 /* Set I2C operation to default */
 pI2C->CONCLR = (I2C_CON_AA | I2C_CON_SI | I2C_CON_STA | I2C_CON_I2EN);
}

STATIC INLINE void IP_I2C_DeInit(IP_I2C_001_T *pI2C)
{
 /* Disable I2C control */
 pI2C->CONCLR = I2C_CON_I2EN | I2C_CON_SI | I2C_CON_STO | I2C_CON_STA | I2C_CON_AA;
}

STATIC INLINE void IP_I2C_SetClockRate(IP_I2C_001_T *pI2C, uint32_t SCLValue)
{
 pI2C->SCLH = (uint32_t) (SCLValue >> 1);
 pI2C->SCLL = (uint32_t) (SCLValue - pI2C->SCLH);
}

STATIC INLINE uint32_t IP_I2C_GetClockDiv(IP_I2C_001_T *pI2C)
{
 return pI2C->SCLH + pI2C->SCLL;
}

STATIC INLINE void IP_I2C_Master_StartXfer(IP_I2C_001_T *pI2C)
{
 /* Reset STA, STO, SI */
 pI2C->CONCLR = I2C_CON_SI | I2C_CON_STO | I2C_CON_STA | I2C_CON_AA;

 /* Enter to Master Transmitter mode */
 pI2C->CONSET = I2C_CON_I2EN | I2C_CON_STA;
}

int IP_I2C_MasterXfer_StateHandler(IP_I2C_001_T *pI2C, I2C_XFER_T  *xfer);

STATIC INLINE int IP_I2C_IsStateChanged(IP_I2C_001_T *pI2C)
{
 return (pI2C->CONSET & I2C_CON_SI) != 0;
}

STATIC INLINE void IP_I2C_Disable(IP_I2C_001_T *pI2C)
{
 pI2C->CONCLR = I2C_I2CONCLR_I2ENC;
}

STATIC INLINE void IP_I2C_SetSlaveAddress(IP_I2C_001_T *pI2C, I2C_SLAVE_ID sid, uint8_t addr, uint8_t mask)
{
 uint32_t index = (uint32_t) sid - 1;
 pI2C->MASK[index] = mask;
 if (sid == I2C_SLAVE_0) {
  pI2C->ADR0 = addr;
 }
 else {
  volatile uint32_t *abase = &pI2C->ADR1;
  abase[index - 1] = addr;
 }
}

STATIC INLINE int IP_I2C_GetCurrentState(IP_I2C_001_T *pI2C)
{
 return (int) (pI2C->STAT & I2C_STAT_CODE_BITMASK);
}

I2C_SLAVE_ID IP_I2C_GetSlaveIndex(IP_I2C_001_T *pI2C);

int IP_I2C_SlaveXfer_StateHandler(IP_I2C_001_T *pI2C, I2C_XFER_T *xfer);

STATIC INLINE void IP_I2C_Slave_StartXfer(IP_I2C_001_T *pI2C)
{
 /* Reset STA, STO, SI */
 pI2C->CONCLR = I2C_CON_SI | I2C_CON_STO | I2C_CON_STA;

 /* Enter to Master Transmitter mode */
 pI2C->CONSET = I2C_CON_I2EN | I2C_CON_AA;
}

STATIC INLINE int IP_I2C_BusFree(IP_I2C_001_T *pI2C)
{
 return !(pI2C->CONSET & I2C_CON_STO);
}

STATIC INLINE int IP_I2C_IsMasterState(IP_I2C_001_T *pI2C)
{
 return IP_I2C_GetCurrentState(pI2C) < 0x60;
}

#ifdef __cplusplus
}
#endif

#endif /* __I2C_001_H_ */