#include "sys_config.h"
#include "cmsis.h"

Go to the source code of this file.

Data Structures
struct	IP_I2S_001_T
	I2S register block structure. More...

Macros
#define	I2S_WORDWIDTH_8 (0UL << 0)
	I2S configuration parameter defines.

#define	I2S_WORDWIDTH_16 (1UL << 0)

#define	I2S_WORDWIDTH_32 (3UL << 0)

#define	I2S_STEREO (0UL << 2)

#define	I2S_MONO (1UL << 2)

#define	I2S_MASTER_MODE (0UL << 5)

#define	I2S_SLAVE_MODE (1UL << 5)

#define	I2S_STOP_ENABLE (0UL << 3)

#define	I2S_STOP_DISABLE (1UL << 3)

#define	I2S_RESET_ENABLE (1UL << 4)

#define	I2S_RESET_DISABLE (0UL << 4)

#define	I2S_MUTE_ENABLE (1UL << 15)

#define	I2S_MUTE_DISABLE (0UL << 15)

#define	I2S_DAO_WORDWIDTH_8 ((uint32_t) (0))
	Macro defines for DAO-Digital Audio Output register.

#define	I2S_DAO_WORDWIDTH_16 ((uint32_t) (1))

#define	I2S_DAO_WORDWIDTH_32 ((uint32_t) (3))

#define	I2S_DAO_WORDWIDTH_MASK ((uint32_t) (3))

#define	I2S_DAO_MONO ((uint32_t) (1 << 2))

#define	I2S_DAO_STOP ((uint32_t) (1 << 3))

#define	I2S_DAO_RESET ((uint32_t) (1 << 4))

#define	I2S_DAO_SLAVE ((uint32_t) (1 << 5))

#define	I2S_DAO_WS_HALFPERIOD(n) ((uint32_t) ((n & 0x1FF) << 6))

#define	I2S_DAO_WS_HALFPERIOD_MASK ((uint32_t) ((0x1FF) << 6))

#define	I2S_DAO_MUTE ((uint32_t) (1 << 15))

#define	I2S_DAI_WORDWIDTH_8 ((uint32_t) (0))
	Macro defines for DAI-Digital Audio Input register.

#define	I2S_DAI_WORDWIDTH_16 ((uint32_t) (1))

#define	I2S_DAI_WORDWIDTH_32 ((uint32_t) (3))

#define	I2S_DAI_WORDWIDTH_MASK ((uint32_t) (3))

#define	I2S_DAI_MONO ((uint32_t) (1 << 2))

#define	I2S_DAI_STOP ((uint32_t) (1 << 3))

#define	I2S_DAI_RESET ((uint32_t) (1 << 4))

#define	I2S_DAI_SLAVE ((uint32_t) (1 << 5))

#define	I2S_DAI_WS_HALFPERIOD(n) ((uint32_t) ((n & 0x1FF) << 6))

#define	I2S_DAI_WS_HALFPERIOD_MASK ((uint32_t) ((0x1FF) << 6))

#define	I2S_STATE_IRQ ((uint32_t) (1))
	Macro defines for STAT register (Status Feedback register)

#define	I2S_STATE_DMA1 ((uint32_t) (1 << 1))

#define	I2S_STATE_DMA2 ((uint32_t) (1 << 2))

#define	I2S_STATE_RX_LEVEL(n) ((uint32_t) ((n & 1F) << 8))

#define	I2S_STATE_TX_LEVEL(n) ((uint32_t) ((n & 1F) << 16))

#define	I2S_DMA1_RX_ENABLE ((uint32_t) (1))
	Macro defines for DMA1 register (DMA1 Configuration register)

#define	I2S_DMA1_TX_ENABLE ((uint32_t) (1 << 1))

#define	I2S_DMA1_RX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 8))

#define	I2S_DMA1_TX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 16))

#define	I2S_DMA2_RX_ENABLE ((uint32_t) (1))
	Macro defines for DMA2 register (DMA2 Configuration register)

#define	I2S_DMA2_TX_ENABLE ((uint32_t) (1 << 1))

#define	I2S_DMA2_RX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 8))

#define	I2S_DMA2_TX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 16))

#define	I2S_IRQ_RX_ENABLE ((uint32_t) (1))
	Macro defines for IRQ register (Interrupt Request Control register)

#define	I2S_IRQ_TX_ENABLE ((uint32_t) (1 << 1))

#define	I2S_IRQ_RX_DEPTH(n) ((uint32_t) ((n & 0x0F) << 8))

#define	I2S_IRQ_RX_DEPTH_MASK ((uint32_t) ((0x0F) << 8))

#define	I2S_IRQ_TX_DEPTH(n) ((uint32_t) ((n & 0x0F) << 16))

#define	I2S_IRQ_TX_DEPTH_MASK ((uint32_t) ((0x0F) << 16))

#define	I2S_TXRATE_Y_DIVIDER(n) ((uint32_t) (n & 0xFF))
	Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register)

#define	I2S_TXRATE_X_DIVIDER(n) ((uint32_t) ((n & 0xFF) << 8))

#define	I2S_RXRATE_Y_DIVIDER(n) ((uint32_t) (n & 0xFF))

#define	I2S_RXRATE_X_DIVIDER(n) ((uint32_t) ((n & 0xFF) << 8))

#define	I2S_TXBITRATE(n) ((uint32_t) (n & 0x3F))
	Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register)

#define	I2S_RXBITRATE(n) ((uint32_t) (n & 0x3F))

#define	I2S_TXMODE_CLKSEL(n) ((uint32_t) (n & 0x03))
	Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register)

#define	I2S_TXMODE_4PIN_ENABLE ((uint32_t) (1 << 2))

#define	I2S_TXMODE_MCENA ((uint32_t) (1 << 3))

#define	I2S_RXMODE_CLKSEL(n) ((uint32_t) (n & 0x03))

#define	I2S_RXMODE_4PIN_ENABLE ((uint32_t) (1 << 2))

#define	I2S_RXMODE_MCENA ((uint32_t) (1 << 3))

Enumerations
enum	IP_I2S_TRxMode_T { I2S_TX_MODE, I2S_RX_MODE }
	I2S transmit/receive mode for configuration. More...

enum	IP_I2S_DMARequestNumber_T { IP_I2S_DMA_REQUEST_NUMBER_1, IP_I2S_DMA_REQUEST_NUMBER_2 }
	I2S DMA request channel define. More...

Functions
void	IP_I2S_Init (IP_I2S_001_T *pI2S)
	Initialize for I2S.

void	IP_I2S_DeInit (IP_I2S_001_T *pI2S)
	Shutdown I2S.

void	IP_I2S_SetWordWidth (IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t wordwidth)
	Set the data width for the specified mode.

void	IP_I2S_SetMono (IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t mono)
	Set I2S data format to mono or stereo.

void	IP_I2S_SetMasterSlaveMode (IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t mode)
	Set I2S interface in master/slave mode.

void	IP_I2S_SetBitRate (IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t mclk_divider)
	Set the clock frequency for I2S interface.

void	IP_I2S_SetXYDivider (IP_I2S_001_T *pI2S, uint8_t TRMode, uint8_t x_divider, uint8_t y_devider)
	Set the MCLK rate by using a fractional rate generator, dividing down the frequency of PCLK.

void	IP_I2S_SetWS_Halfperiod (IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t ws_halfperiod)
	Set word select (WS) half period.

void	IP_I2S_ModeConfig (IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t clksel, uint32_t fpin, uint32_t mcena)
	Set the I2S operating modes.

uint8_t	IP_I2S_GetLevel (IP_I2S_001_T *pI2S, uint8_t TRMode)
	Get the current level of the Transmit/Receive FIFO.

void	IP_I2S_Send (IP_I2S_001_T *pI2S, uint32_t data)
	Send a 32-bit data to TXFIFO for transmition.

uint32_t	IP_I2S_Receive (IP_I2S_001_T *pI2S)
	Get received data from RXFIFO.

void	IP_I2S_Start (IP_I2S_001_T *pI2S, uint8_t TRMode)
	Start the I2S.

void	IP_I2S_Pause (IP_I2S_001_T *pI2S, uint8_t TRMode)
	Disables accesses on FIFOs, places the transmit channel in mute mode.

STATIC INLINE void	IP_I2S_EnableMute (IP_I2S_001_T *pI2S)
	Transmit channel sends only zeroes.

STATIC INLINE void	IP_I2S_DisableMute (IP_I2S_001_T *pI2S)
	Un-Mute the I2S channel.

void	IP_I2S_Stop (IP_I2S_001_T *pI2S, uint8_t TRMode)
	Stop I2S asynchronously.

void	IP_I2S_SetFIFODepthDMA (IP_I2S_001_T *pI2S, uint8_t TRMode, IP_I2S_DMARequestNumber_T DMANum, uint32_t depth)
	Set the FIFO level on which to create an DMA request.

void	IP_I2S_DMACmd (IP_I2S_001_T *pI2S, IP_I2S_DMARequestNumber_T DMANum, uint8_t TRMode, FunctionalState NewState)
	Enable/Disable DMA for the I2S.

void	IP_I2S_InterruptCmd (IP_I2S_001_T *pI2S, uint8_t TRMode, FunctionalState NewState)
	Enable/Disable interrupt for the I2S.

void	IP_I2S_SetFIFODepthIRQ (IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t depth)
	Set the FIFO level on which to create an irq request.

Status	IP_I2S_GetIntStatus (IP_I2S_001_T *pI2S, uint8_t TRMode)
	Get the status of I2S interrupt.

Data Structures

Macros

Enumerations

Functions