mrt_001.h

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/*
 * @brief Multi-Rate Timer (MRT) registers and driver functions
 *
 * @note
 * Copyright(C) NXP Semiconductors, 2012
 * All rights reserved.
 *
 * @par
 * Software that is described herein is for illustrative purposes only
 * which provides customers with programming information regarding the
 * LPC products.  This software is supplied "AS IS" without any warranties of
 * any kind, and NXP Semiconductors and its licensor disclaim any and
 * all warranties, express or implied, including all implied warranties of
 * merchantability, fitness for a particular purpose and non-infringement of
 * intellectual property rights.  NXP Semiconductors assumes no responsibility
 * or liability for the use of the software, conveys no license or rights under any
 * patent, copyright, mask work right, or any other intellectual property rights in
 * or to any products. NXP Semiconductors reserves the right to make changes
 * in the software without notification. NXP Semiconductors also makes no
 * representation or warranty that such application will be suitable for the
 * specified use without further testing or modification.
 *
 * @par
 * Permission to use, copy, modify, and distribute this software and its
 * documentation is hereby granted, under NXP Semiconductors' and its
 * licensor's relevant copyrights in the software, without fee, provided that it
 * is used in conjunction with NXP Semiconductors microcontrollers.  This
 * copyright, permission, and disclaimer notice must appear in all copies of
 * this code.
 */

#ifndef __MRT_001_H_
#define __MRT_001_H_

#include "sys_config.h"
#include "cmsis.h"

#ifdef __cplusplus
extern "C" {
#endif

typedef struct {
 __IO uint32_t INTVAL; 
 __O  uint32_t TIMER; 
 __IO uint32_t CTRL;  
 __IO uint32_t STAT;  
} IP_MRT_001_T;

/* MRT Time interval register bit fields */
#define IP_MRT_001_INTVAL_IVALUE        (0xFFFFFF)
#define IP_MRT_001_INTVAL_LOAD          (1 << 31)

/* MRT Control register bit fields & masks */
#define IP_MRT_001_CTRL_MODE_REPEAT     (0x00)
#define IP_MRT_001_CTRL_MODE_ONESHOT    (0x01)
#define IP_MRT_001_CTRL_INTEN_MASK      (0x01)
#define IP_MRT_001_CTRL_MODE_POS        (0x01)
#define IP_MRT_001_CTRL_MODE_MASK       (0x06)
#define IP_MRT_001_CTRL_MODE_SHIFT(x)   (x << 1)

/* MRT Status register bit fields & masks */
#define IP_MRT_001_STAT_INTFLAG         (0x01)
#define IP_MRT_001_STAT_RUNNING         (0x02)

typedef enum IP_MRT_001_MODE {
 MRT_MODE_REPEAT = 0, 
 MRT_MODE_ONESHOT = 1 
} IP_MRT_001_MODE_T;

STATIC INLINE void IP_MRT_Init(void)
{}

STATIC INLINE void IP_MRT_DeInit(void)
{}

STATIC INLINE uint32_t IP_MRT_GetInterval(IP_MRT_001_T *pMRT)
{
 return (uint32_t) pMRT->INTVAL;
}

STATIC INLINE void IP_MRT_SetInterval(IP_MRT_001_T *pMRT, uint32_t interval)
{
 pMRT->INTVAL = interval;
}

STATIC INLINE uint32_t IP_MRT_GetTimer(IP_MRT_001_T *pMRT)
{
 return (uint32_t) pMRT->TIMER;
}

STATIC INLINE bool IP_MRT_GetEnabled(IP_MRT_001_T *pMRT)
{
 return (bool) (pMRT->CTRL & IP_MRT_001_CTRL_INTEN_MASK);
}

STATIC INLINE void IP_MRT_SetEnabled(IP_MRT_001_T *pMRT)
{
 pMRT->CTRL |= IP_MRT_001_CTRL_INTEN_MASK;
}

STATIC INLINE IP_MRT_001_MODE_T IP_MRT_GetMode(IP_MRT_001_T *pMRT)
{
 return (IP_MRT_001_MODE_T) ((pMRT->CTRL & IP_MRT_001_CTRL_MODE_MASK) >> 1);
}

STATIC INLINE void IP_MRT_SetMode(IP_MRT_001_T *pMRT, IP_MRT_001_MODE_T mode)
{
 pMRT->CTRL |= IP_MRT_001_CTRL_MODE_SHIFT(mode);
}

STATIC INLINE bool IP_MRT_IsRepeatMode(IP_MRT_001_T *pMRT)
{
 return ((pMRT->CTRL & IP_MRT_001_CTRL_MODE_MASK) > 0) ? false : true;
}

STATIC INLINE bool IP_MRT_IsOneShotMode(IP_MRT_001_T *pMRT)
{
 return ((pMRT->CTRL & IP_MRT_001_CTRL_MODE_MASK) > 0) ? true : false;
}

STATIC INLINE bool IP_MRT_IntPending(IP_MRT_001_T *pMRT)
{
 return (bool) (pMRT->STAT & IP_MRT_001_STAT_INTFLAG);
}

STATIC INLINE void IP_MRT_IntClear(IP_MRT_001_T *pMRT)
{
 pMRT->STAT |= IP_MRT_001_STAT_INTFLAG;
}

STATIC INLINE bool IP_MRT_Running(IP_MRT_001_T *pMRT)
{
 return (bool) (pMRT->STAT & IP_MRT_001_STAT_RUNNING);
}

#ifdef __cplusplus
}
#endif

#endif /* __MRT_001_H_ */