pinint_8xx.h

Go to the documentation of this file.

/*
 * @brief LPC8xx Pin Interrupt and Pattern Match Registers and driver
 *
 * @note
 * Copyright(C) NXP Semiconductors, 2012
 * All rights reserved.
 *
 * @par
 * Software that is described herein is for illustrative purposes only
 * which provides customers with programming information regarding the
 * LPC products.  This software is supplied "AS IS" without any warranties of
 * any kind, and NXP Semiconductors and its licensor disclaim any and
 * all warranties, express or implied, including all implied warranties of
 * merchantability, fitness for a particular purpose and non-infringement of
 * intellectual property rights.  NXP Semiconductors assumes no responsibility
 * or liability for the use of the software, conveys no license or rights under any
 * patent, copyright, mask work right, or any other intellectual property rights in
 * or to any products. NXP Semiconductors reserves the right to make changes
 * in the software without notification. NXP Semiconductors also makes no
 * representation or warranty that such application will be suitable for the
 * specified use without further testing or modification.
 *
 * @par
 * Permission to use, copy, modify, and distribute this software and its
 * documentation is hereby granted, under NXP Semiconductors' and its
 * licensor's relevant copyrights in the software, without fee, provided that it
 * is used in conjunction with NXP Semiconductors microcontrollers.  This
 * copyright, permission, and disclaimer notice must appear in all copies of
 * this code.
 */

#ifndef __PIN_INT_8XX_H_
#define __PIN_INT_8XX_H_

#ifdef __cplusplus
extern "C" {
#endif

typedef struct {       
 __IO uint32_t ISEL;      
 __IO uint32_t IENR;      
 __IO uint32_t SIENR;     
 __IO uint32_t CIENR;     
 __IO uint32_t IENF;      
 __IO uint32_t SIENF;     
 __IO uint32_t CIENF;     
 __IO uint32_t RISE;      
 __IO uint32_t FALL;      
 __IO uint32_t IST;      
 __IO uint32_t PMCTRL;     
 __IO uint32_t PMSRC;     
 __IO uint32_t PMCFG;     
} LPC_PIN_INT_T;

#define PMODE_EDGE                  (0) 
#define PMODE_LEVEL                 (1) 
#define PMODE_SET(t, p, x)          (x ? (t->ISEL |= (x << p)) : (t->ISEL &= ~(1 << p)))

#define ENRL_DISABLE                (0) 
#define ENRL_ENABLE                 (1) 
#define ENRL_SET(t, p, x)           (x ? (t->IENR |= (x << p)) : (t->IENR &= ~(1 << p)))

#define SETENRL(t, p)               (t->SIENR |= (1 << p)) 
#define CENRL(t, p)                 (t->CIENR |= (1 << p)) 
#define ENAF_LOW                    (0) 
#define ENAF_HIGH                   (1) 
#define ENAF_SET(t, p, x)           (x ? (t->IENF |= (x << p)) : (t->IENF &= ~(1 << p)))

#define SETENAF(t, p)               (t->SIENF |= (1 << p)) 
#define CENAF(t, p)                 (t->CIENF |= (1 << p)) 
#define RDET_CLR(t, p)              (t->RISE |= (1 << p))

#define FDET_CLR(t, p)              (t->FALL |= (1 << p))

#define PSTAT_CRL(t, p)             (t->IST |= (1 << p))

typedef enum CHIP_PMI_PIN {
 PMI0 = 0, 
 PMI1 = 1, 
 PMI2 = 2, 
 PMI3 = 3, 
 PMI4 = 4, 
 PMI5 = 5, 
 PMI6 = 6, 
 PMI7 = 7 
} CHIP_PMI_PIN_T;

typedef enum CHIP_PINT_CFG {
 PINT_ACTIVE_LOW = 0, 
 PINT_ACTIVE_HIGH = 1, 
 PINT_EDGE_DET = 2,  
 PINT_LEVEL_DET = 4,  
 PINT_RISING = 8,  
 PINT_FALLING = 16  
} CHIP_PINT_CFG_T;

void Chip_PININT_Config(CHIP_PMI_PIN_T pin, CHIP_PINT_CFG_T cfg);

#ifdef __cplusplus
}
#endif

#endif /* __PIN_INT_8XX_H_ */