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sct_001.h
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1 /*
2  * @brief State Configurable Timer registers and control functions
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2012
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #ifndef __SCT_001_H_
33 #define __SCT_001_H_
34 
35 #include "sys_config.h"
36 #include "cmsis.h"
37 
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41 
51 #define CONFIG_SCT_nEV (16)
52 #define CONFIG_SCT_nRG (16)
53 #define CONFIG_SCT_nOU (16)
58 typedef struct {
59  __IO uint32_t CONFIG;
60  union {
61  __IO uint32_t CTRL_U;
62  struct {
63  __IO uint16_t CTRL_L;
64  __IO uint16_t CTRL_H;
65  };
66 
67  };
68 
69  __IO uint16_t LIMIT_L;
70  __IO uint16_t LIMIT_H;
71  __IO uint16_t HALT_L;
72  __IO uint16_t HALT_H;
73  __IO uint16_t STOP_L;
74  __IO uint16_t STOP_H;
75  __IO uint16_t START_L;
76  __IO uint16_t START_H;
77  uint32_t RESERVED1[10];
78  union {
79  __IO uint32_t COUNT_U;
80  struct {
81  __IO uint16_t COUNT_L;
82  __IO uint16_t COUNT_H;
83  };
84 
85  };
86 
87  __IO uint16_t STATE_L;
88  __IO uint16_t STATE_H;
89  __I uint32_t INPUT;
90  __IO uint16_t REGMODE_L;
91  __IO uint16_t REGMODE_H;
92  __IO uint32_t OUTPUT;
93  __IO uint32_t OUTPUTDIRCTRL;
94  __IO uint32_t RES;
95  __IO uint32_t DMA0REQUEST;
96  __IO uint32_t DMA1REQUEST;
97  uint32_t RESERVED2[35];
98  __IO uint32_t EVEN;
99  __IO uint32_t EVFLAG;
100  __IO uint32_t CONEN;
101  __IO uint32_t CONFLAG;
102  union {
103  __IO union {
104  uint32_t U;
105  struct {
106  uint16_t L;
107  uint16_t H;
108  };
109 
110  } MATCH[CONFIG_SCT_nRG];
111 
112  __I union {
113  uint32_t U;
114  struct {
115  uint16_t L;
116  uint16_t H;
117  };
118 
119  } CAP[CONFIG_SCT_nRG];
120 
121  };
122 
123  uint32_t RESERVED3[32 - CONFIG_SCT_nRG];
124  union {
125  __IO uint16_t MATCH_L[CONFIG_SCT_nRG];
126  __I uint16_t CAP_L[CONFIG_SCT_nRG];
127  };
128 
129  uint16_t RESERVED4[32 - CONFIG_SCT_nRG];
130  union {
131  __IO uint16_t MATCH_H[CONFIG_SCT_nRG];
132  __I uint16_t CAP_H[CONFIG_SCT_nRG];
133  };
134 
135  uint16_t RESERVED5[32 - CONFIG_SCT_nRG];
136  union {
137  __IO union {
138  uint32_t U;
139  struct {
140  uint16_t L;
141  uint16_t H;
142  };
143 
144  } MATCHREL[CONFIG_SCT_nRG];
145 
146  __IO union {
147  uint32_t U;
148  struct {
149  uint16_t L;
150  uint16_t H;
151  };
152 
153  } CAPCTRL[CONFIG_SCT_nRG];
154 
155  };
156 
157  uint32_t RESERVED6[32 - CONFIG_SCT_nRG];
158  union {
159  __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG];
160  __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG];
161  };
162 
163  uint16_t RESERVED7[32 - CONFIG_SCT_nRG];
164  union {
165  __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG];
166  __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG];
167  };
168 
169  uint16_t RESERVED8[32 - CONFIG_SCT_nRG];
170  __IO struct {
171  uint32_t STATE;
172  uint32_t CTRL;
173  } EVENT[CONFIG_SCT_nEV];
174 
175  uint32_t RESERVED9[128 - 2 * CONFIG_SCT_nEV];
176  __IO struct {
177  uint32_t SET;
178  uint32_t CLR;
179  } OUT[CONFIG_SCT_nOU];
180 
181  uint32_t RESERVED10[191 - 2 * CONFIG_SCT_nOU];
182  __I uint32_t MODULECONTENT;
183 } IP_SCT_001_T;
184 
188 #define SCT_CONFIG_16BIT_COUNTER 0x00000000
189 #define SCT_CONFIG_32BIT_COUNTER 0x00000001
191 #define SCT_CONFIG_CLKMODE_BUSCLK (0x0 << 1)
192 #define SCT_CONFIG_CLKMODE_SCTCLK (0x1 << 1)
193 #define SCT_CONFIG_CLKMODE_INCLK (0x2 << 1)
194 #define SCT_CONFIG_CLKMODE_INEDGECLK (0x3 << 1)
196 #define SCT_CONFIG_NORELOADL_U (0x1 << 7)
197 #define SCT_CONFIG_NORELOADH (0x1 << 8)
199 /*
200  * @brief Macro defines for SCT control register
201  */
202 #define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0
203 #define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
204 
205 #define SCT_CTRL_STOP_L (1 << 1)
206 #define SCT_CTRL_HALT_L (1 << 2)
207 #define SCT_CTRL_CLRCTR_L (1 << 3)
208 #define SCT_CTRL_BIDIR_L(x) (((x) & 0x01) << 4)
209 #define SCT_CTRL_PRE_L(x) (((x) & 0xFF) << 5)
211 #define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0
212 #define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
213 #define SCT_CTRL_STOP_H (1 << 17)
214 #define SCT_CTRL_HALT_H (1 << 18)
215 #define SCT_CTRL_CLRCTR_H (1 << 19)
216 #define SCT_CTRL_BIDIR_H(x) (((x) & 0x01) << 20)
217 #define SCT_CTRL_PRE_H(x) (((x) & 0xFF) << 21)
219 /*
220  * @brief Macro defines for SCT Conflict resolution register
221  */
222 #define SCT_RES_NOCHANGE (0)
223 #define SCT_RES_SET_OUTPUT (1)
224 #define SCT_RES_CLEAR_OUTPUT (2)
225 #define SCT_RES_TOGGLE_OUTPUT (3)
226 
234 STATIC INLINE void IP_SCT_SetCount(IP_SCT_001_T *pSCT, uint32_t count)
235 {
236  pSCT->COUNT_U = count;
237 }
238 
246 STATIC INLINE void IP_SCT_SetCountL(IP_SCT_001_T *pSCT, uint16_t count)
247 {
248  pSCT->COUNT_L = count;
249 }
250 
258 STATIC INLINE void IP_SCT_SetCountH(IP_SCT_001_T *pSCT, uint16_t count)
259 {
260  pSCT->COUNT_H = count;
261 }
262 
271 STATIC INLINE void IP_SCT_SetMatchCount(IP_SCT_001_T *pSCT, uint32_t n, uint32_t count)
272 {
273  pSCT->MATCH[n].U = count;
274 }
275 
283 STATIC INLINE void IP_SCT_SetMatchReload(IP_SCT_001_T *pSCT, uint32_t n, uint32_t count)
284 {
285  pSCT->MATCHREL[n].U = count;
286 }
287 
294 STATIC INLINE void IP_SCT_EventIntEnable(IP_SCT_001_T *pSCT, uint32_t evt)
295 {
296  pSCT->EVEN |= evt;
297 }
298 
305 STATIC INLINE void IP_SCT_EventIntDisable(IP_SCT_001_T *pSCT, uint32_t evt)
306 {
307  pSCT->EVEN &= ~(evt);
308 }
309 
316 STATIC INLINE void IP_SCT_ClearEventFlag(IP_SCT_001_T *pSCT, uint32_t evt)
317 {
318  pSCT->EVFLAG |= evt;
319 }
320 
328 void IP_SCT_Config(IP_SCT_001_T *pSCT, uint32_t value);
329 
342 void IP_SCT_ControlSetClr(IP_SCT_001_T *pSCT, uint32_t value, FunctionalState ena);
343 
358 void IP_SCT_ConflictResolutionSet(IP_SCT_001_T *pSCT, uint8_t outnum, uint8_t value);
359 
367 void IP_SCT_EventFlagClear(IP_SCT_001_T *pSCT, uint8_t even_num);
368 
373 #ifdef __cplusplus
374 }
375 #endif
376 
377 #endif /* __SCT_001_H_ */