sdc_001.h File Reference

#include "sys_config.h"
#include "cmsis.h"

Go to the source code of this file.

Data Structures
struct	IP_SDC_001_T
	SD/MMC card Interface (SDC) register block structure. More...
struct	IP_SDC_001_RESP_T
	SDC Command Response structure. More...
struct	IP_SDC_001_DATA_TRANSFER_T
	SDC Data Transfer Setup structure. More...

Macros
#define	SDC_PWR_BITMASK   ((uint32_t) 0xC3)
	SDC Power Control Register bit definitions.
#define	SDC_PWR_CTRL_BITMASK   (((uint32_t) 0x03) << 0)
#define	SDC_PWR_CTRL(n)   (((uint32_t) (n & 0x03)) << 0)
#define	SDC_PWR_OPENDRAIN   (((uint32_t) 1) << 6)
#define	SDC_PWR_ROD   (((uint32_t) 1) << 7)
#define	SDC_CLOCK_BITMASK   ((uint32_t) 0xFFF)
	SDC Clock Control Register bit definitions.
#define	SDC_CLOCK_CLKDIV_BITMASK   (((uint32_t) 0xFF ) << 0)
#define	SDC_CLOCK_CLKDIV(n)   (((uint32_t) (n & 0x0FF)) << 0)
#define	SDC_COMMAND_BITMASK   ((uint32_t) 0x7FF)
	SDC Command Register bit definitions.
#define	SDC_COMMAND_INDEX_BITMASK   ((uint32_t) 0x3F)
#define	SDC_COMMAND_INDEX(n)   ((uint32_t) n & 0x3F)
#define	SDC_COMMAND_NO_RSP   (((uint32_t) 0 ) << 6)
#define	SDC_COMMAND_SHORT_RSP   (((uint32_t) 1 ) << 6)
#define	SDC_COMMAND_LONG_RSP   (((uint32_t) 3 ) << 6)
#define	SDC_COMMAND_RSP_BITMASK   (((uint32_t) 3 ) << 6)
#define	SDC_COMMAND_INTERRUPT   (((uint32_t) 1 ) << 8)
#define	SDC_COMMAND_PENDING   (((uint32_t) 1 ) << 9)
#define	SDC_COMMAND_ENABLE   (((uint32_t) 1 ) << 10)
#define	SDC_RESPCOMMAND_VAL(n)   ((uint32_t) n & 0x3F)
	SDC Command Response Register bit definitions.
#define	SDC_DATALENGTH_LEN(n)   ((uint32_t) n & 0xFFFF)
	SDC Data Length Register bit definitions.
#define	SDC_DATACTRL_BITMASK   ((uint32_t) 0xFF)
	SDC Data Control Register bit definitions.
#define	SDC_DATACTRL_ENABLE   (((uint32_t) 1 ) << 0)
#define	SDC_DATACTRL_DIR_FROMCARD   (((uint32_t) 1 ) << 1)
#define	SDC_DATACTRL_DIR_TOCARD   ((uint32_t) 0)
#define	SDC_DATACTRL_XFER_MODE_STREAM   (((uint32_t) 1 ) << 2)
#define	SDC_DATACTRL_XFER_MODE_BLOCK   ((uint32_t) 0)
#define	SDC_DATACTRL_DMA_ENABLE   (((uint32_t) 1 ) << 3)
#define	SDC_DATACTRL_BLOCKSIZE(n)   (((uint32_t) (n & 0x0F) ) << 4)
#define	SDC_DATACTRL_BLOCKSIZE_VAL(n)   (((uint32_t) 1) << n)
#define	SDC_DATACNT_VAL(n)   ((uint32_t) n & 0xFFFF)
	SDC Data Counter Register bit definitions.
#define	SDC_STATUS_CMDCRCFAIL   (((uint32_t) 1 ) << 0)
	SDC Status Register bit definitions.
#define	SDC_STATUS_DATACRCFAIL   (((uint32_t) 1 ) << 1)
#define	SDC_STATUS_CMDTIMEOUT   (((uint32_t) 1 ) << 2)
#define	SDC_STATUS_DATATIMEOUT   (((uint32_t) 1 ) << 3)
#define	SDC_STATUS_TXUNDERRUN   (((uint32_t) 1 ) << 4)
#define	SDC_STATUS_RXOVERRUN   (((uint32_t) 1 ) << 5)
#define	SDC_STATUS_CMDRESPEND   (((uint32_t) 1 ) << 6)
#define	SDC_STATUS_CMDSENT   (((uint32_t) 1 ) << 7)
#define	SDC_STATUS_DATAEND   (((uint32_t) 1 ) << 8)
#define	SDC_STATUS_STARTBITERR   (((uint32_t) 1 ) << 9)
#define	SDC_STATUS_DATABLOCKEND   (((uint32_t) 1 ) << 10)
#define	SDC_STATUS_CMDACTIVE   (((uint32_t) 1 ) << 11)
#define	SDC_STATUS_TXACTIVE   (((uint32_t) 1 ) << 12)
#define	SDC_STATUS_RXACTIVE   (((uint32_t) 1 ) << 13)
#define	SDC_STATUS_TXFIFOHALFEMPTY   (((uint32_t) 1 ) << 14)
#define	SDC_STATUS_RXFIFOHALFFULL   (((uint32_t) 1 ) << 15)
#define	SDC_STATUS_TXFIFOFULL   (((uint32_t) 1 ) << 16)
#define	SDC_STATUS_RXFIFOFULL   (((uint32_t) 1 ) << 17)
#define	SDC_STATUS_TXFIFOEMPTY   (((uint32_t) 1 ) << 18)
#define	SDC_STATUS_RXFIFOEMPTY   (((uint32_t) 1 ) << 19)
#define	SDC_STATUS_TXDATAAVLBL   (((uint32_t) 1 ) << 20)
#define	SDC_STATUS_RXDATAAVLBL   (((uint32_t) 1 ) << 21)
#define	SDC_STATUS_CMDERR   (SDC_STATUS_CMDCRCFAIL | SDC_STATUS_CMDTIMEOUT | SDC_STATUS_STARTBITERR)
#define	SDC_STATUS_DATAERR
#define	SDC_STATUS_FIFO
#define	SDC_STATUS_DATA   (SDC_STATUS_DATAEND )
#define	SDC_CLEAR_ALL   ((uint32_t) 0x7FF)
	SDC Clear Register bit definitions.
#define	SDC_CLEAR_CMDCRCFAIL   (((uint32_t) 1 ) << 0)
#define	SDC_CLEAR_DATACRCFAIL   (((uint32_t) 1 ) << 1)
#define	SDC_CLEAR_CMDTIMEOUT   (((uint32_t) 1 ) << 2)
#define	SDC_CLEAR_DATATIMEOUT   (((uint32_t) 1 ) << 3)
#define	SDC_CLEAR_TXUNDERRUN   (((uint32_t) 1 ) << 4)
#define	SDC_CLEAR_RXOVERRUN   (((uint32_t) 1 ) << 5)
#define	SDC_CLEAR_CMDRESPEND   (((uint32_t) 1 ) << 6)
#define	SDC_CLEAR_CMDSENT   (((uint32_t) 1 ) << 7)
#define	SDC_CLEAR_DATAEND   (((uint32_t) 1 ) << 8)
#define	SDC_CLEAR_STARTBITERR   (((uint32_t) 1 ) << 9)
#define	SDC_CLEAR_DATABLOCKEND   (((uint32_t) 1 ) << 10)
#define	SDC_MASK0_CMDCRCFAIL   (((uint32_t) 1 ) << 0)
	SDC Interrupt Mask Register bit definitions.
#define	SDC_MASK0_DATACRCFAIL   (((uint32_t) 1 ) << 1)
#define	SDC_MASK0_CMDTIMEOUT   (((uint32_t) 1 ) << 2)
#define	SDC_MASK0_DATATIMEOUT   (((uint32_t) 1 ) << 3)
#define	SDC_MASK0_TXUNDERRUN   (((uint32_t) 1 ) << 4)
#define	SDC_MASK0_RXOVERRUN   (((uint32_t) 1 ) << 5)
#define	SDC_MASK0_CMDRESPEND   (((uint32_t) 1 ) << 6)
#define	SDC_MASK0_CMDSENT   (((uint32_t) 1 ) << 7)
#define	SDC_MASK0_DATAEND   (((uint32_t) 1 ) << 8)
#define	SDC_MASK0_STARTBITERR   (((uint32_t) 1 ) << 9)
#define	SDC_MASK0_DATABLOCKEND   (((uint32_t) 1 ) << 10)
#define	SDC_MASK0_CMDACTIVE   (((uint32_t) 1 ) << 11)
#define	SDC_MASK0_TXACTIVE   (((uint32_t) 1 ) << 12)
#define	SDC_MASK0_RXACTIVE   (((uint32_t) 1 ) << 13)
#define	SDC_MASK0_TXFIFOHALFEMPTY   (((uint32_t) 1 ) << 14)
#define	SDC_MASK0_RXFIFOHALFFULL   (((uint32_t) 1 ) << 15)
#define	SDC_MASK0_TXFIFOFULL   (((uint32_t) 1 ) << 16)
#define	SDC_MASK0_RXFIFOFULL   (((uint32_t) 1 ) << 17)
#define	SDC_MASK0_TXFIFOEMPTY   (((uint32_t) 1 ) << 18)
#define	SDC_MASK0_RXFIFOEMPTY   (((uint32_t) 1 ) << 19)
#define	SDC_MASK0_TXDATAAVLBL   (((uint32_t) 1 ) << 20)
#define	SDC_MASK0_RXDATAAVLBL   (((uint32_t) 1 ) << 21)
#define	SDC_MASK0_CMDERR   (SDC_MASK0_CMDCRCFAIL | SDC_MASK0_CMDTIMEOUT | SDC_MASK0_STARTBITERR)
#define	SDC_MASK0_TXDATAERR
#define	SDC_MASK0_RXDATAERR
#define	SDC_MASK0_TXFIFO   (SDC_MASK0_TXFIFOHALFEMPTY | SDC_MASK0_DATABLOCKEND )
#define	SDC_MASK0_RXFIFO   (SDC_MASK0_RXFIFOHALFFULL | SDC_MASK0_DATABLOCKEND )
#define	SDC_MASK0_DATA   (SDC_MASK0_DATAEND | SDC_MASK0_DATABLOCKEND )
#define	SDC_FIFOCNT_VAL(n)   ((uint32_t) n & 0x7FFF)
	SDC FIFO Counter Register bit definitions.
#define	SDC_CARDSTATUS_BYTENUM   ((uint32_t) 4)

Enumerations
enum	IP_SDC_001_PWR_CTRL_T { SDC_POWER_OFF = 0, SDC_POWER_UP = 2, SDC_POWER_ON = 3 }
	SDC Power Control Options. More...
enum	IP_SDC_001_CLOCK_CTRL_T { SDC_CLOCK_ENABLE = 8, SDC_CLOCK_POWER_SAVE = 9, SDC_CLOCK_DIVIDER_BYPASS = 10, SDC_CLOCK_WIDEBUS_MODE = 11 }
	SDC Clock Control Options. More...
enum	IP_SDC_001_RESPONSE_T { SDC_NO_RESPONSE = SDC_COMMAND_NO_RSP, SDC_SHORT_RESPONSE = SDC_COMMAND_SHORT_RSP, SDC_LONG_RESPONSE = SDC_COMMAND_LONG_RSP }
	SDC Response type. More...
enum	IP_SDC_001_TRANSFER_DIR_T { SDC_TRANSFER_DIR_FROMCARD = SDC_DATACTRL_DIR_FROMCARD, SDC_TRANSFER_DIR_TOCARD = SDC_DATACTRL_DIR_TOCARD }
	SDC Data Transfer Direction definitions. More...
enum	IP_SDC_001_TRANSFER_MODE_T { SDC_TRANSFER_MODE_STREAM = SDC_DATACTRL_XFER_MODE_STREAM, SDC_TRANSFER_MODE_BLOCK = SDC_DATACTRL_XFER_MODE_BLOCK }
	SDC Data Transfer Mode definitions. More...
enum	IP_SDC_001_BLOCK_SIZE_T {   SDC_BLOCK_SIZE_1 = 0, SDC_BLOCK_SIZE_2, SDC_BLOCK_SIZE_4, SDC_BLOCK_SIZE_8,   SDC_BLOCK_SIZE_16, SDC_BLOCK_SIZE_32, SDC_BLOCK_SIZE_64, SDC_BLOCK_SIZE_128,   SDC_BLOCK_SIZE_256, SDC_BLOCK_SIZE_512, SDC_BLOCK_SIZE_1024, SDC_BLOCK_SIZE_2048 }
	SDC Data Block size definitions (in bytes) More...

Functions
void	IP_SDC_PowerControl (IP_SDC_001_T *pSDC, IP_SDC_001_PWR_CTRL_T pwrMode, uint32_t flag)
	Set the power state of SDC peripheral.
void	IP_SDC_SetClockDiv (IP_SDC_001_T *pSDC, uint8_t div)
	Set clock divider value for SDC peripheral.
void	IP_SDC_ClockControl (IP_SDC_001_T *pSDC, IP_SDC_001_CLOCK_CTRL_T ctrlType, FunctionalState NewState)
	Set or Reset clock control of SDC peripheral.
void	IP_SDC_SetCommand (IP_SDC_001_T *pSDC, uint32_t Cmd, uint32_t Arg)
	Set SDC Command Information.
void	IP_SDC_ResetCommand (IP_SDC_001_T *pSDC)
	Reset SDC Command Information.
void	IP_SDC_GetResp (IP_SDC_001_T *pSDC, IP_SDC_001_RESP_T *pResp)
	Get SDC Response.
STATIC INLINE void	IP_SDC_SetDataTimer (IP_SDC_001_T *pSDC, uint32_t timeout)
	Set SDC Data Timeout Period.
void	IP_SDC_SetDataTransfer (IP_SDC_001_T *pSDC, IP_SDC_001_DATA_TRANSFER_T *pTransfer)
	Set SDC Data Transfer Information.
void	IP_SDC_WriteFIFO (IP_SDC_001_T *pSDC, uint32_t *pSrc, bool bFirstHalf)
	Write Data to FIFO.
void	IP_SDC_ReadFIFO (IP_SDC_001_T *pSDC, uint32_t *pDst, bool bFirstHalf)
	Write Data to FIFO.
STATIC INLINE uint32_t	IP_SDC_GetStatus (IP_SDC_001_T *pSDC)
	Get status of SDC Peripheral.
STATIC INLINE void	IP_SDC_ClearStatus (IP_SDC_001_T *pSDC, uint32_t flag)
	Clear status of SDC Peripheral.
STATIC INLINE void	IP_SDC_SetIntMask (IP_SDC_001_T *pSDC, uint32_t mask)
	Set interrupt mask for SDC Peripheral.
void	IP_SDC_Init (IP_SDC_001_T *pSDC)
	Initialize the SDC card controller.
STATIC INLINE void	IP_SDC_DeInit (IP_SDC_001_T *pSDC)
	Deinitialise the SDC peripheral.