sdc_001.h

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/*
 * @brief SD Card Interface Registers and control functions
 *
 * @note
 * Copyright(C) NXP Semiconductors, 2012
 * All rights reserved.
 *
 * @par
 * Software that is described herein is for illustrative purposes only
 * which provides customers with programming information regarding the
 * LPC products.  This software is supplied "AS IS" without any warranties of
 * any kind, and NXP Semiconductors and its licensor disclaim any and
 * all warranties, express or implied, including all implied warranties of
 * merchantability, fitness for a particular purpose and non-infringement of
 * intellectual property rights.  NXP Semiconductors assumes no responsibility
 * or liability for the use of the software, conveys no license or rights under any
 * patent, copyright, mask work right, or any other intellectual property rights in
 * or to any products. NXP Semiconductors reserves the right to make changes
 * in the software without notification. NXP Semiconductors also makes no
 * representation or warranty that such application will be suitable for the
 * specified use without further testing or modification.
 *
 * @par
 * Permission to use, copy, modify, and distribute this software and its
 * documentation is hereby granted, under NXP Semiconductors' and its
 * licensor's relevant copyrights in the software, without fee, provided that it
 * is used in conjunction with NXP Semiconductors microcontrollers.  This
 * copyright, permission, and disclaimer notice must appear in all copies of
 * this code.
 */

#ifndef __SDC_001_H_
#define __SDC_001_H_

#include "sys_config.h"
#include "cmsis.h"

#ifdef __cplusplus
extern "C" {
#endif

typedef struct {
 __IO uint32_t POWER;        
 __IO uint32_t CLOCK;        
 __IO uint32_t ARGUMENT;     
 __IO uint32_t COMMAND;      
 __I  uint32_t RESPCMD;      
 __I  uint32_t RESPONSE[4];  
 __IO uint32_t DATATIMER;    
 __IO uint32_t DATALENGTH;   
 __IO uint32_t DATACTRL;     
 __I  uint32_t DATACNT;      
 __I  uint32_t STATUS;       
 __O  uint32_t CLEAR;        
 __IO uint32_t MASK0;        
 uint32_t RESERVED0[2];
 __I  uint32_t FIFOCNT;      
 uint32_t RESERVED1[13];
 __IO uint32_t FIFO[16];     
} IP_SDC_001_T;

#define SDC_PWR_BITMASK         ((uint32_t) 0xC3)

#define SDC_PWR_CTRL_BITMASK    (((uint32_t) 0x03) << 0)

#define SDC_PWR_CTRL(n)         (((uint32_t) (n & 0x03)) << 0)

#define SDC_PWR_OPENDRAIN       (((uint32_t) 1) << 6)

#define SDC_PWR_ROD             (((uint32_t) 1) << 7)

#define SDC_CLOCK_BITMASK       ((uint32_t) 0xFFF)

#define SDC_CLOCK_CLKDIV_BITMASK    (((uint32_t) 0xFF ) << 0)

#define SDC_CLOCK_CLKDIV(n)     (((uint32_t) (n & 0x0FF)) << 0)

#define SDC_COMMAND_BITMASK     ((uint32_t) 0x7FF)

#define SDC_COMMAND_INDEX_BITMASK   ((uint32_t) 0x3F)

#define SDC_COMMAND_INDEX(n)        ((uint32_t) n & 0x3F)

#define SDC_COMMAND_NO_RSP          (((uint32_t) 0 ) << 6)

#define SDC_COMMAND_SHORT_RSP       (((uint32_t) 1 ) << 6)

#define SDC_COMMAND_LONG_RSP        (((uint32_t) 3 ) << 6)

#define SDC_COMMAND_RSP_BITMASK     (((uint32_t) 3 ) << 6)

#define SDC_COMMAND_INTERRUPT       (((uint32_t) 1 ) << 8)

#define SDC_COMMAND_PENDING     (((uint32_t) 1 ) << 9)

#define SDC_COMMAND_ENABLE          (((uint32_t) 1 ) << 10)

#define SDC_RESPCOMMAND_VAL(n)      ((uint32_t) n & 0x3F)

#define SDC_DATALENGTH_LEN(n)       ((uint32_t) n & 0xFFFF)

#define SDC_DATACTRL_BITMASK        ((uint32_t) 0xFF)

#define SDC_DATACTRL_ENABLE             (((uint32_t) 1 ) << 0)

#define SDC_DATACTRL_DIR_FROMCARD       (((uint32_t) 1 ) << 1)

#define SDC_DATACTRL_DIR_TOCARD         ((uint32_t) 0)

#define SDC_DATACTRL_XFER_MODE_STREAM   (((uint32_t) 1 ) << 2)

#define SDC_DATACTRL_XFER_MODE_BLOCK    ((uint32_t) 0)

#define SDC_DATACTRL_DMA_ENABLE         (((uint32_t) 1 ) << 3)

#define SDC_DATACTRL_BLOCKSIZE(n)       (((uint32_t) (n & 0x0F) ) << 4)

#define SDC_DATACTRL_BLOCKSIZE_VAL(n)   (((uint32_t) 1) << n)

#define SDC_DATACNT_VAL(n)          ((uint32_t) n & 0xFFFF)

#define SDC_STATUS_CMDCRCFAIL     (((uint32_t) 1 ) << 0)

#define SDC_STATUS_DATACRCFAIL     (((uint32_t) 1 ) << 1)

#define SDC_STATUS_CMDTIMEOUT     (((uint32_t) 1 ) << 2)

#define SDC_STATUS_DATATIMEOUT     (((uint32_t) 1 ) << 3)

#define SDC_STATUS_TXUNDERRUN     (((uint32_t) 1 ) << 4)

#define SDC_STATUS_RXOVERRUN     (((uint32_t) 1 ) << 5)

#define SDC_STATUS_CMDRESPEND     (((uint32_t) 1 ) << 6)

#define SDC_STATUS_CMDSENT     (((uint32_t) 1 ) << 7)

#define SDC_STATUS_DATAEND     (((uint32_t) 1 ) << 8)

#define SDC_STATUS_STARTBITERR     (((uint32_t) 1 ) << 9)

#define SDC_STATUS_DATABLOCKEND     (((uint32_t) 1 ) << 10)

#define SDC_STATUS_CMDACTIVE     (((uint32_t) 1 ) << 11)

#define SDC_STATUS_TXACTIVE     (((uint32_t) 1 ) << 12)

#define SDC_STATUS_RXACTIVE     (((uint32_t) 1 ) << 13)

#define SDC_STATUS_TXFIFOHALFEMPTY     (((uint32_t) 1 ) << 14)

#define SDC_STATUS_RXFIFOHALFFULL     (((uint32_t) 1 ) << 15)

#define SDC_STATUS_TXFIFOFULL     (((uint32_t) 1 ) << 16)

#define SDC_STATUS_RXFIFOFULL     (((uint32_t) 1 ) << 17)

#define SDC_STATUS_TXFIFOEMPTY     (((uint32_t) 1 ) << 18)

#define SDC_STATUS_RXFIFOEMPTY     (((uint32_t) 1 ) << 19)

#define SDC_STATUS_TXDATAAVLBL     (((uint32_t) 1 ) << 20)

#define SDC_STATUS_RXDATAAVLBL     (((uint32_t) 1 ) << 21)

#define SDC_STATUS_CMDERR    (SDC_STATUS_CMDCRCFAIL | SDC_STATUS_CMDTIMEOUT | SDC_STATUS_STARTBITERR)

#define SDC_STATUS_DATAERR    (SDC_STATUS_DATACRCFAIL | SDC_STATUS_DATATIMEOUT | SDC_STATUS_TXUNDERRUN \
          | SDC_STATUS_RXOVERRUN | SDC_STATUS_STARTBITERR)

#define SDC_STATUS_FIFO    (SDC_STATUS_TXFIFOHALFEMPTY | SDC_STATUS_RXFIFOHALFFULL \
       | SDC_STATUS_TXFIFOFULL  | SDC_STATUS_RXFIFOFULL \
       | SDC_STATUS_TXFIFOEMPTY | SDC_STATUS_RXFIFOEMPTY \
       | SDC_STATUS_DATABLOCKEND)

#define SDC_STATUS_DATA    (SDC_STATUS_DATAEND )

#define SDC_CLEAR_ALL       ((uint32_t) 0x7FF)

#define SDC_CLEAR_CMDCRCFAIL     (((uint32_t) 1 ) << 0)

#define SDC_CLEAR_DATACRCFAIL     (((uint32_t) 1 ) << 1)

#define SDC_CLEAR_CMDTIMEOUT     (((uint32_t) 1 ) << 2)

#define SDC_CLEAR_DATATIMEOUT     (((uint32_t) 1 ) << 3)

#define SDC_CLEAR_TXUNDERRUN     (((uint32_t) 1 ) << 4)

#define SDC_CLEAR_RXOVERRUN     (((uint32_t) 1 ) << 5)

#define SDC_CLEAR_CMDRESPEND     (((uint32_t) 1 ) << 6)

#define SDC_CLEAR_CMDSENT     (((uint32_t) 1 ) << 7)

#define SDC_CLEAR_DATAEND     (((uint32_t) 1 ) << 8)

#define SDC_CLEAR_STARTBITERR     (((uint32_t) 1 ) << 9)

#define SDC_CLEAR_DATABLOCKEND     (((uint32_t) 1 ) << 10)

#define SDC_MASK0_CMDCRCFAIL     (((uint32_t) 1 ) << 0)

#define SDC_MASK0_DATACRCFAIL     (((uint32_t) 1 ) << 1)

#define SDC_MASK0_CMDTIMEOUT     (((uint32_t) 1 ) << 2)

#define SDC_MASK0_DATATIMEOUT     (((uint32_t) 1 ) << 3)

#define SDC_MASK0_TXUNDERRUN     (((uint32_t) 1 ) << 4)

#define SDC_MASK0_RXOVERRUN     (((uint32_t) 1 ) << 5)

#define SDC_MASK0_CMDRESPEND     (((uint32_t) 1 ) << 6)

#define SDC_MASK0_CMDSENT     (((uint32_t) 1 ) << 7)

#define SDC_MASK0_DATAEND     (((uint32_t) 1 ) << 8)

#define SDC_MASK0_STARTBITERR     (((uint32_t) 1 ) << 9)

#define SDC_MASK0_DATABLOCKEND     (((uint32_t) 1 ) << 10)

#define SDC_MASK0_CMDACTIVE     (((uint32_t) 1 ) << 11)

#define SDC_MASK0_TXACTIVE     (((uint32_t) 1 ) << 12)

#define SDC_MASK0_RXACTIVE     (((uint32_t) 1 ) << 13)

#define SDC_MASK0_TXFIFOHALFEMPTY     (((uint32_t) 1 ) << 14)

#define SDC_MASK0_RXFIFOHALFFULL     (((uint32_t) 1 ) << 15)

#define SDC_MASK0_TXFIFOFULL     (((uint32_t) 1 ) << 16)

#define SDC_MASK0_RXFIFOFULL     (((uint32_t) 1 ) << 17)

#define SDC_MASK0_TXFIFOEMPTY     (((uint32_t) 1 ) << 18)

#define SDC_MASK0_RXFIFOEMPTY     (((uint32_t) 1 ) << 19)

#define SDC_MASK0_TXDATAAVLBL     (((uint32_t) 1 ) << 20)

#define SDC_MASK0_RXDATAAVLBL     (((uint32_t) 1 ) << 21)

#define SDC_MASK0_CMDERR    (SDC_MASK0_CMDCRCFAIL | SDC_MASK0_CMDTIMEOUT | SDC_MASK0_STARTBITERR)

#define SDC_MASK0_TXDATAERR    (SDC_MASK0_DATACRCFAIL | SDC_MASK0_DATATIMEOUT | SDC_MASK0_TXUNDERRUN | \
        SDC_MASK0_STARTBITERR)

#define SDC_MASK0_RXDATAERR    (SDC_MASK0_DATACRCFAIL | SDC_MASK0_DATATIMEOUT | SDC_MASK0_RXOVERRUN | \
        SDC_MASK0_STARTBITERR)

#define SDC_MASK0_TXFIFO    (SDC_MASK0_TXFIFOHALFEMPTY | SDC_MASK0_DATABLOCKEND )

#define SDC_MASK0_RXFIFO    (SDC_MASK0_RXFIFOHALFFULL  | SDC_MASK0_DATABLOCKEND )

#define SDC_MASK0_DATA    (SDC_MASK0_DATAEND | SDC_MASK0_DATABLOCKEND )

#define SDC_FIFOCNT_VAL(n)          ((uint32_t) n & 0x7FFF)

/* The number of bytes used to store card status*/
#define SDC_CARDSTATUS_BYTENUM              ((uint32_t) 4)

typedef enum IP_SDC_001_PWR_CTRL {
 SDC_POWER_OFF = 0,  
 SDC_POWER_UP = 2,  
 SDC_POWER_ON = 3,  
} IP_SDC_001_PWR_CTRL_T;

typedef enum IP_SDC_001_CLOCK_CTRL {
 SDC_CLOCK_ENABLE = 8,     
 SDC_CLOCK_POWER_SAVE = 9,    
 SDC_CLOCK_DIVIDER_BYPASS = 10, 
 SDC_CLOCK_WIDEBUS_MODE = 11,   
} IP_SDC_001_CLOCK_CTRL_T;

typedef enum IP_SDC_001_RESPONSE {
 SDC_NO_RESPONSE = SDC_COMMAND_NO_RSP,       
 SDC_SHORT_RESPONSE = SDC_COMMAND_SHORT_RSP, 
 SDC_LONG_RESPONSE = SDC_COMMAND_LONG_RSP,   
} IP_SDC_001_RESPONSE_T;

typedef enum IP_SDC_001_TRANSFER_DIR {
 SDC_TRANSFER_DIR_FROMCARD = SDC_DATACTRL_DIR_FROMCARD, 
 SDC_TRANSFER_DIR_TOCARD = SDC_DATACTRL_DIR_TOCARD,     
} IP_SDC_001_TRANSFER_DIR_T;

typedef enum IP_SDC_001_TRANSFER_MODE {
 SDC_TRANSFER_MODE_STREAM = SDC_DATACTRL_XFER_MODE_STREAM, 
 SDC_TRANSFER_MODE_BLOCK = SDC_DATACTRL_XFER_MODE_BLOCK,   
} IP_SDC_001_TRANSFER_MODE_T;

typedef enum IP_SDC_001_BLOCK_SIZE {
 SDC_BLOCK_SIZE_1 = 0,     
 SDC_BLOCK_SIZE_2,         
 SDC_BLOCK_SIZE_4,         
 SDC_BLOCK_SIZE_8,         
 SDC_BLOCK_SIZE_16,        
 SDC_BLOCK_SIZE_32,        
 SDC_BLOCK_SIZE_64,        
 SDC_BLOCK_SIZE_128,       
 SDC_BLOCK_SIZE_256,       
 SDC_BLOCK_SIZE_512,       
 SDC_BLOCK_SIZE_1024,      
 SDC_BLOCK_SIZE_2048,      
} IP_SDC_001_BLOCK_SIZE_T;

typedef struct {
 uint8_t CmdIndex;               
 uint32_t Data[SDC_CARDSTATUS_BYTENUM]; /* Card Status which can be stored in 1 or 4 bytes */
} IP_SDC_001_RESP_T;

typedef struct {
 uint16_t BlockNum;      
 IP_SDC_001_BLOCK_SIZE_T BlockSize;  
 IP_SDC_001_TRANSFER_DIR_T Dir;   
 IP_SDC_001_TRANSFER_MODE_T  Mode;  
 bool     DMAUsed;      
 uint32_t Timeout;      
} IP_SDC_001_DATA_TRANSFER_T;

void IP_SDC_PowerControl(IP_SDC_001_T *pSDC, IP_SDC_001_PWR_CTRL_T pwrMode, uint32_t flag);

void IP_SDC_SetClockDiv(IP_SDC_001_T *pSDC, uint8_t div);

void IP_SDC_ClockControl(IP_SDC_001_T *pSDC, IP_SDC_001_CLOCK_CTRL_T ctrlType,
       FunctionalState NewState);

void IP_SDC_SetCommand(IP_SDC_001_T *pSDC, uint32_t Cmd, uint32_t Arg);

void IP_SDC_ResetCommand(IP_SDC_001_T *pSDC);

void IP_SDC_GetResp(IP_SDC_001_T *pSDC, IP_SDC_001_RESP_T *pResp);

STATIC INLINE void IP_SDC_SetDataTimer(IP_SDC_001_T *pSDC, uint32_t timeout)
{
 pSDC->DATATIMER = timeout;
}

void IP_SDC_SetDataTransfer(IP_SDC_001_T *pSDC, IP_SDC_001_DATA_TRANSFER_T *pTransfer);

void IP_SDC_WriteFIFO(IP_SDC_001_T *pSDC, uint32_t *pSrc, bool bFirstHalf);

void IP_SDC_ReadFIFO(IP_SDC_001_T *pSDC, uint32_t *pDst, bool bFirstHalf);

STATIC INLINE uint32_t IP_SDC_GetStatus(IP_SDC_001_T *pSDC)
{
 return pSDC->STATUS;
}

STATIC INLINE void IP_SDC_ClearStatus(IP_SDC_001_T *pSDC, uint32_t flag)
{
 pSDC->CLEAR = flag;
}

STATIC INLINE void IP_SDC_SetIntMask(IP_SDC_001_T *pSDC, uint32_t mask)
{
 pSDC->MASK0 = mask;
}

void IP_SDC_Init(IP_SDC_001_T *pSDC);

STATIC INLINE void IP_SDC_DeInit(IP_SDC_001_T *pSDC)
{
 IP_SDC_PowerControl(pSDC, SDC_POWER_OFF, 0);
}

#ifdef __cplusplus
}
#endif

#endif /* __SDC_001_H_ */