ssp_001.h

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/*
 * @brief SSP Registers and control functions
 *
 * @note
 * Copyright(C) NXP Semiconductors, 2012
 * All rights reserved.
 *
 * @par
 * Software that is described herein is for illustrative purposes only
 * which provides customers with programming information regarding the
 * LPC products.  This software is supplied "AS IS" without any warranties of
 * any kind, and NXP Semiconductors and its licensor disclaim any and
 * all warranties, express or implied, including all implied warranties of
 * merchantability, fitness for a particular purpose and non-infringement of
 * intellectual property rights.  NXP Semiconductors assumes no responsibility
 * or liability for the use of the software, conveys no license or rights under any
 * patent, copyright, mask work right, or any other intellectual property rights in
 * or to any products. NXP Semiconductors reserves the right to make changes
 * in the software without notification. NXP Semiconductors also makes no
 * representation or warranty that such application will be suitable for the
 * specified use without further testing or modification.
 *
 * @par
 * Permission to use, copy, modify, and distribute this software and its
 * documentation is hereby granted, under NXP Semiconductors' and its
 * licensor's relevant copyrights in the software, without fee, provided that it
 * is used in conjunction with NXP Semiconductors microcontrollers.  This
 * copyright, permission, and disclaimer notice must appear in all copies of
 * this code.
 */

#ifndef __SSP_001_H_
#define __SSP_001_H_

#include "sys_config.h"
#include "cmsis.h"

#ifdef __cplusplus
extern "C" {
#endif

typedef struct {   
 __IO uint32_t CR0;  
 __IO uint32_t CR1;  
 __IO uint32_t DR;  
 __I  uint32_t SR;  
 __IO uint32_t CPSR;  
 __IO uint32_t IMSC;  
 __I  uint32_t RIS;  
 __I  uint32_t MIS;  
 __O  uint32_t ICR;  
#if !defined(CHIP_LPC110X) && !defined(CHIP_LPC11XXLV) && !defined(CHIP_LPC11AXX) && \
 !defined(CHIP_LPC11CXX) && !defined(CHIP_LPC11EXX) && !defined(CHIP_LPC11UXX)
 __IO uint32_t DMACR; 
#endif
} IP_SSP_001_T;

#define SSP_CR0_DSS(n)          ((uint32_t) ((n) & 0xF))

#define SSP_CR0_FRF_SPI         ((uint32_t) (0 << 4))

#define SSP_CR0_FRF_TI          ((uint32_t) (1 << 4))

#define SSP_CR0_FRF_MICROWIRE   ((uint32_t) (2 << 4))

#define SSP_CR0_CPOL_LO     ((uint32_t) (0))
#define SSP_CR0_CPOL_HI     ((uint32_t) (1 << 6))

#define SSP_CR0_CPHA_FIRST  ((uint32_t) (0))
#define SSP_CR0_CPHA_SECOND ((uint32_t) (1 << 7))

#define SSP_CR0_SCR(n)      ((uint32_t) ((n & 0xFF) << 8))

#define SSP_CR0_BITMASK     ((uint32_t) (0xFFFF))

#define SSP_CR0_BITMASK     ((uint32_t) (0xFFFF))

#define SSP_CR0_SCR(n)      ((uint32_t) ((n & 0xFF) << 8))

#define SSP_CR1_LBM_EN      ((uint32_t) (1 << 0))

#define SSP_CR1_SSP_EN      ((uint32_t) (1 << 1))

#define SSP_CR1_SLAVE_EN    ((uint32_t) (1 << 2))
#define SSP_CR1_MASTER_EN   ((uint32_t) (0))

#define SSP_CR1_SO_DISABLE  ((uint32_t) (1 << 3))

#define SSP_CR1_BITMASK     ((uint32_t) (0x0F))

#define SSP_CPSR_BITMASK    ((uint32_t) (0xFF))

#define SSP_DR_BITMASK(n)   ((n) & 0xFFFF)

#define SSP_SR_BITMASK  ((uint32_t) (0x1F))

#define SSP_ICR_BITMASK ((uint32_t) (0x03))

typedef enum IP_SSP_STATUS {
 SSP_STAT_TFE = ((uint32_t)(1 << 0)),
 SSP_STAT_TNF = ((uint32_t)(1 << 1)),
 SSP_STAT_RNE = ((uint32_t)(1 << 2)),
 SSP_STAT_RFF = ((uint32_t)(1 << 3)),
 SSP_STAT_BSY = ((uint32_t)(1 << 4)),
} IP_SSP_STATUS_T;

typedef enum IP_SSP_INTMASK {
 SSP_RORIM = ((uint32_t)(1 << 0)), 
 SSP_RTIM = ((uint32_t)(1 << 1)),
 SSP_RXIM = ((uint32_t)(1 << 2)),
 SSP_TXIM = ((uint32_t)(1 << 3)),
 SSP_INT_MASK_BITMASK = ((uint32_t)(0xF)),
} IP_SSP_INTMASK_T;

typedef enum IP_SSP_MASKINTSTATUS {
 SSP_RORMIS = ((uint32_t)(1 << 0)), 
 SSP_RTMIS = ((uint32_t)(1 << 1)), 
 SSP_RXMIS = ((uint32_t)(1 << 2)), 
 SSP_TXMIS = ((uint32_t)(1 << 3)), 
 SSP_MASK_INT_STAT_BITMASK = ((uint32_t)(0xF)),
} IP_SSP_MASKINTSTATUS_T;

typedef enum IP_SSP_RAWINTSTATUS {
 SSP_RORRIS = ((uint32_t)(1 << 0)), 
 SSP_RTRIS = ((uint32_t)(1 << 1)), 
 SSP_RXRIS = ((uint32_t)(1 << 2)), 
 SSP_TXRIS = ((uint32_t)(1 << 3)), 
 SSP_RAW_INT_STAT_BITMASK = ((uint32_t)(0xF)),
} IP_SSP_RAWINTSTATUS_T;

typedef enum IP_SSP_INTCLEAR {
 SSP_RORIC = 0x0,
 SSP_RTIC = 0x1,
 SSP_INT_CLEAR_BITMASK = 0x3,
} IP_SSP_INTCLEAR_T;

typedef enum IP_SSP_DMA {
 SSP_DMA_RX = (1u), 
 SSP_DMA_TX = (1u << 1), 
 SSP_DMA_BITMASK = ((uint32_t)(0x3)),
} IP_SSP_DMA_T;

STATIC INLINE void IP_SSP_DeInit(IP_SSP_001_T *pSSP)
{
 pSSP->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;
}

STATIC INLINE void IP_SSP_Enable(IP_SSP_001_T *pSSP)
{
 pSSP->CR1 |= SSP_CR1_SSP_EN;
}

STATIC INLINE void IP_SSP_Disable(IP_SSP_001_T *pSSP)
{
 pSSP->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;
}

STATIC INLINE void IP_SSP_EnableLoopBack(IP_SSP_001_T *pSSP)
{
 pSSP->CR1 |= SSP_CR1_LBM_EN;
}

STATIC INLINE void IP_SSP_DisableLoopBack(IP_SSP_001_T *pSSP)
{
 pSSP->CR1 &= (~SSP_CR1_LBM_EN) & SSP_CR1_BITMASK;
}

STATIC INLINE FlagStatus IP_SSP_GetStatus(IP_SSP_001_T *pSSP, IP_SSP_STATUS_T Stat)
{
 return (pSSP->SR & Stat) ? SET : RESET;
}

STATIC INLINE uint32_t IP_SSP_GetIntStatus(IP_SSP_001_T *pSSP)
{
 return pSSP->MIS;
}

STATIC INLINE IntStatus IP_SSP_GetRawIntStatus(IP_SSP_001_T *pSSP, IP_SSP_RAWINTSTATUS_T RawInt)
{
 return (pSSP->RIS & RawInt) ? SET : RESET;
}

STATIC INLINE uint8_t IP_SSP_GetDataSize(IP_SSP_001_T *pSSP)
{
 return SSP_CR0_DSS(pSSP->CR0);
}

STATIC INLINE void IP_SSP_ClearIntPending(IP_SSP_001_T *pSSP, IP_SSP_INTCLEAR_T IntClear)
{
 pSSP->ICR = IntClear;
}

STATIC INLINE void IP_SSP_Int_Enable(IP_SSP_001_T *pSSP, IP_SSP_INTMASK_T IntType)
{
 pSSP->IMSC |= IntType;
}

STATIC INLINE void IP_SSP_Int_Disable(IP_SSP_001_T *pSSP, IP_SSP_INTMASK_T IntType)
{
 pSSP->IMSC &= (~IntType);
}

STATIC INLINE uint16_t IP_SSP_ReceiveFrame(IP_SSP_001_T *pSSP)
{
 return (uint16_t) (SSP_DR_BITMASK(pSSP->DR));
}

STATIC INLINE void IP_SSP_SendFrame(IP_SSP_001_T *pSSP, uint16_t tx_data)
{
 pSSP->DR = SSP_DR_BITMASK(tx_data);
}

void IP_SSP_Set_ClockRate(IP_SSP_001_T *pSSP, uint32_t clk_rate, uint32_t prescale);

STATIC INLINE void IP_SSP_SetFormat(IP_SSP_001_T *pSSP, uint32_t bits, uint32_t frameFormat, uint32_t clockMode)
{
 pSSP->CR0 = (pSSP->CR0 & ~0xFF) | bits | frameFormat | clockMode;
}

STATIC INLINE void IP_SSP_Set_Mode(IP_SSP_001_T *pSSP, uint32_t mode)
{
 pSSP->CR1 = (pSSP->CR1 & ~(1 << 2)) | mode;
}

#if !defined(CHIP_LPC110X) && !defined(CHIP_LPC11XXLV) && !defined(CHIP_LPC11AXX) && \
 !defined(CHIP_LPC11CXX) && !defined(CHIP_LPC11EXX) && !defined(CHIP_LPC11UXX)

STATIC INLINE void IP_SSP_DMA_Enable(IP_SSP_001_T *pSSP, IP_SSP_DMA_T flag)
{
 pSSP->DMACR |= flag;
}

STATIC INLINE void IP_SSP_DMA_Disable(IP_SSP_001_T *pSSP, IP_SSP_DMA_T flag)
{
 pSSP->DMACR &= ~flag;
}

#endif

#ifdef __cplusplus
}
#endif

#endif /* __SSP_001_H_ */