IP_SSP_001_T Struct Reference

Detailed Description

SSP register block structure.

Definition at line 50 of file ssp_001.h.

#include "ssp_001.h"

Data Fields
__IO uint32_t	CR0
__IO uint32_t	CR1
__IO uint32_t	DR
__I uint32_t	SR
__IO uint32_t	CPSR
__IO uint32_t	IMSC
__I uint32_t	RIS
__I uint32_t	MIS
__O uint32_t	ICR
__IO uint32_t	DMACR

Field Documentation

__IO uint32_t CPSR

Clock Prescale Register

Definition at line 55 of file ssp_001.h.

__IO uint32_t CR0

< SSPn Structure Control Register 0. Selects the serial clock rate, bus type, and data size.

Definition at line 51 of file ssp_001.h.

__IO uint32_t CR1

Control Register 1. Selects master/slave and other modes.

Definition at line 52 of file ssp_001.h.

__IO uint32_t DMACR

SSPn DMA control register

Definition at line 62 of file ssp_001.h.

__IO uint32_t DR

Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO.

Definition at line 53 of file ssp_001.h.

__O uint32_t ICR

SSPICR Interrupt Clear Register

Definition at line 59 of file ssp_001.h.

__IO uint32_t IMSC

Interrupt Mask Set and Clear Register

Definition at line 56 of file ssp_001.h.

__I uint32_t MIS

Masked Interrupt Status Register

Definition at line 58 of file ssp_001.h.

__I uint32_t RIS

Raw Interrupt Status Register

Definition at line 57 of file ssp_001.h.

__I uint32_t SR

Status Register

Definition at line 54 of file ssp_001.h.

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The documentation for this struct was generated from the following file:

• C:/nxp/v1.03/lpcopen_v1.03/lpcopen/software/lpc_core/lpc_ip/ssp_001.h