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LPCOpen Platform
v1.03
LPCOpen Platform for NXP LPC Microcontrollers
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LPCOpen Platform
v1.03
LPCOpen Platform for NXP LPC Microcontrollers
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USART register block structure.
Definition at line 50 of file usart_001.h.
#include "usart_001.h"
Data Fields | |
| union { | |
| __IO uint32_t DLL | |
| __O uint32_t THR | |
| __I uint32_t RBR | |
| }; | |
| union { | |
| __IO uint32_t IER | |
| __IO uint32_t DLM | |
| }; | |
| union { | |
| __O uint32_t FCR | |
| __I uint32_t IIR | |
| }; | |
| __IO uint32_t | LCR |
| __IO uint32_t | MCR |
| __I uint32_t | LSR |
| __I uint32_t | MSR |
| __IO uint32_t | SCR |
| __IO uint32_t | ACR |
| __IO uint32_t | ICR |
| __IO uint32_t | FDR |
| __IO uint32_t | OSR |
| __IO uint32_t | TER1 |
| uint32_t | RESERVED0 [3] |
| __IO uint32_t | HDEN |
| __I uint32_t | RESERVED1 [1] |
| __IO uint32_t | SCICTRL |
| __IO uint32_t | RS485CTRL |
| __IO uint32_t | RS485ADRMATCH |
| __IO uint32_t | RS485DLY |
| union { | |
| __IO uint32_t SYNCCTRL | |
| __I uint32_t FIFOLVL | |
| }; | |
| __IO uint32_t | TER2 |
| union { | |
| __IO uint32_t DLL | |
| __O uint32_t THR | |
| __I uint32_t RBR | |
| }; | |
| union { | |
| __IO uint32_t IER | |
| __IO uint32_t DLM | |
| }; | |
| union { | |
| __O uint32_t FCR | |
| __I uint32_t IIR | |
| }; | |
| union { | |
| __IO uint32_t SYNCCTRL | |
| __I uint32_t FIFOLVL | |
| }; | |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| __IO uint32_t ACR |
Auto-baud Control Register. Contains controls for the auto-baud feature.
Definition at line 73 of file usart_001.h.
| __IO uint32_t DLL |
Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1).
Definition at line 53 of file usart_001.h.
| __IO uint32_t DLM |
Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1).
Definition at line 60 of file usart_001.h.
| __O uint32_t FCR |
FIFO Control Register. Controls UART FIFO usage and modes.
Definition at line 64 of file usart_001.h.
| __IO uint32_t FDR |
Fractional Divider Register. Generates a clock input for the baud rate divider.
Definition at line 75 of file usart_001.h.
| __I uint32_t FIFOLVL |
FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs.
Definition at line 87 of file usart_001.h.
| __IO uint32_t HDEN |
Half-duplex enable Register- only on some UARTs
Definition at line 79 of file usart_001.h.
| __IO uint32_t ICR |
IrDA control register (not all UARTS)
Definition at line 74 of file usart_001.h.
| __IO uint32_t IER |
Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0).
Definition at line 59 of file usart_001.h.
| __I uint32_t IIR |
Interrupt ID Register. Identifies which interrupt(s) are pending.
Definition at line 65 of file usart_001.h.
| __IO uint32_t LCR |
Line Control Register. Contains controls for frame formatting and break generation.
Definition at line 68 of file usart_001.h.
| __I uint32_t LSR |
Line Status Register. Contains flags for transmit and receive status, including line errors.
Definition at line 70 of file usart_001.h.
| __IO uint32_t MCR |
Modem Control Register. Only present on USART ports with full modem support.
Definition at line 69 of file usart_001.h.
| __I uint32_t MSR |
Modem Status Register. Only present on USART ports with full modem support.
Definition at line 71 of file usart_001.h.
| __IO uint32_t OSR |
Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS.
Definition at line 76 of file usart_001.h.
| __I uint32_t RBR |
Receiver Buffer Register. Contains the next received character to be read (DLAB = 0).
Definition at line 55 of file usart_001.h.
| uint32_t RESERVED0 |
Definition at line 78 of file usart_001.h.
| __I uint32_t RESERVED1 |
Definition at line 80 of file usart_001.h.
| __IO uint32_t RS485ADRMATCH |
RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.
Definition at line 83 of file usart_001.h.
| __IO uint32_t RS485CTRL |
RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.
Definition at line 82 of file usart_001.h.
| __IO uint32_t RS485DLY |
RS-485/EIA-485 direction control delay.
Definition at line 84 of file usart_001.h.
| __IO uint32_t SCICTRL |
Smart card interface control register- only on some UARTs
Definition at line 81 of file usart_001.h.
| __IO uint32_t SCR |
Scratch Pad Register. Eight-bit temporary storage for software.
Definition at line 72 of file usart_001.h.
| __IO uint32_t SYNCCTRL |
Synchronous mode control register. Only on USARTs.
Definition at line 86 of file usart_001.h.
| __IO uint32_t TER1 |
Transmit Enable Register. Turns off USART transmitter for use with software flow control.
Definition at line 77 of file usart_001.h.
| __IO uint32_t TER2 |
Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3.
Definition at line 91 of file usart_001.h.
| __O uint32_t THR |
Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0).
Definition at line 54 of file usart_001.h.
1.8.2 
