syscon_8xx.h

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/*
 * @brief LPC8xx System & Control driver inclusion file
 *
 * @note
 * Copyright(C) NXP Semiconductors, 2012
 * All rights reserved.
 *
 * @par
 * Software that is described herein is for illustrative purposes only
 * which provides customers with programming information regarding the
 * LPC products.  This software is supplied "AS IS" without any warranties of
 * any kind, and NXP Semiconductors and its licensor disclaim any and
 * all warranties, express or implied, including all implied warranties of
 * merchantability, fitness for a particular purpose and non-infringement of
 * intellectual property rights.  NXP Semiconductors assumes no responsibility
 * or liability for the use of the software, conveys no license or rights under any
 * patent, copyright, mask work right, or any other intellectual property rights in
 * or to any products. NXP Semiconductors reserves the right to make changes
 * in the software without notification. NXP Semiconductors also makes no
 * representation or warranty that such application will be suitable for the
 * specified use without further testing or modification.
 *
 * @par
 * Permission to use, copy, modify, and distribute this software and its
 * documentation is hereby granted, under NXP Semiconductors' and its
 * licensor's relevant copyrights in the software, without fee, provided that it
 * is used in conjunction with NXP Semiconductors microcontrollers.  This
 * copyright, permission, and disclaimer notice must appear in all copies of
 * this code.
 */

#ifndef __SYSCTL_8XX_H_
#define __SYSCTL_8XX_H_

#ifdef __cplusplus
extern "C" {
#endif

#define SYSCTL_RST_POR    (1 << 0) 
#define SYSCTL_RST_EXTRST (1 << 1) 
#define SYSCTL_RST_WDT    (1 << 2) 
#define SYSCTL_RST_BOD    (1 << 3) 
#define SYSCTL_RST_SYSRST (1 << 4) 
#define SYSCTL_WAKEUP_SPI0TINT    (1 << 0) 
#define SYSCTL_WAKEUP_SPI1INT     (1 << 1) 
#define SYSCTL_WAKEUP_USART0INT   (1 << 3) 
#define SYSCTL_WAKEUP_USART1INT   (1 << 4) 
#define SYSCTL_WAKEUP_USART2INT   (1 << 5) 
#define SYSCTL_WAKEUP_I2CINT      (1 << 8) 
#define SYSCTL_WAKEUP_WWDTINT     (1 << 12) 
#define SYSCTL_WAKEUP_BODINT      (1 << 13) 
#define SYSCTL_WAKEUP_WKTINT      (1 << 15) 
#define SYSCTL_DEEPSLP_BOD_PD    (1 << 3) 
#define SYSCTL_DEEPSLP_WDTOSC_PD (1 << 6) 
#define SYSCTL_SLPWAKE_IRCOUT_PD (1 << 0) 
#define SYSCTL_SLPWAKE_IRC_PD    (1 << 1) 
#define SYSCTL_SLPWAKE_FLASH_PD  (1 << 2) 
#define SYSCTL_SLPWAKE_BOD_PD    (1 << 3) 
#define SYSCTL_SLPWAKE_SYSOSC_PD (1 << 5) 
#define SYSCTL_SLPWAKE_WDTOSC_PD (1 << 6) 
#define SYSCTL_SLPWAKE_SYSPLL_PD (1 << 7) 
#define SYSCTL_SLPWAKE_ACMP_PD   (1 << 15) 
#define SYSCTL_NMISRC_ENABLE   ((uint32_t) 1 << 31) 
typedef struct {
 __IO uint32_t SYSMEMREMAP;   
 __IO uint32_t PRESETCTRL;   
 __IO uint32_t SYSPLLCTRL;   
 __IO uint32_t SYSPLLSTAT;   
 uint32_t RESERVED0[4];
 __IO uint32_t SYSOSCCTRL;   
 __IO uint32_t WDTOSCCTRL;   
 uint32_t RESERVED1[2];
 __IO uint32_t SYSRSTSTAT;   
 uint32_t RESERVED2[3];
 __IO uint32_t SYSPLLCLKSEL;   
 __IO uint32_t SYSPLLCLKUEN;   
 uint32_t RESERVED3[10];
 __IO uint32_t MAINCLKSEL;   
 __IO uint32_t MAINCLKUEN;   
 __IO uint32_t SYSAHBCLKDIV;   
 uint32_t RESERVED4[1];
 __IO uint32_t SYSAHBCLKCTRL;  
 uint32_t RESERVED5[4];
 __IO uint32_t UARTCLKDIV;   
 uint32_t RESERVED6[18];
 __IO uint32_t CLKOUTSEL;   
 __IO uint32_t CLKOUTUEN;   
 __IO uint32_t CLKOUTDIV;   
 uint32_t RESERVED7;
 __IO uint32_t UARTFRGDIV;   
 __IO uint32_t UARTFRGMULT;   
 uint32_t RESERVED8[1];
 __IO uint32_t EXTTRACECMD;   
 __IO uint32_t PIOPORCAP0;   
 uint32_t RESERVED9[12];
 __IO uint32_t IOCONCLKDIV[7];  
 __IO uint32_t BODCTRL;    
 __IO uint32_t SYSTCKCAL;   
 uint32_t RESERVED10[6];
 __IO uint32_t IRQLATENCY;   
 __IO uint32_t NMISRC;    
 __IO uint32_t PINTSEL[8];   
 uint32_t RESERVED11[27];
 __IO uint32_t STARTERP0;   
 uint32_t RESERVED12[3];
 __IO uint32_t STARTERP1;   
 uint32_t RESERVED13[6];
 __IO uint32_t PDSLEEPCFG;   
 __IO uint32_t PDAWAKECFG;   
 __IO uint32_t PDRUNCFG;    
 uint32_t RESERVED14[110];
 __I  uint32_t DEVICEID;    
} LPC_SYSCTL_T;

typedef enum CHIP_SYSCTL_BOOT_MODE_REMAP {
 REMAP_BOOT_LOADER_MODE, 
 REMAP_USER_RAM_MODE, 
 REMAP_USER_FLASH_MODE 
} CHIP_SYSCTL_BOOT_MODE_REMAP_T;

typedef enum {
 RESET_SPI0,   
 RESET_SPI1,   
 RESET_UARTFBRG,  
 RESET_USART0,  
 RESET_USART1,  
 RESET_USART2,  
 RESET_I2C,   
 RESET_MRT,   
 RESET_SCT,   
 RESET_WKT,   
 RESET_GPIO,   
 RESET_FLASH,  
 RESET_ACMP   
} CHIP_SYSCTL_PERIPH_RESET_T;

typedef enum CHIP_SYSCTL_BODRSTLVL {
 SYSCTL_BODRSTLVL_0, 
 SYSCTL_BODRSTLVL_1, 
 SYSCTL_BODRSTLVL_2, 
 SYSCTL_BODRSTLVL_3, 
} CHIP_SYSCTL_BODRSTLVL_T;

typedef enum CHIP_SYSCTL_BODRINTVAL {
 SYSCTL_BODINTVAL_LVL0, /* Brown-out interrupt at 1.65 ~ 1.80v */
 SYSCTL_BODINTVAL_LVL1, /* Brown-out interrupt at 2.22v ~ 2.35v*/
 SYSCTL_BODINTVAL_LVL2, /* Brown-out interrupt at 2.52v ~ 2.66v */
 SYSCTL_BODINTVAL_LVL3, /* Brown-out interrupt at 2.80v ~ 2.90v */
} CHIP_SYSCTL_BODRINTVAL_T;

STATIC INLINE void Chip_SYSCTL_Map(CHIP_SYSCTL_BOOT_MODE_REMAP_T remap)
{
 LPC_SYSCTL->SYSMEMREMAP = (uint32_t) remap;
}

STATIC INLINE void Chip_SYSCTL_AssertPeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
{
 LPC_SYSCTL->PRESETCTRL &= ~(1 << (uint32_t) periph);
}

STATIC INLINE void Chip_SYSCTL_DeassertPeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
{
 LPC_SYSCTL->PRESETCTRL |= (1 << (uint32_t) periph);
}

STATIC INLINE void Chip_SYSCTL_PeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
{
 Chip_SYSCTL_AssertPeriphReset(periph);
 Chip_SYSCTL_DeassertPeriphReset(periph);
}

STATIC INLINE uint32_t Chip_SYSCTL_GetSystemRSTStatus(void)
{
 return LPC_SYSCTL->SYSRSTSTAT;
}

STATIC INLINE void Chip_SYSCTL_ClearSystemRSTStatus(uint32_t reset)
{
 LPC_SYSCTL->SYSRSTSTAT = reset;
}

STATIC INLINE uint32_t Chip_SYSCTL_GetPORPIOStatus(void)
{
 return LPC_SYSCTL->PIOPORCAP0;
}

STATIC INLINE void Chip_SYSCTL_SetBODLevels(CHIP_SYSCTL_BODRSTLVL_T rstlvl,
           CHIP_SYSCTL_BODRINTVAL_T intlvl)
{
 LPC_SYSCTL->BODCTRL = ((uint32_t) rstlvl) | (((uint32_t) intlvl) << 2);
}

STATIC INLINE void Chip_SYSCTL_EnableBODReset(void)
{
 LPC_SYSCTL->BODCTRL |= (1 << 4);
}

STATIC INLINE void Chip_SYSCTL_DisableBODReset(void)
{
 LPC_SYSCTL->BODCTRL &= ~(1 << 4);
}

STATIC INLINE void Chip_SYSCTL_SetSYSTCKCAL(uint32_t sysCalVal)
{
 LPC_SYSCTL->SYSTCKCAL = sysCalVal;
}

STATIC INLINE void Chip_SYSCTL_SetIRQLatency(uint32_t latency)
{
 LPC_SYSCTL->IRQLATENCY = latency;
}

STATIC INLINE uint32_t Chip_SYSCTL_GetIRQLatency(void)
{
 return LPC_SYSCTL->IRQLATENCY;
}

STATIC INLINE void Chip_SYSCTL_SetNMISource(uint32_t intsrc)
{
 LPC_SYSCTL->NMISRC = intsrc;
}

STATIC INLINE void Chip_SYSCTL_EnableNMISource(void)
{
 LPC_SYSCTL->NMISRC |= SYSCTL_NMISRC_ENABLE;
}

STATIC INLINE void Chip_SYSCTL_DisableNMISource(void)
{
 LPC_SYSCTL->NMISRC &= ~(SYSCTL_NMISRC_ENABLE);
}

STATIC INLINE void Chip_SYSCTL_SetPinInterrupt(uint32_t intno, uint32_t pin)
{
 LPC_SYSCTL->PINTSEL[intno] = (uint32_t) pin;
}

STATIC INLINE void Chip_SYSCTL_EnablePINTWakeuup(uint32_t pin)
{
 LPC_SYSCTL->STARTERP0 |= (1 << pin);
}

STATIC INLINE void Chip_SYSCTL_DisablePINTWakeup(uint32_t pin)
{
 LPC_SYSCTL->STARTERP0 &= ~(1 << pin);
}

STATIC INLINE void Chip_SYSCTL_EnablePeriphWakeup(uint32_t periphmask)
{
 LPC_SYSCTL->STARTERP1 |= periphmask;
}

STATIC INLINE void Chip_SYSCTL_DisablePeriphWakeup(uint32_t periphmask)
{
 LPC_SYSCTL->STARTERP1 &= ~periphmask;
}

STATIC INLINE uint32_t Chip_SYSCTL_GetDeepSleepPD(void)
{
 return LPC_SYSCTL->PDSLEEPCFG;
}

STATIC INLINE uint32_t Chip_SYSCTL_GetWakeup(void)
{
 return LPC_SYSCTL->PDAWAKECFG;
}

STATIC INLINE uint32_t Chip_SYSCTL_GetPowerStates(void)
{
 return LPC_SYSCTL->PDRUNCFG;
}

STATIC INLINE uint32_t Chip_SYSCTL_GetDeviceID(void)
{
 return LPC_SYSCTL->DEVICEID;
}

STATIC INLINE void Chip_SYSCTL_SetUSARTFRGDivider(uint8_t div)
{
 LPC_SYSCTL->UARTFRGDIV = (uint32_t) div;
}

STATIC INLINE uint32_t Chip_SYSCTL_GetUSARTFRGDivider(void)
{
 return LPC_SYSCTL->UARTFRGDIV;
}

STATIC INLINE void Chip_SYSCTL_SetUSARTFRGMultiplier(uint8_t mult)
{
 LPC_SYSCTL->UARTFRGMULT = (uint32_t) mult;
}

STATIC INLINE uint32_t Chip_SYSCTL_GetUSARTFRGMultiplier(void)
{
 return LPC_SYSCTL->UARTFRGMULT;
}

void Chip_SYSCTL_SetDeepSleepPD(uint32_t sleepmask);

void Chip_SYSCTL_SetWakeup(uint32_t wakeupmask);

void Chip_SYSCTL_PowerDown(uint32_t powerdownmask);

void Chip_SYSCTL_PowerUp(uint32_t powerupmask);

#ifdef __cplusplus
}
#endif

#endif /* __SYSCTL_8XX_H_ */