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sysinit_keil_mcb_18574357.c
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1 /*
2  * Copyright(C) NXP Semiconductors, 2012
3  * All rights reserved.
4  *
5  * Software that is described herein is for illustrative purposes only
6  * which provides customers with programming information regarding the
7  * LPC products. This software is supplied "AS IS" without any warranties of
8  * any kind, and NXP Semiconductors and its licensor disclaim any and
9  * all warranties, express or implied, including all implied warranties of
10  * merchantability, fitness for a particular purpose and non-infringement of
11  * intellectual property rights. NXP Semiconductors assumes no responsibility
12  * or liability for the use of the software, conveys no license or rights under any
13  * patent, copyright, mask work right, or any other intellectual property rights in
14  * or to any products. NXP Semiconductors reserves the right to make changes
15  * in the software without notification. NXP Semiconductors also makes no
16  * representation or warranty that such application will be suitable for the
17  * specified use without further testing or modification.
18  *
19  * Permission to use, copy, modify, and distribute this software and its
20  * documentation is hereby granted, under NXP Semiconductors' and its
21  * licensor's relevant copyrights in the software, without fee, provided that it
22  * is used in conjunction with NXP Semiconductors microcontrollers. This
23  * copyright, permission, and disclaimer notice must appear in all copies of
24  * this code.
25  */
26 
27 #include "board.h"
28 
56 #ifndef CORE_M0
57 /* SCR pin definitions for pin muxing */
58 typedef struct {
59  uint8_t pingrp; /* Pin group */
60  uint8_t pinnum; /* Pin number */
61  uint16_t modefunc; /* Pin mode and function for SCU */
62 } PINMUX_GRP_T;
63 
64 /* Structure for initial base clock states */
65 struct CLK_BASE_STATES {
66  CHIP_CGU_BASE_CLK_T clk; /* Base clock */
67  CHIP_CGU_CLKIN_T clkin; /* Base clock source, see UM for allowable souorces per base clock */
68  bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */
69  bool powerdn; /* Set to true if the base clock is initially powered down */
70 };
71 
72 /* Initial base clock states are mostly on */
73 STATIC const struct CLK_BASE_STATES InitClkStates[] = {
74  {CLK_BASE_SAFE, CLKIN_IRC, true, false},
75  {CLK_BASE_APB1, CLKIN_MAINPLL, true, false},
76  {CLK_BASE_APB3, CLKIN_MAINPLL, true, false},
77  {CLK_BASE_USB0, CLKIN_USBPLL, true, true},
78 #if defined(CHIP_LPC43XX)
79  {CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false},
80  {CLK_BASE_SPI, CLKIN_MAINPLL, true, false},
81  {CLK_BASE_VADC, CLKIN_MAINPLL, true, true},
82 #endif
83  {CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false},
84 #if defined(USE_RMII)
85  {CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false},
86 #else
87  {CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false},
88 #endif
89  {CLK_BASE_SDIO, CLKIN_MAINPLL, true, false},
90  {CLK_BASE_SSP0, CLKIN_MAINPLL, true, false},
91  {CLK_BASE_SSP1, CLKIN_MAINPLL, true, false},
92  {CLK_BASE_UART0, CLKIN_MAINPLL, true, false},
93  {CLK_BASE_UART1, CLKIN_MAINPLL, true, false},
94  {CLK_BASE_UART2, CLKIN_MAINPLL, true, false},
95  {CLK_BASE_UART3, CLKIN_MAINPLL, true, false},
96  {CLK_BASE_OUT, CLKINPUT_PD, true, false},
97  {CLK_BASE_APLL, CLKINPUT_PD, true, false},
98  {CLK_BASE_CGU_OUT0, CLKINPUT_PD, true, false},
99  {CLK_BASE_CGU_OUT1, CLKINPUT_PD, true, false},
100 
101  /* Clocks derived from dividers */
102  {CLK_BASE_LCD, CLKIN_IDIVC, true, false},
103  {CLK_BASE_USB1, CLKIN_IDIVD, true, true}
104 };
105 
106 /* SPIFI high speed pin mode setup */
107 STATIC const PINMUX_GRP_T spifipinmuxing[] = {
108  {0x3, 3, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
109  {0x3, 4, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
110  {0x3, 5, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
111  {0x3, 6, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
112  {0x3, 7, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
113  {0x3, 8, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}
114 };
115 
116 /* USB PLL pre-initialized setup values for 480MHz output rate */
117 static const CGU_USBAUDIO_PLL_SETUP_T usbPLLSetup = {
118  0x0000601D, /* Default control with main osc input, PLL disabled */
119  0x06167FFA, /* M-divider value for 480MHz output from 12MHz input */
120  0x00000000, /* N-divider value */
121  0x00000000 /* Not applicable for USB PLL */
122 };
123 
124 /* Audio PLL pre-initialized setup values for FIXME output rate */
125 // static const CGU_USBAUDIO_PLL_SETUP_T audioPLLSetup = {
126 // 0x0000601D, /* Default control with main osc input, PLL disabled */
127 // 0x06167FFA, /* M-divider value for FIXME output from 12MHz input */
128 // 0x00000000, /* N-divider value */
129 // 0x00000000 /* FIXME */
130 // };
131 
132 /* Setup system clocking */
133 STATIC void SystemSetupClocking(void)
134 {
135  int i;
136 
137  /* Setup FLASH acceleration to target clock rate prior to clock switch */
138  Chip_CREG_SetFlashAcceleration(MAX_CLOCK_FREQ);
139 
140  /* Switch main system clocking to crystal */
141  Chip_Clock_EnableCrystal();
142  Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false);
143 
144  /* Setup PLL for 100MHz and switch main system clocking */
145  Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000);
146  Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);
147 
148  /* Setup PLL for maximum clock */
149  Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ);
150 
151  /* Setup system base clocks and initial states. This won't enable and
152  disable individual clocks, but sets up the base clock sources for
153  each individual peripheral clock. */
154  for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
155  Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
156  InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
157  }
158 
159  /* Reset and enable 32Khz oscillator */
160  LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
161  LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
162 
163  /* SPIFI pin setup is done prior to setting up system clocking */
164  for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) {
165  Chip_SCU_PinMuxSet(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum,
166  spifipinmuxing[i].modefunc);
167  }
168 
169  /* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
170  Divide rate is based on CPU speed and speed of SPI FLASH part. */
171 #if (MAX_CLOCK_FREQ > 180000000)
172  Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
173 #else
174  Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
175 #endif
176  Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
177 
178  /* LCD with HX8347-D LCD Controller */
179  /* Attach main PLL clock to divider C with a divider of 2 */
180  Chip_Clock_SetDivider(CLK_IDIV_C, CLKIN_MAINPLL, 2);
181 
182  /* Setup default USB PLL state for a 480MHz output and attach */
183  Chip_Clock_SetupPLL(CLKIN_CRYSTAL, CGU_USB_PLL, &usbPLLSetup);
184 
185  /* USB1 needs a 60MHz clock. To get it, a divider of 4 and then 2 are
186  chained to make a divide by 8 function. Connect the output of
187  divider D to the USB1 base clock. */
188  Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_USBPLL, 4);
189  Chip_Clock_SetDivider(CLK_IDIV_D, CLKIN_IDIVA, 2);
190  Chip_Clock_SetBaseClock(CLK_BASE_USB1, CLKIN_IDIVD, true, true);
191 
192  /* Setup default audio PLL state for a FIXME output */
193  // Chip_Clock_SetupPLL(CGU_AUDIO_PLL, &audioPLLSetup); // FIXME
194 }
195 
196 STATIC const PINMUX_GRP_T pinmuxing[] = {
197  /* RMII pin group */
198  {0x1, 19,
199  (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0)},
200  {0x0, 1, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC6)},
201  {0x1, 18, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
202  {0x1, 20, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
203  {0x1, 17,
204  (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
205  {0xC, 1, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
206  {0x1, 16,
207  (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC7)},
208  {0x1, 15,
209  (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
210  {0x0, 0,
211  (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2)},
212  /* External data lines D0 .. D15 */
213  {0x1, 7,
214  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
215  {0x1, 8,
216  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
217  {0x1, 9,
218  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
219  {0x1, 10,
220  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
221  {0x1, 11,
222  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
223  {0x1, 12,
224  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
225  {0x1, 13,
226  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
227  {0x1, 14,
228  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
229  {0x5, 4,
230  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
231  {0x5, 5,
232  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
233  {0x5, 6,
234  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
235  {0x5, 7,
236  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
237  {0x5, 0,
238  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
239  {0x5, 1,
240  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
241  {0x5, 2,
242  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
243  {0x5, 3,
244  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
245  {0xD, 2,
246  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
247  {0xD, 3,
248  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
249  {0xD, 4,
250  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
251  {0xD, 5,
252  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
253  {0xD, 6,
254  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
255  {0xD, 7,
256  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
257  {0xD, 8,
258  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
259  {0xD, 9,
260  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
261  {0xE, 5,
262  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
263  {0xE, 6,
264  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
265  {0xE, 7,
266  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
267  {0xE, 8,
268  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
269  {0xE, 9,
270  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
271  {0xE, 10,
272  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
273  {0xE, 11,
274  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
275  {0xE, 12,
276  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
277  /* Address lines A0 .. A23 */
278  {0x2, 9,
279  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
280  {0x2, 10,
281  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
282  {0x2, 11,
283  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
284  {0x2, 12,
285  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
286  {0x2, 13,
287  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
288  {0x1, 0,
289  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
290  {0x1, 1,
291  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
292  {0x1, 2,
293  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
294  {0x2, 8,
295  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
296  {0x2, 7,
297  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
298  {0x2, 6,
299  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
300  {0x2, 2,
301  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
302  {0x2, 1,
303  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
304  {0x2, 0,
305  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
306  {0x6, 8,
307  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC1)},
308  {0x6, 7,
309  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC1)},
310  {0xD, 16,
311  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
312  {0xD, 15,
313  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
314  {0xE, 0,
315  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
316  {0xE, 1,
317  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
318  {0xE, 2,
319  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
320  {0xE, 3,
321  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
322  {0xE, 4,
323  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
324  {0xA, 4,
325  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
326  /* EMC control signals */
327  {0x1, 4,
328  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
329  {0x6, 6,
330  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC1)},
331  {0xD, 13,
332  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
333  {0xD, 10,
334  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
335  {0x6, 9,
336  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
337  {0x1, 6,
338  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
339  {0x6, 4,
340  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
341  {0x6, 5,
342  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
343  {0x6, 11,
344  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
345  {0x6, 12,
346  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
347  {0x6, 10,
348  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
349  {0xD, 0,
350  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
351  {0xE, 13,
352  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
353  {0x1, 3, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
354  {0x1, 4, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
355  {0x6, 6, (SCU_PINIO_FAST | SCU_MODE_FUNC1)},
356  {0x1, 5, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
357  {0x1, 6, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
358  /* Board LEDs */
359  {0xD, 10, (SCU_MODE_MODE_PULLUP | SCU_MODE_FUNC4)},
360  {0xD, 11, (SCU_MODE_MODE_PULLUP | SCU_MODE_FUNC4)},
361  {0xD, 12, (SCU_MODE_MODE_PULLUP | SCU_MODE_FUNC4)},
362  {0xD, 13, (SCU_MODE_MODE_PULLUP | SCU_MODE_FUNC4)},
363  {0xD, 14, (SCU_MODE_MODE_PULLUP | SCU_MODE_FUNC4)},
364  {0x9, 0, (SCU_MODE_MODE_PULLUP | SCU_MODE_FUNC0)},
365  {0x9, 1, (SCU_MODE_MODE_PULLUP | SCU_MODE_FUNC0)},
366  {0x9, 2, (SCU_MODE_MODE_PULLUP | SCU_MODE_FUNC0)},
367  /* SSP0 */
368  {0xF, 0, (SCU_PINIO_FAST | SCU_MODE_FUNC0)},
369  {0xF, 1, (SCU_PINIO_FAST | SCU_MODE_FUNC4)},
370  {0xF, 2, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
371  {0xF, 3, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
372  /* LCD interface, 16bpp */
373  {0x4, 1, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC5)},
374  {0x4, 2, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC2)},
375  {0x4, 5, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC2)},
376  {0x4, 6, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC2)},
377  {0x4, 7, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC0)},
378  {0x4, 9, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC2)},
379  {0x4, 10, (SCU_MODE_MODE_INACT | SCU_MODE_FUNC2)},
380  {0x7, 0, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC0)},
381  {0x7, 6, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC3)},
382  {0x8, 3, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC3)},
383  {0x8, 4, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC3)},
384  {0x8, 5, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC3)},
385  {0x8, 6, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC3)},
386  {0x8, 7, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC3)},
387  {0xB, 0, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC2)},
388  {0xB, 1, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC2)},
389  {0xB, 2, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC2)},
390  {0xB, 3, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC2)},
391  {0xB, 4, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC2)},
392  {0xB, 5, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC2)},
393  {0xB, 6, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC2)},
394  /* I2S */
395  {0x3, 0, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
396  {0x6, 0, (SCU_PINIO_FAST | SCU_MODE_FUNC4)},
397  {0x7, 2, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
398  {0x6, 2, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
399  {0x7, 1, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
400  {0x6, 1, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
401  /* CCAN */
402  {0x3, 2, (SCU_MODE_MODE_PULLUP | SCU_MODE_FUNC2)}, /* PE.3 CAN TD1 | SCU_MODE_FUNC1) */
403  {0x3, 1, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC2)}, /* PE.2 CAN RD1 | SCU_MODE_FUNC1) */
404 };
405 
406 /* Pin clock mux values, re-used structure, value in first index is meaningless */
407 STATIC const PINMUX_GRP_T pinclockmuxing[] = {
408  {0, 0, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
409  {0, 1, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
410  {0, 2, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
411  {0, 3, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
412 };
413 
414 /* Sets up system pin muxing */
415 STATIC void SystemSetupMuxing(void)
416 {
417  int i;
418 
419  /* Setup system level pin muxing */
420  for (i = 0; i < (sizeof(pinmuxing) / sizeof(pinmuxing[0])); i++) {
421  Chip_SCU_PinMuxSet(pinmuxing[i].pingrp, pinmuxing[i].pinnum,
422  pinmuxing[i].modefunc);
423  }
424  /* Clock pins only, group field not used */
425  for (i = 0; i < (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++) {
426  Chip_SCU_ClockPinMuxSet(pinclockmuxing[i].pinnum, pinclockmuxing[i].modefunc);
427  }
428 }
429 
430 /* EMC clock delay */
431 #define CLK0_DELAY 7
432 
433 /* Keil SDRAM timing and chip Config */
434 STATIC const IP_EMC_DYN_CONFIG_T MT48LC4M32_config = {
435  EMC_NANOSECOND(64000000 / 4096), /* Row refresh time */
436  0x01, /* Command Delayed */
437  EMC_NANOSECOND(18),
438  EMC_NANOSECOND(42),
439  EMC_NANOSECOND(70),
440  EMC_CLOCK(0x01),
441  EMC_CLOCK(0x05),
442  EMC_NANOSECOND(12),
443  EMC_NANOSECOND(60),
444  EMC_NANOSECOND(60),
445  EMC_NANOSECOND(70),
446  EMC_NANOSECOND(12),
447  EMC_CLOCK(0x02),
448  {
449  {
450  EMC_ADDRESS_DYCS0, /* Keil Board uses DYCS0 for SDRAM */
451  3, /* RAS */
452 
453  EMC_DYN_MODE_WBMODE_PROGRAMMED |
454  EMC_DYN_MODE_OPMODE_STANDARD |
455  EMC_DYN_MODE_CAS_3 |
456  EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL |
457  EMC_DYN_MODE_BURST_LEN_4,
458 
459  EMC_DYN_CONFIG_DATA_BUS_32 |
460  EMC_DYN_CONFIG_LPSDRAM |
461  EMC_DYN_CONFIG_4Mx32_4BANKS_12ROWS_8COLS |
462  EMC_DYN_CONFIG_MD_SDRAM
463  },
464  {0, 0, 0, 0},
465  {0, 0, 0, 0},
466  {0, 0, 0, 0}
467  }
468 };
469 
470 /* Keil NorFlash timing and chip Config */
471 /* FIXME : Keil NOR FLASH not yet tested */
472 STATIC const IP_EMC_STATIC_CONFIG_T S29GL64N90_config = {
473  0,
474  EMC_STATIC_CONFIG_MEM_WIDTH_32 |
475  EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW |
476  EMC_STATIC_CONFIG_BLS_HIGH /* |
477  EMC_CONFIG_BUFFER_ENABLE*/,
478 
479  EMC_NANOSECOND(0),
480  EMC_NANOSECOND(65),
481  EMC_NANOSECOND(90),
482  EMC_NANOSECOND(90),
483  EMC_NANOSECOND(35),
484  EMC_CLOCK(4)
485 };
486 
487 /* Setup external memories */
488 STATIC void SystemSetupMemory(void)
489 {
490  /* Setup EMC Delays */
491  /* Move all clock delays together */
492  LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY) | (CLK0_DELAY << 4) | (CLK0_DELAY << 8) | (CLK0_DELAY << 12));
493 
494  /* Setup EMC Clock Divider for divide by 2 - this is done in both the CCU (clocking)
495  and CREG. For frequencies over 120MHz, a divider of 2 must be used. For frequencies
496  less than 120MHz, a divider of 1 or 2 is ok. */
497  Chip_Clock_EnableOpts(CLK_MX_EMC_DIV, true, true, 2);
498  LPC_CREG->CREG6 |= (1 << 16);
499 
500  /* Enable EMC clock */
501  Chip_Clock_Enable(CLK_MX_EMC);
502 
503  /* Init EMC Controller -Enable-LE mode */
504  Chip_EMC_Init(1, 0);
505  /* Init EMC Dynamic Controller */
506  Chip_EMC_Dynamic_Init((IP_EMC_DYN_CONFIG_T *) &MT48LC4M32_config);
507  /* Init EMC Static Controller CS0 */
508  Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_T *) &S29GL64N90_config);
509 
510  /* Enable Buffer for External Flash */
511  LPC_EMC->STATICCONFIG0 |= 1 << 19;
512 }
513 
514 #endif
515 
523 void SystemInit(void)
524 {
525 #if defined(CORE_M3) || defined(CORE_M4)
526  unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
527 
528 #if defined(__IAR_SYSTEMS_ICC__)
529  extern void *__vector_table;
530 
531  *pSCB_VTOR = (unsigned int) &__vector_table;
532 #elif defined(__CODE_RED)
533  extern void *g_pfnVectors;
534 
535  *pSCB_VTOR = (unsigned int) &g_pfnVectors;
536 #elif defined(__ARMCC_VERSION)
537  extern void *__Vectors;
538 
539  *pSCB_VTOR = (unsigned int) &__Vectors;
540 #endif
541 
542 #if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
543  fpuInit();
544 #endif
545 
546  /* Setup system clocking and memory. This is done early to allow the
547  application and tools to clear memory and use scatter loading to
548  external memory. */
549  SystemSetupClocking();
550  SystemSetupMuxing();
551  SystemSetupMemory();
552 #endif
553 }
554