timer_001.h

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/*
 * @brief 32-bit Timer/PWM registers and control functions
 *
 * @note
 * Copyright(C) NXP Semiconductors, 2012
 * All rights reserved.
 *
 * @par
 * Software that is described herein is for illustrative purposes only
 * which provides customers with programming information regarding the
 * LPC products.  This software is supplied "AS IS" without any warranties of
 * any kind, and NXP Semiconductors and its licensor disclaim any and
 * all warranties, express or implied, including all implied warranties of
 * merchantability, fitness for a particular purpose and non-infringement of
 * intellectual property rights.  NXP Semiconductors assumes no responsibility
 * or liability for the use of the software, conveys no license or rights under any
 * patent, copyright, mask work right, or any other intellectual property rights in
 * or to any products. NXP Semiconductors reserves the right to make changes
 * in the software without notification. NXP Semiconductors also makes no
 * representation or warranty that such application will be suitable for the
 * specified use without further testing or modification.
 *
 * @par
 * Permission to use, copy, modify, and distribute this software and its
 * documentation is hereby granted, under NXP Semiconductors' and its
 * licensor's relevant copyrights in the software, without fee, provided that it
 * is used in conjunction with NXP Semiconductors microcontrollers.  This
 * copyright, permission, and disclaimer notice must appear in all copies of
 * this code.
 */

#ifndef __TIMER_001_H_
#define __TIMER_001_H_

#include "sys_config.h"
#include "cmsis.h"

#ifdef __cplusplus
extern "C" {
#endif

typedef struct {     
 __IO uint32_t IR;    
 __IO uint32_t TCR;    
 __IO uint32_t TC;    
 __IO uint32_t PR;    
 __IO uint32_t PC;    
 __IO uint32_t MCR;    
 __IO uint32_t MR[4];   
 __IO uint32_t CCR;    
 __IO uint32_t CR[4];   
 __IO uint32_t EMR;    
 __I  uint32_t RESERVED0[12];
 __IO uint32_t CTCR;    
#if defined(CHIP_LPC110X) || defined(CHIP_LPC11XXLV) || defined(CHIP_LPC11AXX) || \
  defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
 __IO uint32_t PWMC;
#endif
} IP_TIMER_001_T;

#define TIMER_IR_CLR(n)         _BIT(n)

#define TIMER_MATCH_INT(n)      (_BIT((n) & 0x0F))

#define TIMER_CAP_INT(n)        (_BIT((((n) & 0x0F) + 4)))

#define TIMER_ENABLE            ((uint32_t) (1 << 0))

#define TIMER_RESET             ((uint32_t) (1 << 1))

#define TIMER_INT_ON_MATCH(n)   (_BIT(((n) * 3)))

#define TIMER_RESET_ON_MATCH(n) (_BIT((((n) * 3) + 1)))

#define TIMER_STOP_ON_MATCH(n)  (_BIT((((n) * 3) + 2)))

#define TIMER_CAP_RISING(n)     (_BIT(((n) * 3)))

#define TIMER_CAP_FALLING(n)    (_BIT((((n) * 3) + 1)))

#define TIMER_INT_ON_CAP(n)     (_BIT((((n) * 3) + 2)))

STATIC INLINE bool IP_TIMER_MatchPending(IP_TIMER_001_T *pTimer, int8_t matchnum)
{
 return (bool) ((pTimer->IR & TIMER_MATCH_INT(matchnum)) != 0);
}

STATIC INLINE bool IP_TIMER_CapturePending(IP_TIMER_001_T *pTimer, int8_t capnum)
{
 return (bool) ((pTimer->IR & TIMER_CAP_INT(capnum)) != 0);
}

STATIC INLINE void IP_TIMER_ClearMatch(IP_TIMER_001_T *pTimer, int8_t matchnum)
{
 pTimer->IR = TIMER_IR_CLR(matchnum);
}

STATIC INLINE void IP_TIMER_ClearCapture(IP_TIMER_001_T *pTimer, int8_t capnum)
{
 pTimer->IR = (0x10 << capnum);
}

STATIC INLINE void IP_TIMER_Enable(IP_TIMER_001_T *pTimer)
{
 pTimer->TCR |= TIMER_ENABLE;
}

STATIC INLINE void IP_TIMER_Disable(IP_TIMER_001_T *pTimer)
{
 pTimer->TCR &= ~TIMER_ENABLE;
}

STATIC INLINE uint32_t IP_TIMER_ReadCount(IP_TIMER_001_T *pTimer)
{
 return pTimer->TC;
}

STATIC INLINE uint32_t IP_TIMER_ReadPrescale(IP_TIMER_001_T *pTimer)
{
 return pTimer->PC;
}

STATIC INLINE void IP_TIMER_PrescaleSet(IP_TIMER_001_T *pTimer, uint32_t prescale)
{
 pTimer->PR = prescale;
}

STATIC INLINE void IP_TIMER_SetMatch(IP_TIMER_001_T *pTimer, int8_t matchnum, uint32_t matchval)
{
 pTimer->MR[matchnum] = matchval;
}

STATIC INLINE uint32_t IP_TIMER_ReadCapture(IP_TIMER_001_T *pTimer, int8_t capnum)
{
 return pTimer->CR[capnum];
}

void IP_TIMER_Reset(IP_TIMER_001_T *pTimer);

STATIC INLINE void IP_TIMER_MatchEnableInt(IP_TIMER_001_T *pTimer, int8_t matchnum)
{
 pTimer->MCR |= TIMER_INT_ON_MATCH(matchnum);
}

STATIC INLINE void IP_TIMER_MatchDisableInt(IP_TIMER_001_T *pTimer, int8_t matchnum)
{
 pTimer->MCR &= ~TIMER_INT_ON_MATCH(matchnum);
}

STATIC INLINE void IP_TIMER_ResetOnMatchEnable(IP_TIMER_001_T *pTimer, int8_t matchnum)
{
 pTimer->MCR |= TIMER_RESET_ON_MATCH(matchnum);
}

STATIC INLINE void IP_TIMER_ResetOnMatchDisable(IP_TIMER_001_T *pTimer, int8_t matchnum)
{
 pTimer->MCR &= ~TIMER_RESET_ON_MATCH(matchnum);
}

STATIC INLINE void IP_TIMER_StopOnMatchEnable(IP_TIMER_001_T *pTimer, int8_t matchnum)
{
 pTimer->MCR |= TIMER_STOP_ON_MATCH(matchnum);
}

STATIC INLINE void IP_TIMER_StopOnMatchDisable(IP_TIMER_001_T *pTimer, int8_t matchnum)
{
 pTimer->MCR &= ~TIMER_STOP_ON_MATCH(matchnum);
}

STATIC INLINE void IP_TIMER_CaptureRisingEdgeEnable(IP_TIMER_001_T *pTimer, int8_t capnum)
{
 pTimer->CCR |= TIMER_CAP_RISING(capnum);
}

STATIC INLINE void IP_TIMER_CaptureRisingEdgeDisable(IP_TIMER_001_T *pTimer, int8_t capnum)
{
 pTimer->CCR &= ~TIMER_CAP_RISING(capnum);
}

STATIC INLINE void IP_TIMER_CaptureFallingEdgeEnable(IP_TIMER_001_T *pTimer, int8_t capnum)
{
 pTimer->CCR |= TIMER_CAP_FALLING(capnum);
}

STATIC INLINE void IP_TIMER_CaptureFallingEdgeDisable(IP_TIMER_001_T *pTimer, int8_t capnum)
{
 pTimer->CCR &= ~TIMER_CAP_FALLING(capnum);
}

STATIC INLINE void IP_TIMER_CaptureEnableInt(IP_TIMER_001_T *pTimer, int8_t capnum)
{
 pTimer->CCR |= TIMER_INT_ON_CAP(capnum);
}

STATIC INLINE void IP_TIMER_CaptureDisableInt(IP_TIMER_001_T *pTimer, int8_t capnum)
{
 pTimer->CCR &= ~TIMER_INT_ON_CAP(capnum);
}

typedef enum IP_TIMER_PIN_MATCH_STATE {
 TIMER_EXTMATCH_DO_NOTHING = 0, 
 TIMER_EXTMATCH_CLEAR      = 1, 
 TIMER_EXTMATCH_SET        = 2, 
 TIMER_EXTMATCH_TOGGLE     = 3 
} IP_TIMER_PIN_MATCH_STATE_T;

void IP_TIMER_ExtMatchControlSet(IP_TIMER_001_T *pTimer, int8_t initial_state,
         IP_TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum);

typedef enum IP_TIMER_CAP_SRC_STATE {
 TIMER_CAPSRC_RISING_PCLK  = 0, 
 TIMER_CAPSRC_RISING_CAPN  = 1, 
 TIMER_CAPSRC_FALLING_CAPN = 2, 
 TIMER_CAPSRC_BOTH_CAPN    = 3 
} IP_TIMER_CAP_SRC_STATE_T;

void IP_TIMER_SetCountClockSrc(IP_TIMER_001_T *pTimer,
          IP_TIMER_CAP_SRC_STATE_T capSrc, int8_t capnum);

#ifdef __cplusplus
}
#endif

#endif /* __TIMER_001_H_ */