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LPCOpen Platform
v1.03
LPCOpen Platform for NXP LPC Microcontrollers
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#include "sys_config.h"#include "cmsis.h"Go to the source code of this file.
Data Structures | |
| struct | IP_USART_001_T |
| USART register block structure. More... | |
Macros | |
| #define | UART_RBR_MASKBIT (0xFF) |
| #define | UART_IER_RBRINT (1 << 0) |
| Macro defines for UART interrupt enable register. | |
| #define | UART_IER_THREINT (1 << 1) |
| #define | UART_IER_RLSINT (1 << 2) |
| #define | UART_IER_MSINT (1 << 3) |
| #define | UART_IER_CTSINT (1 << 7) |
| #define | UART_IER_ABEOINT (1 << 8) |
| #define | UART_IER_ABTOINT (1 << 9) |
| #define | UART_IER_BITMASK (0x307) |
| #define | UART1_IER_BITMASK (0x38F) |
| #define | UART_IIR_INTSTAT_PEND (1 << 0) |
| Macro defines for UART interrupt identification register. | |
| #define | UART_IIR_INTID_RLS (3 << 1) |
| #define | UART_IIR_INTID_RDA (2 << 1) |
| #define | UART_IIR_INTID_CTI (6 << 1) |
| #define | UART_IIR_INTID_THRE (1 << 1) |
| #define | UART_IIR_INTID_MODEM (0 << 1) |
| #define | UART_IIR_INTID_MASK (7 << 1) |
| #define | UART_IIR_FIFO_EN (3 << 6) |
| #define | UART_IIR_ABEO_INT (1 << 8) |
| #define | UART_IIR_ABTO_INT (1 << 9) |
| #define | UART_IIR_BITMASK (0x3CF) |
| #define | UART_FCR_FIFO_EN (1 << 0) |
| Macro defines for UART FIFO control register. | |
| #define | UART_FCR_RX_RS (1 << 1) |
| #define | UART_FCR_TX_RS (1 << 2) |
| #define | UART_FCR_DMAMODE_SEL (1 << 3) |
| #define | UART_FCR_TRG_LEV0 (0) |
| #define | UART_FCR_TRG_LEV1 (1 << 6) |
| #define | UART_FCR_TRG_LEV2 (2 << 6) |
| #define | UART_FCR_TRG_LEV3 (3 << 6) |
| #define | UART_FCR_BITMASK (0xCF) |
| #define | UART_TX_FIFO_SIZE (16) |
| #define | UART_LCR_WLEN5 (0) |
| Macro defines for UART line control register. | |
| #define | UART_LCR_WLEN6 (1 << 0) |
| #define | UART_LCR_WLEN7 (2 << 0) |
| #define | UART_LCR_WLEN8 (3 << 0) |
| #define | UART_LCR_SBS_1BIT (0 << 2) |
| #define | UART_LCR_SBS_2BIT (1 << 2) |
| #define | UART_LCR_PARITY_EN (1 << 3) |
| #define | UART_LCR_PARITY_DIS (0 << 3) |
| #define | UART_LCR_PARITY_ODD (0) |
| #define | UART_LCR_PARITY_EVEN (1 << 4) |
| #define | UART_LCR_PARITY_F_1 (2 << 4) |
| #define | UART_LCR_PARITY_F_0 (3 << 4) |
| #define | UART_LCR_BREAK_EN (1 << 6) |
| #define | UART_LCR_DLAB_EN (1 << 7) |
| #define | UART_LCR_BITMASK (0xFF) |
| #define | UART_DLL_MASKBIT (0xFF) |
| #define | UART_DLM_MASKBIT (0xFF) |
| #define | UART_MCR_DTR_CTRL (1 << 0) |
| Macro defines for UART Modem control register. | |
| #define | UART_MCR_RTS_CTRL (1 << 1) |
| #define | UART_MCR_LOOPB_EN (1 << 4) |
| #define | UART_MCR_AUTO_RTS_EN (1 << 6) |
| #define | UART_MCR_AUTO_CTS_EN (1 << 7) |
| #define | UART_MCR_BITMASK (0x0F3) |
| #define | UART_LSR_RDR (1 << 0) |
| Macro defines for UART line status register. | |
| #define | UART_LSR_OE (1 << 1) |
| #define | UART_LSR_PE (1 << 2) |
| #define | UART_LSR_FE (1 << 3) |
| #define | UART_LSR_BI (1 << 4) |
| #define | UART_LSR_THRE (1 << 5) |
| #define | UART_LSR_TEMT (1 << 6) |
| #define | UART_LSR_RXFE (1 << 7) |
| #define | UART_LSR_BITMASK (0xFF) |
| #define | UART_MSR_DELTA_CTS (1 << 0) |
| Macro defines for UART Modem status register. | |
| #define | UART_MSR_DELTA_DSR (1 << 1) |
| #define | UART_MSR_LO2HI_RI (1 << 2) |
| #define | UART_MSR_DELTA_DCD (1 << 3) |
| #define | UART_MSR_CTS (1 << 4) |
| #define | UART_MSR_DSR (1 << 5) |
| #define | UART_MSR_RI (1 << 6) |
| #define | UART_MSR_DCD (1 << 7) |
| #define | UART_MSR_BITMASK (0xFF) |
| #define | UART_ACR_START (1 << 0) |
| Macro defines for UART Auto baudrate control register. | |
| #define | UART_ACR_MODE (1 << 1) |
| #define | UART_ACR_AUTO_RESTART (1 << 2) |
| #define | UART_ACR_ABEOINT_CLR (1 << 8) |
| #define | UART_ACR_ABTOINT_CLR (1 << 9) |
| #define | UART_ACR_BITMASK (0x307) |
| #define | UART_RS485CTRL_NMM_EN (1 << 0) |
| Macro defines for UART1 RS485 Control register. | |
| #define | UART_RS485CTRL_RX_DIS (1 << 1) |
| #define | UART_RS485CTRL_AADEN (1 << 2) |
| #define | UART_RS485CTRL_SEL_DTR (1 << 3) |
| #define | UART_RS485CTRL_DCTRL_EN (1 << 4) |
| #define | UART_RS485CTRL_OINV_1 (1 << 5) |
| #define | UART_RS485CTRL_BITMASK (0x3F) |
Functions | |
| void | IP_UART_Init (IP_USART_001_T *pUART) |
| Basic UART initialization. | |
| STATIC INLINE void | IP_UART_DeInit (IP_USART_001_T *pUART) |
| UART de-initialization. | |
| STATIC INLINE void | IP_UART_SendByte (IP_USART_001_T *pUART, const uint8_t data) |
| Transmit a single byte through the UART peripheral. | |
| STATIC INLINE uint8_t | IP_UART_ReadByte (IP_USART_001_T *pUART) |
| Get a single data from UART peripheral. | |
| STATIC INLINE void | IP_UART_IntEnable (IP_USART_001_T *pUART, uint32_t intMask) |
| Enable UART interrupts. | |
| STATIC INLINE void | IP_UART_IntDisable (IP_USART_001_T *pUART, uint32_t intMask) |
| Disable UART interrupts. | |
| STATIC INLINE uint32_t | IP_UART_ReadIntIDReg (IP_USART_001_T *pUART) |
| Read the Interrupt Identification Register (IIR) | |
| STATIC INLINE void | IP_UART_SetupFIFOS (IP_USART_001_T *pUART, uint32_t fcr) |
| Setup the UART FIFOs. | |
| STATIC INLINE void | IP_UART_SetMode (IP_USART_001_T *pUART, uint32_t lcr) |
| Setup the UART operation mode in the Line Control Register (LCR) | |
| STATIC INLINE void | IP_UART_EnableDivisorAccess (IP_USART_001_T *pUART) |
| Enable access to Divisor Latches. | |
| STATIC INLINE void | IP_UART_DisableDivisorAccess (IP_USART_001_T *pUART) |
| Disable access to Divisor Latches. | |
| STATIC INLINE void | IP_UART_SetDivisorLatches (IP_USART_001_T *pUART, uint8_t dll, uint8_t dlm) |
| Set LSB and MSB divisor latch registers. | |
| STATIC INLINE uint32_t | IP_UART_ReadModemControl (IP_USART_001_T *pUART) |
| Return modem control register/status. | |
| STATIC INLINE void | IP_UART_SetModemControl (IP_USART_001_T *pUART, uint32_t mcr) |
| Set modem control register/status. | |
| STATIC INLINE void | IP_UART_ClearModemControl (IP_USART_001_T *pUART, uint32_t mcr) |
| Clear modem control register/status. | |
| STATIC INLINE uint32_t | IP_UART_ReadLineStatus (IP_USART_001_T *pUART) |
| Return Line Status register/status (LSR) | |
| STATIC INLINE uint32_t | IP_UART_ReadModemStatus (IP_USART_001_T *pUART) |
| Return Modem Status register/status (MSR) | |
| STATIC INLINE void | IP_UART_SetScratch (IP_USART_001_T *pUART, uint8_t data) |
| Write a byte to the scratchpad register. | |
| STATIC INLINE uint8_t | IP_UART_ReadScratch (IP_USART_001_T *pUART) |
| Returns current byte value in the scratchpad register. | |
| STATIC INLINE void | IP_UART_SetAutoBaudReg (IP_USART_001_T *pUART, uint32_t acr) |
| Set autobaud register options. | |
| STATIC INLINE void | IP_UART_ClearAutoBaudReg (IP_USART_001_T *pUART, uint32_t acr) |
| Clear autobaud register options. | |
| STATIC INLINE void | IP_UART_TXEnable (IP_USART_001_T *pUART) |
| Enable transmission on UART TxD pin. | |
| STATIC INLINE void | IP_UART_TXDisable (IP_USART_001_T *pUART) |
| Disable transmission on UART TxD pin. | |
| STATIC INLINE void | IP_UART_SetRS485Flags (IP_USART_001_T *pUART, uint32_t ctrl) |
| Set RS485 control register options. | |
| STATIC INLINE void | IP_UART_ClearRS485Flags (IP_USART_001_T *pUART, uint32_t ctrl) |
| Clear RS485 control register options. | |
| STATIC INLINE void | IP_UART_SetRS485Addr (IP_USART_001_T *pUART, uint8_t addr) |
| Set RS485 address match value. | |
| STATIC INLINE uint8_t | IP_UART_GetRS485Addr (IP_USART_001_T *pUART) |
| Read RS485 address match value. | |
| STATIC INLINE void | IP_UART_SetRS485Delay (IP_USART_001_T *pUART, uint8_t dly) |
| Set RS485 direction control (RTS or DTR) delay value. | |
| STATIC INLINE uint8_t | IP_UART_GetRS485Delay (IP_USART_001_T *pUART) |
| Read RS485 direction control (RTS or DTR) delay value. | |
| uint32_t | IP_UART_SetBaud (IP_USART_001_T *pUART, uint32_t baudrate, uint32_t uClk) |
| Determines and sets best dividers to get a target bit rate. | |