RDC FPGA file for the EM7216 Receiver

Revision 2080

This does rounding of 16 bit data to 12 bit data for the nadir beam fix

Below was in rev 1080

This is derivered from the standard 7125 RDC FPGA

For incoming ceramic data the even channels are negated.

The caltone signal is passed through without change.
Note the caltone signal is equivalent to the C mux being set.