RDC FPGA bin file for Russian 7150 MNS system 

reg 2BA3

this is derived from rev 1B23 with the following change

every 25th channel is zero filled and the last 5 channels of the 144 are omitted

this is to accomodate the moidified receiver and avoid messy cabling

the comments following are from rev 1B23

single rack with 144 channels centered in a 288 channel packet and zero filled

BITE is not enabled but the rev can be read through debug board

The input RX timing is the same as in the 7111 DDS system