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adc_17xx_40xx.h
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1 /*
2 * @brief LPC17xx/40xx ADC conversion driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __ADC_17XX_40XX_H_
33 #define __ADC_17XX_40XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
43 #if defined(CHIP_LPC175X_6X)
44 #define ADC_MAX_SAMPLE_RATE 200000
45 #else
46 #define ADC_MAX_SAMPLE_RATE 400000
47 #endif
48
52 typedef enum CHIP_ADC_CHANNEL {
53 ADC_CH0 = 0,
54 ADC_CH1,
55 ADC_CH2,
56 ADC_CH3,
57 ADC_CH4,
58 ADC_CH5,
59 ADC_CH6,
60 ADC_CH7,
61 } CHIP_ADC_CHANNEL_T;
62
66 typedef enum CHIP_ADC_EDGE_CFG {
67 ADC_TRIGGERMODE_RISING = 0,
68 ADC_TRIGGERMODE_FALLING,
69 } CHIP_ADC_EDGE_CFG_T;
70
74 typedef enum CHIP_ADC_START_MODE {
75 ADC_NO_START = 0,
76 ADC_START_NOW,
77 ADC_START_ON_CTOUT15,
78 ADC_START_ON_CTOUT8,
79 ADC_START_ON_ADCTRIG0,
80 ADC_START_ON_ADCTRIG1,
81 ADC_START_ON_MCOA2
82 } CHIP_ADC_START_MODE_T;
83
87 typedef struct {
88 uint32_t adcRate;
89 uint8_t bitsAccuracy;
90 bool burstMode;
91 } ADC_Clock_Setup_T;
92
100 STATIC INLINE Status Chip_ADC_Read_Value(LPC_ADC_T *pADC, uint8_t channel, uint16_t *data)
101 {
102 return IP_ADC_Get_Val(pADC, channel, data);
103 }
104
112 STATIC INLINE FlagStatus Chip_ADC_Read_Status(LPC_ADC_T *pADC, uint8_t channel, uint32_t StatusType)
113 {
114 return IP_ADC_GetStatus(pADC, channel, StatusType);
115 }
116
124 STATIC INLINE void Chip_ADC_Channel_Int_Cmd(LPC_ADC_T *pADC, uint8_t channel, FunctionalState NewState)
125 {
126 IP_ADC_Int_Enable(pADC, channel, NewState);
127 }
128
135 STATIC INLINE void Chip_ADC_Global_Int_Cmd(LPC_ADC_T *pADC, FunctionalState NewState)
136 {
137 IP_ADC_Int_Enable(pADC, 8, NewState);
138 }
139
145 void Chip_ADC_DeInit(LPC_ADC_T *pADC);
146
154 void Chip_ADC_Init(LPC_ADC_T *pADC, ADC_Clock_Setup_T *ADCSetup);
155
172 void Chip_ADC_Set_StartMode(LPC_ADC_T *pADC, CHIP_ADC_START_MODE_T mode, CHIP_ADC_EDGE_CFG_T EdgeOption);
173
181 void Chip_ADC_Set_SampleRate(LPC_ADC_T *pADC, ADC_Clock_Setup_T *ADCSetup, uint32_t rate);
182
192 void Chip_ADC_Channel_Enable_Cmd(LPC_ADC_T *pADC, CHIP_ADC_CHANNEL_T channel, FunctionalState NewState);
193
202 void Chip_ADC_Burst_Cmd(LPC_ADC_T *pADC, FunctionalState NewState);
203
211 Status Chip_ADC_Read_Byte(LPC_ADC_T *pADC, CHIP_ADC_CHANNEL_T channel, uint8_t *data);
212
217 #ifdef __cplusplus
218 }
219 #endif
220
221 #endif /* __ADC_17XX_40XX_H_ */