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ssp_17xx_40xx.h
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1 /*
2 * @brief LPC17xx/40xx SSP driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __SSP_17XX_40XX_H_
33 #define __SSP_17XX_40XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
44 /*
45 * @brief SSP clock format
46 */
47 typedef enum CHIP_SSP_CLOCK_FORMAT {
48 SSP_CLOCK_CPHA0_CPOL0 = (0 << 6),
49 SSP_CLOCK_CPHA0_CPOL1 = (1u << 6),
50 SSP_CLOCK_CPHA1_CPOL0 = (2u << 6),
51 SSP_CLOCK_CPHA1_CPOL1 = (3u << 6),
52 SSP_CLOCK_MODE0 = SSP_CLOCK_CPHA0_CPOL0,
53 SSP_CLOCK_MODE1 = SSP_CLOCK_CPHA1_CPOL0,
54 SSP_CLOCK_MODE2 = SSP_CLOCK_CPHA0_CPOL1,
55 SSP_CLOCK_MODE3 = SSP_CLOCK_CPHA1_CPOL1,
56 } CHIP_SSP_CLOCK_MODE_T;
57
58 /*
59 * @brief SSP frame format
60 */
61 typedef enum CHIP_SSP_FRAME_FORMAT {
62 SSP_FRAMEFORMAT_SPI = (0 << 4),
63 CHIP_SSP_FRAME_FORMAT_TI = (1u << 4),
64 SSP_FRAMEFORMAT_MICROWIRE = (2u << 4),
65 } CHIP_SSP_FRAME_FORMAT_T;
66
67 /*
68 * @brief Number of bits per frame
69 */
70 typedef enum CHIP_SSP_BITS {
71 SSP_BITS_4 = (3u << 0),
72 SSP_BITS_5 = (4u << 0),
73 SSP_BITS_6 = (5u << 0),
74 SSP_BITS_7 = (6u << 0),
75 SSP_BITS_8 = (7u << 0),
76 SSP_BITS_9 = (8u << 0),
77 SSP_BITS_10 = (9u << 0),
78 SSP_BITS_11 = (10u << 0),
79 SSP_BITS_12 = (11u << 0),
80 SSP_BITS_13 = (12u << 0),
81 SSP_BITS_14 = (13u << 0),
82 SSP_BITS_15 = (14u << 0),
83 SSP_BITS_16 = (15u << 0),
84 } CHIP_SSP_BITS_T;
85
86 /*
87 * @brief SSP config format
88 */
89 typedef struct SSP_ConfigFormat {
90 CHIP_SSP_BITS_T bits;
91 CHIP_SSP_CLOCK_MODE_T clockMode;
92 CHIP_SSP_FRAME_FORMAT_T frameFormat;
93 } SSP_ConfigFormat;
94
95 /*
96 * @brief SSP mode
97 */
98 typedef enum CHIP_SSP_MODE {
99 SSP_MODE_MASTER = (0 << 2),
100 SSP_MODE_SLAVE = (1u << 2),
101 } CHIP_SSP_MODE_T;
102
103 /*
104 * @brief SPI address
105 */
106 typedef struct {
107 uint8_t port;
108 uint8_t pin;
109 } SPI_Address_t;
110
111 /*
112 * @brief SSP data setup structure
113 */
114 typedef struct {
115 void *tx_data;
116 uint32_t tx_cnt;
117 void *rx_data;
118 uint32_t rx_cnt;
119 uint32_t length;
120 } Chip_SSP_DATA_SETUP_T;
121
124 #define SSP_CPHA_FIRST SSP_CR0_CPHA_FIRST
125 #define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND
126
128 /* There's no bug here!!!
129 * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
130 * That means the active clock is in HI state.
131 * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
132 * high between frames. That means the active clock is in LO state.
133 */
134 #define SSP_CPOL_HI SSP_CR0_CPOL_LO
135 #define SSP_CPOL_LO SSP_CR0_CPOL_HI
136
138 #define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN
139 #define SSP_MASTER_MODE SSP_CR1_MASTER_EN
140
152 STATIC INLINE FlagStatus Chip_SSP_GetStatus(LPC_SSP_T *pSSP, IP_SSP_STATUS_T Stat)
153 {
154 return IP_SSP_GetStatus(pSSP, Stat);
155 }
156
162 STATIC INLINE void Chip_SSP_Enable(LPC_SSP_T *pSSP)
163 {
164 IP_SSP_Enable(pSSP);
165 }
166
172 STATIC INLINE void Chip_SSP_Disable(LPC_SSP_T *pSSP)
173 {
174 IP_SSP_Disable(pSSP);
175 }
176
182 STATIC INLINE void Chip_SSP_DMA_Enable(LPC_SSP_T *pSSP)
183 {
184 IP_SSP_DMA_Enable(pSSP, SSP_DMA_BITMASK);
185 }
186
192 STATIC INLINE void Chip_SSP_DMA_Disable(LPC_SSP_T *pSSP)
193 {
194 IP_SSP_DMA_Disable(pSSP, SSP_DMA_BITMASK);
195 }
196
204 STATIC INLINE void Chip_SSP_EnableLoopBack(LPC_SSP_T *pSSP)
205 {
206 IP_SSP_EnableLoopBack(pSSP);
207 }
208
216 STATIC INLINE void Chip_SSP_DisableLoopBack(LPC_SSP_T *pSSP)
217 {
218 IP_SSP_DisableLoopBack(pSSP);
219 }
220
226 void Chip_SSP_Int_FlushData(LPC_SSP_T *pSSP);
227
235 Status Chip_SSP_Int_RWFrames8Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
236
244 Status Chip_SSP_Int_RWFrames16Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
245
257 uint32_t Chip_SSP_RWFrames_Blocking(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
258
269 uint32_t Chip_SSP_WriteFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len);
270
281 uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len);
282
288 void Chip_SSP_Init(LPC_SSP_T *pSSP);
289
296 void Chip_SSP_DeInit(LPC_SSP_T *pSSP);
297
304 void Chip_SSP_SetMaster(LPC_SSP_T *pSSP, bool master);
305
312 void Chip_SSP_SetBitRate(LPC_SSP_T *pSSP, uint32_t bitRate);
313
320 STATIC INLINE void Chip_SSP_SetFormat(LPC_SSP_T *pSSP, SSP_ConfigFormat *format)
321 {
322 IP_SSP_SetFormat(pSSP, format->bits, format->frameFormat, format->clockMode);
323 }
324
330 STATIC INLINE void Chip_SSP_Int_Enable(LPC_SSP_T *pSSP)
331 {
332 IP_SSP_Int_Enable(pSSP, SSP_TXIM);
333 }
334
340 STATIC INLINE void Chip_SSP_Int_Disable(LPC_SSP_T *pSSP)
341 {
342 IP_SSP_Int_Disable(pSSP, SSP_TXIM);
343 }
344
349 #ifdef __cplusplus
350 }
351 #endif
352
353 #endif /* __SSP_17XX_40XX_H_ */