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clock_18xx_43xx.h
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1 /*
2 * @brief LPC18xx/43xx clock driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licenser disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __CLOCK_18XX_43XX_H_
33 #define __CLOCK_18XX_43XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
66 /* Internal oscillator frequency */
67 #define CGU_IRC_FREQ (12000000)
68
69 #ifndef MAX_CLOCK_FREQ
70 #if defined(CHIP_LPC43XX)
71 #define MAX_CLOCK_FREQ (204000000)
72 #else
73 #define MAX_CLOCK_FREQ (180000000)
74 #endif
75 #endif /* MAX_CLOCK_FREQ */
76
81 void Chip_Clock_EnableCrystal(void);
82
87 void Chip_Clock_DisableCrystal(void);
88
100 uint32_t Chip_Clock_SetupMainPLLHz(CHIP_CGU_CLKIN_T Input, uint32_t MinHz, uint32_t DesiredHz, uint32_t MaxHz);
101
108 uint32_t Chip_Clock_SetupMainPLLMult(CHIP_CGU_CLKIN_T Input, uint32_t mult);
109
115 uint32_t Chip_Clock_GetMainPLLHz(void);
116
123 void Chip_Clock_DisableMainPLL(void);
124
130 void Chip_Clock_EnableMainPLL(void);
131
137 bool Chip_Clock_MainPLLLocked(void);
138
148 void Chip_Clock_SetDivider(CHIP_CGU_IDIV_T Divider, CHIP_CGU_CLKIN_T Input, uint32_t Divisor);
149
155 CHIP_CGU_CLKIN_T Chip_Clock_GetDividerSource(CHIP_CGU_IDIV_T Divider);
156
162 uint32_t Chip_Clock_GetDividerDivisor(CHIP_CGU_IDIV_T Divider);
163
171 uint32_t Chip_Clock_GetClockInputHz(CHIP_CGU_CLKIN_T input);
172
180 uint32_t Chip_Clock_GetBaseClocktHz(CHIP_CGU_BASE_CLK_T clock);
181
190 void Chip_Clock_SetBaseClock(CHIP_CGU_BASE_CLK_T BaseClock, CHIP_CGU_CLKIN_T Input, bool autoblocken, bool powerdn);
191
200 void Chip_Clock_GetBaseClockOpts(CHIP_CGU_BASE_CLK_T BaseClock, CHIP_CGU_CLKIN_T *Input, bool *autoblocken,
201 bool *powerdn);
202
208 CHIP_CGU_CLKIN_T Chip_Clock_GetBaseClock(CHIP_CGU_BASE_CLK_T BaseClock);
209
215 void Chip_Clock_EnableBaseClock(CHIP_CGU_BASE_CLK_T BaseClock);
216
222 void Chip_Clock_DisableBaseClock(CHIP_CGU_BASE_CLK_T BaseClock);
223
229 bool Chip_Clock_IsBaseClockEnabled(CHIP_CGU_BASE_CLK_T BaseClock);
230
239 void Chip_Clock_EnableOpts(CHIP_CCU_CLK_T clk, bool autoen, bool wakeupen, int div);
240
246 void Chip_Clock_Enable(CHIP_CCU_CLK_T clk);
247
253 void Chip_Clock_Disable(CHIP_CCU_CLK_T clk);
254
260 uint32_t Chip_Clock_GetRate(CHIP_CCU_CLK_T clk);
261
268 void Chip_Clock_StartPowerDown(void);
269
276 void Chip_Clock_ClearPowerDown(void);
277
281 typedef struct {
282 uint32_t ctrl; /* Default control word for PLL */
283 uint32_t mdiv; /* Default M-divider value for PLL */
284 uint32_t ndiv; /* Default NP-divider value for PLL */
285 uint32_t fract; /* Default fractional value for audio PLL only */
286 } CGU_USBAUDIO_PLL_SETUP_T;
287
296 void Chip_Clock_SetupPLL(CHIP_CGU_CLKIN_T Input, CHIP_CGU_USB_AUDIO_PLL_T pllnum,
297 const CGU_USBAUDIO_PLL_SETUP_T *pPLLSetup);
298
304 void Chip_Clock_EnablePLL(CHIP_CGU_USB_AUDIO_PLL_T pllnum);
305
311 void Chip_Clock_DisablePLL(CHIP_CGU_USB_AUDIO_PLL_T pllnum);
312
313 #define CGU_PLL_LOCKED (1 << 0) /* PLL locked status */
314 #define CGU_PLL_FR (1 << 1) /* PLL free running indicator status */
315
321 uint32_t Chip_Clock_GetPLLStatus(CHIP_CGU_USB_AUDIO_PLL_T pllnum);
322
327 #ifdef __cplusplus
328 }
329 #endif
330
331 #endif /* __CLOCK_18XX_43XX_H_ */