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IP_TIMER_001_T Struct Reference
IP: Timer register block and driver

## Detailed Description

32-bit Standard timer register block structure

Definition at line 50 of file timer_001.h.

`#include "timer_001.h"`

## Data Fields
__IO uint32_t | IR
__IO uint32_t | TCR
__IO uint32_t | TC
__IO uint32_t | PR
__IO uint32_t | PC
__IO uint32_t | MCR
__IO uint32_t | MR [4]
__IO uint32_t | CCR
__IO uint32_t | CR [4]
__IO uint32_t | EMR
__I uint32_t | RESERVED0 [12]
__IO uint32_t | CTCR

## Field Documentation

__IO uint32_t CCR

Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.

Definition at line 58 of file timer_001.h.

__IO uint32_t CR[4]

Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input.

Definition at line 59 of file timer_001.h.

__IO uint32_t CTCR

Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.

Definition at line 62 of file timer_001.h.

__IO uint32_t EMR

External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively).

Definition at line 60 of file timer_001.h.

__IO uint32_t IR

< TIMERn Structure Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.

Definition at line 51 of file timer_001.h.

__IO uint32_t MCR

Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.

Definition at line 56 of file timer_001.h.

__IO uint32_t MR[4]

Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.

Definition at line 57 of file timer_001.h.

__IO uint32_t PC

Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.

Definition at line 55 of file timer_001.h.

__IO uint32_t PR

Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.

Definition at line 54 of file timer_001.h.

__I uint32_t RESERVED0[12]

Definition at line 61 of file timer_001.h.

__IO uint32_t TC

Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.

Definition at line 53 of file timer_001.h.

__IO uint32_t TCR

Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.

Definition at line 52 of file timer_001.h.

The documentation for this struct was generated from the following file:

- C:/nxp/v1.03/lpcopen_v1.03/lpcopen/software/lpc_core/lpc_ip/timer_001.h