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Endpoint_LPC18xx.h
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1 /*
2 * @brief USB Endpoint definitions for the LPC18xx microcontrollers
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
65 #ifndef __ENDPOINT_LPC18XX_H__
66 #define __ENDPOINT_LPC18XX_H__
67
68 #include "../EndpointCommon.h"
69
70 /* Enable C linkage for C++ Compilers: */
71 #if defined(__cplusplus)
72 extern "C" {
73 #endif
74
75 /* Preprocessor Checks: */
76 #if !defined(__INCLUDE_FROM_USB_DRIVER)
77 #error Do not include this file directly. Include lpcroot/libraries/LPCUSBlib/Drivers/USB/USB.h instead.
78 #endif
79
80 /* Private Interface - For use in library only: */
81 #if !defined(__DOXYGEN__)
82 /* Macros: */
83 #define ENDPOINT_DETAILS_MAXEP0 6
84 #define ENDPOINT_DETAILS_MAXEP1 4
85
86 #if defined(USB_DEVICE_ROM_DRIVER)
87 /*==========================================================================*/
88 /* USB ROM DRIVER DEFINITIONS */
89
90 /* A table of pointers to the chip's main ROM functions contained in ROM is located at the
91 address contained at this location */
92 typedef struct _ROM {
93 const unsigned p_otp;
94 const unsigned p_aes;
95 const unsigned p_pwd;
96 const unsigned p_clk;
97 const unsigned p_ipc;
98 const unsigned p_spifi;
99 const unsigned p_usbd;
100 } ROM_FUNCTION_TABLE;
101
102 /* A table of pointers to the USBD functions contained in ROM is located at the
103 address contained at this location */
104 #define ROM_FUNCTION_TABLE_PTR_ADDR (0x10400104UL)
105 #define ROM_USBD_PTR (((ROM_FUNCTION_TABLE *) (ROM_FUNCTION_TABLE_PTR_ADDR))->p_usbd)
106
107 #define ROMDRIVER_USB0_BASE LPC_USB0_BASE
108 #define ROMDRIVER_USB1_BASE LPC_USB1_BASE
109 #define ROMDRIVER_MEM_SIZE 0x1000
110 extern uint8_t usb_RomDriver_buffer[ROMDRIVER_MEM_SIZE];
111
112 #define ROMDRIVER_MSC_MEM_SIZE 0x1000
113 extern uint8_t usb_RomDriver_MSC_buffer[ROMDRIVER_MSC_MEM_SIZE];
114
115 #define ROMDRIVER_CDC_MEM_SIZE 0x800
116 extern uint8_t usb_RomDriver_CDC_buffer[ROMDRIVER_CDC_MEM_SIZE];
117 #define ROMDRIVER_CDC_DATA_BUFFER_SIZE 640
118 #if (USB_FORCED_FULLSPEED)
119 #define CDC_MAX_BULK_EP_SIZE 64
120 #else
121 #define CDC_MAX_BULK_EP_SIZE 512
122 #endif
123 extern uint8_t UsbdCdc_EPIN_buffer[CDC_MAX_BULK_EP_SIZE];
124 extern uint8_t UsbdCdc_EPOUT_buffer[CDC_MAX_BULK_EP_SIZE];
125
126 #define ROMDRIVER_HID_MEM_SIZE 0x800
127 extern uint8_t usb_RomDriver_HID_buffer[ROMDRIVER_HID_MEM_SIZE];
128 /*==========================================================================*/
129 #endif
130
131 /*==========================================================================*/
132 /* DEVICE REGISTER DEFINITIONS */
133 /*==========================================================================*/
134 /*---------- USBCMD ----------*/
135 #define USBCMD_D_RunStop (1 << 0) /* Run or Stop */
136 #define USBCMD_D_Reset (1 << 1) /* Host Controller Reset */
137 #define USBCMD_D_SetupTripWire (1 << 13)
138 #define USBCMD_D_AddTDTripWire (1 << 14)
139 #define USBCMD_D_IntThreshold (0xff << 16)
140
141 /*---------- USBSTS ----------*/
142 #define USBSTS_D_UsbInt 0x00000001UL /* USB Interrupt */
143 #define USBSTS_D_UsbErrorInt 0x00000002UL /* USB Error Interrupt */
144 #define USBSTS_D_PortChangeDetect 0x00000004UL /* Port Change Detect */
145 #define USBSTS_D_ResetReceived (1 << 6)
146 #define USBSTS_D_SofReceived (1 << 7)
147 #define USBSTS_D_SuspendInt (1 << 8)
148 #define USBSTS_D_NAK (1 << 16)
149
150 /*---------- USBINTR ----------*/
151 #define USBINTR_D_UsbIntEnable (1 << 0)
152 #define USBINTR_D_UsbErrorIntEnable (1 << 1)
153 #define USBINTR_D_PortChangeIntEnable (1 << 2)
154 #define USBINTR_D_UsbResetEnable (1 << 6)
155 #define USBINTR_D_SofReceivedEnable (1 << 7)
156 #define USBINTR_D_SuspendEnable (1 << 8)
157 #define USBINTR_D_NAKEnable (1 << 16)
158
159 /*---------- DEVICEADDR ----------*/
160 #define DEVICEADDR_AddressAdvance (1 << 24)
161 #define DEVICEADDR_DeviceAddr (0xff << 25)
162
163 /*---------- ENDPTNAK ----------*/
164 #define ENDPTNAK_RX (0x3f)
165 #define ENDPTNAK_TX (0x3f << 16)
166
167 /*---------- ENDPTNAKEN ----------*/
168 #define ENDPTNAKEN_RX (0x3f)
169 #define ENDPTNAKEN_TX (0x3f << 16)
170
171 /*---------- PORTSC ----------*/
172 #define PORTSC_D_CurrentConnectStatus 0x00000001UL /* Current Connect Status */
173 #define PORTSC_D_ForcePortResume 0x00000040UL /* Force Port Resume */
174 #define PORTSC_D_PortSuspend 0x00000080UL /* Port Suspend */
175 #define PORTSC_D_PortReset 0x00000100UL /* Port Reset */
176 #define PORTSC_D_HighSpeedStatus 0x00000200UL /* Line Status */
177 #define PORTSC_D_PortIndicatorControl 0x0000C000UL /* Port Indicator Control */
178 #define PORTSC_D_PortTestControl 0x000F0000UL /* Port Test Control */
179 #define PORTSC_D_PhyClockDisable 0x00800000UL /* PHY Clock Disable - EHCI derivation */
180 #define PORTSC_D_PortForceFullspeedConnect 0x01000000UL /* Force Device on Fullspeed mode (disable chirp sequences) - EHCI derivation */
181 #define PORTSC_D_PortSpeed 0x0C000000UL /* Device Speed - EHCI derivation */
182
183 /*---------- USBMODE_D ----------*/
184 /*---------- ENDPSETUPSTAT ----------*/
185
186 /*---------- ENDPTPRIME ----------*/
187 #define ENDPTPRIME_RX (0x3f)
188 #define ENDPTPRIME_TX (0x3f << 16)
189
190 /*---------- ENDPTFLUSH ----------*/
191 #define ENDPTFLUSH_RX (0x3f)
192 #define ENDPTFLUSH_TX (0x3f << 16)
193
194 /*---------- ENDPTSTAT ----------*/
195 #define ENDPTSTAT_RX (0x3f)
196 #define ENDPTSTAT_TX (0x3f << 16)
197
198 /*---------- ENDPTCOMPLETE ----------*/
199 #define ENDPTCOMPLETE_RX (0x3f)
200 #define ENDPTCOMPLETE_TX (0x3f << 16)
201
202 /*---------- ENDPTCTRL ----------*/
203 #define ENDPTCTRL_RxStall (1)
204 #define ENDPTCTRL_RxType (3 << 2)
205 #define ENDPTCTRL_RxToggleInhibit (1 << 5)
206 #define ENDPTCTRL_RxToggleReset (1 << 6)
207 #define ENDPTCTRL_RxEnable (1 << 7)
208
209 #define ENDPTCTRL_TxStall (1 << 16)
210 #define ENDPTCTRL_TxType (3 << 18)
211 #define ENDPTCTRL_TxToggleInhibit (1 << 21)
212 #define ENDPTCTRL_TxToggleReset (1 << 22)
213 #define ENDPTCTRL_TxEnable (1 << 23)
214 #define ENDPTCTRL_REG(corenum, LogicalAddr) ( ((__IO uint32_t *) &(USB_REG(corenum)->ENDPTCTRL[0]))[ \
215 LogicalAddr] )
216 #define EP_Physical2Logical(n) ((n) / 2)
217 /* Total physical endpoints*/
218 #define USED_PHYSICAL_ENDPOINTS0 ENDPOINT_DETAILS_MAXEP0 * 2 /* This macro effect memory size of the DCD */
219 #define USED_PHYSICAL_ENDPOINTS1 ENDPOINT_DETAILS_MAXEP1 * 2 /* This macro effect memory size of the DCD */
220 #define USED_PHYSICAL_ENDPOINTS(corenum) ((corenum) ? USED_PHYSICAL_ENDPOINTS1 : USED_PHYSICAL_ENDPOINTS0) /* This macro effect memory size of the DCD */
221 #define EP_Physical2BitPosition(n) ( EP_Physical2Logical(n) + ((n) % 2 ? 16 : 0 ) )
222 // #define LINK_TERMINATE 1
223
224 /*---------- Device TD ----------*/
225 typedef struct {
226 /*---------- Word 1 ----------*/
227 uint32_t NextTD;
228
229 /*---------- Word 2 ----------*/
230 uint32_t : 3;
231 __IO uint32_t TransactionErr : 1;
232 uint32_t : 1;
233 __IO uint32_t BufferErr : 1;
234 __IO uint32_t Halted : 1;
235 __IO uint32_t Active : 1;
236 uint32_t : 2;
237 uint32_t MultiplierOverride : 2;
238 uint32_t : 3;
239 __IO uint32_t IntOnComplete : 1;
240 __IO uint32_t TotalBytes : 15;
241 uint32_t : 0; /* force next member alinged on the next word */
242
243 /*---------- Word 3 - 7 ----------*/
244 uint32_t BufferPage[5];
245
246 uint32_t reserved;
247 } DeviceTransferDescriptor, *PDeviceTransferDescriptor;
248
249 /*---------- Device Qhd ----------*/
250 typedef struct {
251 /*---------- Word 1: Capability/Characteristics ----------*/
252 uint32_t : 15;
253 __IO uint32_t IntOnSetup : 1;
254 uint32_t MaxPacketSize : 11;
255 uint32_t : 2;
256 __IO uint32_t ZeroLengthTermination : 1;
257 uint32_t Mult : 2;
258 uint32_t : 0;
259
260 /*---------- Word 2 ----------*/
261 uint32_t currentTD;
262
263 /*---------- Word 3 - 10 ----------*/
264 __IO DeviceTransferDescriptor overlay;
265
266 /*---------- Word 11-12 ----------*/
267 __IO uint8_t SetupPackage[8];
268
269 uint16_t TransferCount;
270 __IO uint16_t IsOutReceived; // === TODO: IsOutReceived should be refractor to QueueHead Status ===
271 uint16_t reserved[6];
272 } DeviceQueueHead, *PDeviceQueueHead;
273
274 extern volatile DeviceQueueHead * const dQueueHead[];
275 extern DeviceTransferDescriptor * const dTransferDescriptor[];
276
277 void DcdDataTransfer(uint8_t corenum, uint8_t EPNum, uint8_t *pData, uint32_t cnt);
278
279 void Endpoint_Streaming(uint8_t corenum, uint8_t *buffer, uint16_t packetsize,
280 uint16_t totalpackets, uint16_t dummypackets);
281
282 /* Inline Functions: */
283
284 /* Function Prototypes: */
285 void Endpoint_ClearEndpoints(uint8_t corenum);
286
287 bool Endpoint_ConfigureEndpoint_Prv(uint8_t corenum,
288 const uint8_t Number,
289 const uint8_t UECFG0XData,
290 const uint8_t UECFG1XData);
291
292 #endif
293
294 /* Inline Functions: */
315 /*static inline */ bool Endpoint_ConfigureEndpoint(uint8_t corenum,
316 const uint8_t Number,
317 const uint8_t Type,
318 const uint8_t Direction,
319 const uint16_t Size,
320 const uint8_t Banks) /*ATTR_ALWAYS_INLINE*/;
321
322 // static inline bool Endpoint_ConfigureEndpoint(const uint8_t Number,
323 // const uint8_t Type,
324 // const uint8_t Direction,
325 // const uint16_t Size,
326 // const uint8_t Banks)
327 // {
328 // endpointhandle[Number] = HAL17XX_ConfigureEndpoint(Number,Type,Direction,Size,Banks);
329 // return true;
330 // }
331
339 static inline void Endpoint_ResetEndpoint(const uint8_t EndpointNumber) ATTR_ALWAYS_INLINE;
340
341 static inline void Endpoint_ResetEndpoint(const uint8_t EndpointNumber)
342 {}
343
351 static inline void Endpoint_EnableEndpoint(void) ATTR_ALWAYS_INLINE;
352
353 static inline void Endpoint_EnableEndpoint(void)
354 {}
355
361 static inline void Endpoint_DisableEndpoint(void) ATTR_ALWAYS_INLINE;
362
363 static inline void Endpoint_DisableEndpoint(void)
364 {}
365
370 static inline bool Endpoint_IsEnabled(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;
371
372 static inline bool Endpoint_IsEnabled(void)
373 {
374 return true;
375 }
376
386 static inline uint8_t Endpoint_GetBusyBanks(void) ATTR_ALWAYS_INLINE ATTR_WARN_UNUSED_RESULT;
387
388 static inline uint8_t Endpoint_GetBusyBanks(void)
389 {
390 return 0;
391 }
392
401 static inline void Endpoint_AbortPendingIN(void)
402 {}
403
409 static inline bool Endpoint_IsConfigured(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;
410
411 static inline bool Endpoint_IsConfigured(void)
412 {
413 // return ((UESTA0X & (1 << CFGOK)) ? true : false);
414 return true;
415 }
416
424 static inline uint8_t Endpoint_GetEndpointInterrupts(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;
425
426 static inline uint8_t Endpoint_GetEndpointInterrupts(void)
427 {
428 return 0; // TODO not yet implemented
429 }
430
437 static inline bool Endpoint_HasEndpointInterrupted(const uint8_t EndpointNumber) ATTR_WARN_UNUSED_RESULT
438 ATTR_ALWAYS_INLINE;
439
440 static inline bool Endpoint_HasEndpointInterrupted(const uint8_t EndpointNumber)
441 {
442 return (Endpoint_GetEndpointInterrupts() & (1 << EndpointNumber)) ? true : false;
443 }
444
456 static inline uint16_t Endpoint_BytesInEndpoint(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;
457
458 static inline uint16_t Endpoint_BytesInEndpoint(uint8_t corenum)
459 {
460 // return usb_data_buffer_index; // TODO not implemented yet
461 // uint8_t PhyEP = (endpointselected==ENDPOINT_CONTROLEP ? 1: endpointhandle[endpointselected]);
462 if (endpointselected[corenum] == ENDPOINT_CONTROLEP) {
463 return usb_data_buffer_size[corenum];
464 }
465 else {
466 return usb_data_buffer_OUT_size[corenum];
467 }
468 }
469
478 static inline bool Endpoint_IsINReady(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;
479
480 static inline bool Endpoint_IsINReady(uint8_t corenum)
481 {
482 uint8_t PhyEP = (endpointselected[corenum] == ENDPOINT_CONTROLEP ? 1 : endpointhandle(corenum)[endpointselected[corenum]]);
483 return (dQueueHead[corenum][PhyEP].overlay.NextTD & LINK_TERMINATE) &&
484 (dQueueHead[corenum][PhyEP].overlay.Active == 0);
485 }
486
495 static inline bool Endpoint_IsOUTReceived(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;
496
497 static inline bool Endpoint_IsOUTReceived(uint8_t corenum)
498 {
499 // return (dQueueHead[ endpointhandle[endpointselected] ].overlay.NextTD == LINK_TERMINATE &&
500 // dQueueHead[ endpointhandle[endpointselected] ].overlay.Active == 0 );
501 return dQueueHead[corenum][endpointhandle(corenum)[endpointselected[corenum]]].IsOutReceived ? true : false; // TODO refractor IsOutReceived
502 }
503
512 static inline bool Endpoint_IsSETUPReceived(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;
513
514 static inline bool Endpoint_IsSETUPReceived(uint8_t corenum)
515 {
516 return USB_REG(corenum)->ENDPTSETUPSTAT ? true : false;
517 }
518
529 static inline void Endpoint_ClearSETUP(uint8_t corenum) ATTR_ALWAYS_INLINE;
530
531 static inline void Endpoint_ClearSETUP(uint8_t corenum)
532 {
533 IP_USBHS_001_T * USB_Reg = USB_REG(corenum);
534 USB_Reg->ENDPTSETUPSTAT = USB_Reg->ENDPTSETUPSTAT;
535 usb_data_buffer_index[corenum] = 0;
536 USB_Reg->ENDPTNAKEN |= (1 << 0);
537 }
538
547 static inline void Endpoint_ClearIN(uint8_t corenum) ATTR_ALWAYS_INLINE;
548
549 static inline void Endpoint_ClearIN(uint8_t corenum)
550 {
551 uint8_t PhyEP = endpointselected[corenum] == ENDPOINT_CONTROLEP ? 1 : (endpointhandle(corenum)[endpointselected[corenum]]);
552 if (endpointselected[corenum] == ENDPOINT_CONTROLEP) {
553 DcdDataTransfer(corenum, PhyEP, (uint8_t *)usb_data_buffer[corenum], usb_data_buffer_index[corenum]);
554 usb_data_buffer_index[corenum] = 0;
555 }
556 else {
557 DcdDataTransfer(corenum, PhyEP, usb_data_buffer_IN[corenum], usb_data_buffer_IN_index[corenum]);
558 usb_data_buffer_IN_index[corenum] = 0;
559 }
560 }
561
570 static inline void Endpoint_ClearOUT(uint8_t corenum) ATTR_ALWAYS_INLINE;
571
572 static inline void Endpoint_ClearOUT(uint8_t corenum)
573 {
574 if (endpointselected[corenum] == ENDPOINT_CONTROLEP) {
575 usb_data_buffer_index[corenum] = 0;
576 dQueueHead[corenum][endpointhandle(corenum)[endpointselected[corenum]]].IsOutReceived = 0;
577 }
578 else {
579 usb_data_buffer_OUT_index[corenum] = 0;
580 dQueueHead[corenum][endpointhandle(corenum)[endpointselected[corenum]]].IsOutReceived = 0;
581 USB_REG(corenum)->ENDPTNAKEN |= (1 << endpointselected[corenum]);
582 }
583
584 }
585
600 static inline void Endpoint_StallTransaction(uint8_t corenum) ATTR_ALWAYS_INLINE;
601
602 static inline void Endpoint_StallTransaction(uint8_t corenum)
603 {
604 ENDPTCTRL_REG(corenum, EP_Physical2Logical(endpointhandle(corenum)[endpointselected[corenum]]) ) |= ENDPTCTRL_RxStall | ENDPTCTRL_TxStall;
605 }
606
614 static inline void Endpoint_ClearStall(uint8_t corenum) ATTR_ALWAYS_INLINE;
615
616 static inline void Endpoint_ClearStall(uint8_t corenum)
617 {
618 // === TODO: Only clear stall correct endpoint ===
619 ENDPTCTRL_REG(corenum, EP_Physical2Logical(endpointhandle(corenum)[endpointselected[corenum]]) ) &= ~(ENDPTCTRL_RxStall | ENDPTCTRL_TxStall);
620 }
621
630 static inline bool Endpoint_IsStalled(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;
631
632 static inline bool Endpoint_IsStalled(uint8_t corenum)
633 {
634 return ENDPTCTRL_REG(corenum, EP_Physical2Logical(endpointhandle(corenum)[endpointselected[corenum]]) ) &
635 (ENDPTCTRL_RxStall | ENDPTCTRL_TxStall);
636 }
637
639 static inline void Endpoint_ResetDataToggle(uint8_t corenum) ATTR_ALWAYS_INLINE;
640
641 static inline void Endpoint_ResetDataToggle(uint8_t corenum)
642 {
643 ENDPTCTRL_REG(corenum, EP_Physical2Logical(endpointhandle(corenum)[endpointselected[corenum]]) ) |= ENDPTCTRL_RxToggleReset |
644 ENDPTCTRL_TxToggleReset;
645 }
646
647 /* External Variables: */
663 #if (!defined(FIXED_CONTROL_ENDPOINT_SIZE) || defined(__DOXYGEN__))
664 extern uint8_t USB_Device_ControlEndpointSize;
665 #else
666 #define USB_Device_ControlEndpointSize FIXED_CONTROL_ENDPOINT_SIZE
667 #endif
668
669 /* Function Prototypes: */
677 void Endpoint_ClearStatusStage(uint8_t corenum);
678
689 uint8_t Endpoint_WaitUntilReady(void);
690
691 /* Disable C linkage for C++ Compilers: */
692 #if defined(__cplusplus)
693 }
694 #endif
695
696 #endif
697