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Data Structures | Macros | Enumerations | Functions
IP: SPI register block and driver
IP drivers: Common drivers used on multiple NXP devices

## Detailed Description

## Data Structures
struct | IP_SPI_001_T
| SPI register block structure. More...

## Macros
#define | SPI_CR_BITMASK ((uint32_t) 0xFFC)
#define | SPI_CR_BIT_EN ((uint32_t) (1 << 2))
#define | SPI_CR_BITS_MASK ((uint32_t) 0xF00)
#define | SPI_CR_BITS(n) ((uint32_t) ((n << 8) & 0xF00)) /* n is in range 8-16 */
#define | SPI_CR_CPHA_FIRST ((uint32_t) (0)) /*Capture data on the first edge, Change data on the following edge*/
#define | SPI_CR_CPHA_SECOND ((uint32_t) (1 << 3)) /*Change data on the first edge, Capture data on the following edge*/
#define | SPI_CR_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/
#define | SPI_CR_CPOL_HI ((uint32_t) (1 << 4)) /* The rest state of the clock (between frames) is high.*/
#define | SPI_CR_SLAVE_EN ((uint32_t) 0)
#define | SPI_CR_MASTER_EN ((uint32_t) (1 << 5))
#define | SPI_CR_MSB_FIRST_EN ((uint32_t) 0) /*Data will be transmitted and received in standard order (MSB first).*/
#define | SPI_CR_LSB_FIRST_EN ((uint32_t) (1 << 6)) /*Data will be transmitted and received in reverse order (LSB first).*/
#define | SPI_CR_INT_EN ((uint32_t) (1 << 7))
#define | SPI_SR_BITMASK ((uint32_t) 0xF8)
#define | SPI_SR_ABRT ((uint32_t) (1 << 3)) /* When 1, this bit indicates that a slave abort has occurred. */
#define | SPI_SR_MODF ((uint32_t) (1 << 4)) /* when 1, this bit indicates that a Mode fault error has occurred. */
#define | SPI_SR_ROVR ((uint32_t) (1 << 5)) /* When 1, this bit indicates that a read overrun has occurred. */
#define | SPI_SR_WCOL ((uint32_t) (1 << 6)) /* When 1, this bit indicates that a write collision has occurred.. */
#define | SPI_SR_SPIF ((uint32_t) (1 << 7)) /* When 1, this bit indicates when a SPI data transfer is complete.. */
#define | SPI_SR_ERROR (SPI_SR_ABRT | SPI_SR_MODF | SPI_SR_ROVR | SPI_SR_WCOL)
#define | SPI_TCR_TEST(n) ((uint32_t) ((n & 0x3F) << 1))
#define | SPI_INT_SPIF ((uint32_t) (1 << 0))
#define | SPI_DR_DATA(n) ((uint32_t) ((n) & 0xFFFF))

## Enumerations
enum | IP_SPI_MODE_T { SPI_MODE_MASTER = SPI_CR_MASTER_EN, SPI_MODE_SLAVE = SPI_CR_SLAVE_EN, SPI_MODE_MASTER = SPI_CFG_MASTER_EN, SPI_MODE_SLAVE = SPI_CFG_SLAVE_EN }
| SPI Mode. More...
enum | IP_SPI_CLOCK_MODE_T { SPI_CLOCK_CPHA0_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_FIRST, SPI_CLOCK_CPHA0_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_FIRST, SPI_CLOCK_CPHA1_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_SECOND, SPI_CLOCK_CPHA1_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_SECOND, SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0, SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0, SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1, SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1, SPI_CLOCK_CPHA0_CPOL0 = SPI_CFG_CPOL_LO | SPI_CFG_CPHA_FIRST, SPI_CLOCK_CPHA0_CPOL1 = SPI_CFG_CPOL_HI | SPI_CFG_CPHA_FIRST, SPI_CLOCK_CPHA1_CPOL0 = SPI_CFG_CPOL_LO | SPI_CFG_CPHA_SECOND, SPI_CLOCK_CPHA1_CPOL1 = SPI_CFG_CPOL_HI | SPI_CFG_CPHA_SECOND, SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0, SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0, SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1, SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1 }
| SPI Clock Mode. More...
enum | IP_SPI_DATA_ORDER_T { SPI_DATA_MSB_FIRST = SPI_CR_MSB_FIRST_EN, SPI_DATA_LSB_FIRST = SPI_CR_LSB_FIRST_EN, SPI_DATA_MSB_FIRST = SPI_CFG_MSB_FIRST_EN, SPI_DATA_LSB_FIRST = SPI_CFG_LSB_FIRST_EN }
| SPI Data Order Mode. More...
enum | IP_SPI_BITS_T { SPI_BITS_8 = SPI_CR_BITS(8), SPI_BITS_9 = SPI_CR_BITS(9), SPI_BITS_10 = SPI_CR_BITS(10), SPI_BITS_11 = SPI_CR_BITS(11), SPI_BITS_12 = SPI_CR_BITS(12), SPI_BITS_13 = SPI_CR_BITS(13), SPI_BITS_14 = SPI_CR_BITS(14), SPI_BITS_15 = SPI_CR_BITS(15), SPI_BITS_16 = SPI_CR_BITS(16) }

## Functions
STATIC INLINE uint32_t | IP_SPI_GetStatus (IP_SPI_001_T *pSPI)
| Get the current status of SPI controller.
STATIC INLINE void | IP_SPI_IntEnable (IP_SPI_001_T *pSPI)
| Enable the interrupt for the SPI.
STATIC INLINE void | IP_SPI_IntDisable (IP_SPI_001_T *pSPI)
| Disable the interrupt for the SPI.
STATIC INLINE uint32_t | IP_SPI_GetIntStatus (IP_SPI_001_T *pSPI)
| Get the interrupt status.
STATIC INLINE void | IP_SPI_ClearIntStatus (IP_SPI_001_T *pSPI, uint32_t mask)
| Clear the interrupt status.
STATIC INLINE void | IP_SPI_SendFrame (IP_SPI_001_T *pSPI, uint16_t data)
| Send SPI 16-bit data.
STATIC INLINE uint16_t | IP_SPI_ReceiveFrame (IP_SPI_001_T *pSPI)
| Get received SPI data.
STATIC INLINE void | IP_SPI_SetClockCounter (IP_SPI_001_T *pSPI, uint32_t counter)
| Set up output clocks per bit for SPI bus.
STATIC INLINE void | IP_SPI_SetFormat (IP_SPI_001_T *pSPI, IP_SPI_BITS_T bits, IP_SPI_CLOCK_MODE_T clockMode, IP_SPI_DATA_ORDER_T order)
| Set up the SPI frame format.
STATIC INLINE IP_SPI_BITS_T | IP_SPI_GetDataSize (IP_SPI_001_T *pSPI)
| Get the number of bits transferred in each frame.
STATIC INLINE IP_SPI_CLOCK_MODE_T | IP_SPI_GetClockMode (IP_SPI_001_T *pSPI)
| Get the current CPHA & CPOL setting.
STATIC INLINE void | IP_SPI_SetMode (IP_SPI_001_T *pSPI, IP_SPI_MODE_T mode)
| Set the SPI working as master or slave mode.
STATIC INLINE IP_SPI_MODE_T | IP_SPI_GetMode (IP_SPI_001_T *pSPI)
| Set the SPI working as master or slave mode.

## Macro Definition Documentation

#define SPI_CR_BIT_EN ((uint32_t) (1 << 2))

Enable of controlling the number of bits per transfer

Definition at line 65 of file spi_001.h.

#define SPI_CR_BITMASK ((uint32_t) 0xFFC)

Definition at line 63 of file spi_001.h.

#define SPI_CR_BITS | ( |  | n | ) | ((uint32_t) ((n << 8) & 0xF00)) /* n is in range 8-16 */

Set the number of bits per a transfer

Definition at line 69 of file spi_001.h.

#define SPI_CR_BITS_MASK ((uint32_t) 0xF00)

Mask of field of bit controlling

Definition at line 67 of file spi_001.h.

#define SPI_CR_CPHA_FIRST ((uint32_t) (0)) /*Capture data on the first edge, Change data on the following edge*/

SPI Clock Phase Select

Definition at line 71 of file spi_001.h.

#define SPI_CR_CPHA_SECOND ((uint32_t) (1 << 3)) /*Change data on the first edge, Capture data on the following edge*/

Definition at line 72 of file spi_001.h.

#define SPI_CR_CPOL_HI ((uint32_t) (1 << 4)) /* The rest state of the clock (between frames) is high.*/

Definition at line 75 of file spi_001.h.

#define SPI_CR_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/

SPI Clock Polarity Select

Definition at line 74 of file spi_001.h.

#define SPI_CR_INT_EN ((uint32_t) (1 << 7))

SPI interrupt enable

Definition at line 85 of file spi_001.h.

#define SPI_CR_LSB_FIRST_EN ((uint32_t) (1 << 6)) /*Data will be transmitted and received in reverse order (LSB first).*/

SPI LSB First mode enable

Definition at line 83 of file spi_001.h.

#define SPI_CR_MASTER_EN ((uint32_t) (1 << 5))

SPI Master Mode Select

Definition at line 79 of file spi_001.h.

#define SPI_CR_MSB_FIRST_EN ((uint32_t) 0) /*Data will be transmitted and received in standard order (MSB first).*/

SPI MSB First mode enable

Definition at line 81 of file spi_001.h.

#define SPI_CR_SLAVE_EN ((uint32_t) 0)

SPI Slave Mode Select

Definition at line 77 of file spi_001.h.

#define SPI_DR_DATA | ( |  | n | ) | ((uint32_t) ((n) & 0xFFFF))

Macro defines for SPI Data registerReceiver Data

Definition at line 120 of file spi_001.h.

#define SPI_INT_SPIF ((uint32_t) (1 << 0))

SPI interrupt flag

Definition at line 114 of file spi_001.h.

#define SPI_SR_ABRT ((uint32_t) (1 << 3)) /* When 1, this bit indicates that a slave abort has occurred. */

Slave abort Flag

Definition at line 93 of file spi_001.h.

#define SPI_SR_BITMASK ((uint32_t) 0xF8)

SPI STAT Register BitMask

Definition at line 91 of file spi_001.h.

#define SPI_SR_ERROR (SPI_SR_ABRT | SPI_SR_MODF | SPI_SR_ROVR | SPI_SR_WCOL)

SPI error flag

Definition at line 103 of file spi_001.h.

#define SPI_SR_MODF ((uint32_t) (1 << 4)) /* when 1, this bit indicates that a Mode fault error has occurred. */

Definition at line 95 of file spi_001.h.

#define SPI_SR_ROVR ((uint32_t) (1 << 5)) /* When 1, this bit indicates that a read overrun has occurred. */

Read overrun flag

Definition at line 97 of file spi_001.h.

#define SPI_SR_SPIF ((uint32_t) (1 << 7)) /* When 1, this bit indicates when a SPI data transfer is complete.. */

SPI transfer complete flag.

Definition at line 101 of file spi_001.h.

#define SPI_SR_WCOL ((uint32_t) (1 << 6)) /* When 1, this bit indicates that a write collision has occurred.. */

Write collision flag.

Definition at line 99 of file spi_001.h.

#define SPI_TCR_TEST | ( |  | n | ) | ((uint32_t) ((n & 0x3F) << 1))

Definition at line 108 of file spi_001.h.

## Enumeration Type Documentation

enum IP_SPI_BITS_T

Enumerator:

  SPI_BITS_8 | 8 bits/frame
  SPI_BITS_9 | 9 bits/frame
  SPI_BITS_10 | 10 bits/frame
  SPI_BITS_11 | 11 bits/frame
  SPI_BITS_12 | 12 bits/frame
  SPI_BITS_13 | 13 bits/frame
  SPI_BITS_14 | 14 bits/frame
  SPI_BITS_15 | 15 bits/frame
  SPI_BITS_16 | 16 bits/frame

Definition at line 149 of file spi_001.h.

enum IP_SPI_CLOCK_MODE_T

SPI Clock Mode.

Enumerator:

  SPI_CLOCK_CPHA0_CPOL0 | CPHA = 0, CPOL = 0
  SPI_CLOCK_CPHA0_CPOL1 | CPHA = 0, CPOL = 1
  SPI_CLOCK_CPHA1_CPOL0 | CPHA = 1, CPOL = 0
  SPI_CLOCK_CPHA1_CPOL1 | CPHA = 1, CPOL = 1
  SPI_CLOCK_MODE0 | alias
  SPI_CLOCK_MODE1 | alias
  SPI_CLOCK_MODE2 | alias
  SPI_CLOCK_MODE3 | alias
  SPI_CLOCK_CPHA0_CPOL0 | CPHA = 0, CPOL = 0
  SPI_CLOCK_CPHA0_CPOL1 | CPHA = 0, CPOL = 1
  SPI_CLOCK_CPHA1_CPOL0 | CPHA = 1, CPOL = 0
  SPI_CLOCK_CPHA1_CPOL1 | CPHA = 1, CPOL = 1
  SPI_CLOCK_MODE0 | alias
  SPI_CLOCK_MODE1 | alias
  SPI_CLOCK_MODE2 | alias
  SPI_CLOCK_MODE3 | alias

Definition at line 129 of file spi_001.h.

enum IP_SPI_DATA_ORDER_T

SPI Data Order Mode.

Enumerator:

  SPI_DATA_MSB_FIRST |
  SPI_DATA_LSB_FIRST |
  SPI_DATA_MSB_FIRST |
  SPI_DATA_LSB_FIRST |

Definition at line 141 of file spi_001.h.

enum IP_SPI_MODE_T

SPI Mode.

Enumerator:

  SPI_MODE_MASTER |
  SPI_MODE_SLAVE |
  SPI_MODE_MASTER |
  SPI_MODE_SLAVE |

Definition at line 123 of file spi_001.h.

## Function Documentation

STATIC INLINE void IP_SPI_ClearIntStatus | ( | IP_SPI_001_T * | pSPI,
|  | uint32_t | mask
| ) |  |

Clear the interrupt status.

Parameters

  pSPI | : The base of SPI peripheral on the chip
  mask | : SPI interrupt mask (Or-ed bit value of SPI_INT_*)

Returns
  Nothing

Definition at line 208 of file spi_001.h.

STATIC INLINE IP_SPI_CLOCK_MODE_T IP_SPI_GetClockMode | ( | IP_SPI_001_T * | pSPI | ) |

Get the current CPHA & CPOL setting.

Parameters

  pSPI | : The base of SPI peripheral on the chip

Returns
  CPHA & CPOL setting

Definition at line 282 of file spi_001.h.

STATIC INLINE IP_SPI_BITS_T IP_SPI_GetDataSize | ( | IP_SPI_001_T * | pSPI | ) |

Get the number of bits transferred in each frame.

Parameters

  pSPI | : The base of SPI peripheral on the chip

Returns
  the number of bits transferred in each frame

Definition at line 272 of file spi_001.h.

STATIC INLINE uint32_t IP_SPI_GetIntStatus | ( | IP_SPI_001_T * | pSPI | ) |

Get the interrupt status.

Parameters

  pSPI | : The base of SPI peripheral on the chip

Returns
  SPI interrupt Status (Or-ed bit value of SPI_INT_*)

Definition at line 197 of file spi_001.h.

STATIC INLINE IP_SPI_MODE_T IP_SPI_GetMode | ( | IP_SPI_001_T * | pSPI | ) |

Set the SPI working as master or slave mode.

Parameters

  pSPI | : The base of SPI peripheral on the chip

Returns
  Operating mode

Definition at line 303 of file spi_001.h.

STATIC INLINE uint32_t IP_SPI_GetStatus | ( | IP_SPI_001_T * | pSPI | ) |

Get the current status of SPI controller.

Parameters

  pSPI | : The base of SPI peripheral on the chip

Returns
  SPI Status (Or-ed bit value of SPI_SR_*)

Note
  See user manual about how status bits are cleared.

Definition at line 167 of file spi_001.h.

STATIC INLINE void IP_SPI_IntDisable | ( | IP_SPI_001_T * | pSPI | ) |

Disable the interrupt for the SPI.

Parameters

  pSPI | : The base of SPI peripheral on the chip

Returns
  Nothing

Definition at line 187 of file spi_001.h.

STATIC INLINE void IP_SPI_IntEnable | ( | IP_SPI_001_T * | pSPI | ) |

Enable the interrupt for the SPI.

Parameters

  pSPI | : The base of SPI peripheral on the chip

Returns
  Nothing

Definition at line 177 of file spi_001.h.

STATIC INLINE uint16_t IP_SPI_ReceiveFrame | ( | IP_SPI_001_T * | pSPI | ) |

Get received SPI data.

Parameters

  pSPI | : The base of SPI peripheral on the chip

Returns
  receive data

Definition at line 229 of file spi_001.h.

STATIC INLINE void IP_SPI_SendFrame | ( | IP_SPI_001_T * | pSPI,
|  | uint16_t | data
| ) |  |

Send SPI 16-bit data.

Parameters

  pSPI | : The base of SPI peripheral on the chip
  data | : Transmit Data

Returns
  Nothing

Definition at line 219 of file spi_001.h.

STATIC INLINE void IP_SPI_SetClockCounter | ( | IP_SPI_001_T * | pSPI,
|  | uint32_t | counter
| ) |  |

Set up output clocks per bit for SPI bus.

Parameters

  pSPI | : The base of SPI peripheral on the chip
  counter | : the number of SPI peripheral clock cycles that make up an SPI clock

Returns
  Nothing

Note
  The counter must be an even number greater than or equal to 8.
  The SPI SCK rate = PCLK_SPI / counter.

Definition at line 242 of file spi_001.h.

STATIC INLINE void IP_SPI_SetFormat | ( | IP_SPI_001_T * | pSPI,
|  | IP_SPI_BITS_T | bits,
|  | IP_SPI_CLOCK_MODE_T | clockMode,
|  | IP_SPI_DATA_ORDER_T | order
| ) |  |

Set up the SPI frame format.

Parameters

  pSPI | : The base of SPI peripheral on the chip
  bits | : The number of bits transferred in each frame.
  clockMode | : Select Clock polarity and Clock phase, should be : SPI_CLOCK_CPHA0_CPOL0 SPI_CLOCK_CPHA0_CPOL1 SPI_CLOCK_CPHA1_CPOL0 SPI_CLOCK_CPHA1_CPOL1 or SPI_CLOCK_MODE*
  order | : Data order (MSB first/LSB first).

Returns
  Nothing

Note
  Note: The clockFormat is only used in SPI mode

Definition at line 261 of file spi_001.h.

STATIC INLINE void IP_SPI_SetMode | ( | IP_SPI_001_T * | pSPI,
|  | IP_SPI_MODE_T | mode
| ) |  |

Set the SPI working as master or slave mode.

Parameters

  pSPI | : The base of SPI peripheral on the chip
  mode | : Operating mode

Returns
  Nothing

Definition at line 293 of file spi_001.h.