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usart_004.h
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1 /*
2 * @brief UART/USART Registers and control functions
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __USART_004_H_
33 #define __USART_004_H_
34
35 #include "sys_config.h"
36 #include "cmsis.h"
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
50 typedef struct {
52 union {
53 __IO uint32_t DLL;
54 __O uint32_t THR;
55 __I uint32_t RBR;
56 };
57
58 union {
59 __IO uint32_t IER;
60 __IO uint32_t DLM;
61 };
62
63 union {
64 __O uint32_t FCR;
65 __I uint32_t IIR;
66 };
67
68 __IO uint32_t LCR;
69 __IO uint32_t MCR;
70 __I uint32_t LSR;
71 __I uint32_t MSR;
72 __IO uint32_t SCR;
73 __IO uint32_t ACR;
74 __IO uint32_t ICR;
75 __IO uint32_t FDR;
77 __IO uint32_t OSR;
78 __IO uint32_t TER1;
79 uint32_t RESERVED0[3];
80 __IO uint32_t HDEN;
81 __I uint32_t RESERVED1[1];
82 __IO uint32_t SCICTRL;
84 __IO uint32_t RS485CTRL;
85 __IO uint32_t RS485ADRMATCH;
86 __IO uint32_t RS485DLY;
88 union {
89 __IO uint32_t SYNCCTRL;
90 __I uint32_t FIFOLVL;
91 };
92
93 __IO uint32_t TER2;
94 } IP_USART_001_T;
95
96 #define UART_RBR_MASKBIT (0xFF)
104 void IP_UART_Init(IP_USART_001_T *pUART);
105
111 STATIC INLINE void IP_UART_DeInit(IP_USART_001_T *pUART) {}
112
121 STATIC INLINE void IP_UART_SendByte(IP_USART_001_T *pUART, const uint8_t data)
122 {
123 pUART->THR = (uint32_t) data;
124 }
125
133 STATIC INLINE uint8_t IP_UART_ReadByte(IP_USART_001_T *pUART)
134 {
135 return (uint8_t) (pUART->RBR & UART_RBR_MASKBIT);
136 }
137
141 #define UART_IER_RBRINT (1 << 0)
142 #define UART_IER_THREINT (1 << 1)
143 #define UART_IER_RLSINT (1 << 2)
144 #define UART_IER_MSINT (1 << 3)
145 #define UART_IER_CTSINT (1 << 7)
146 #define UART_IER_ABEOINT (1 << 8)
147 #define UART_IER_ABTOINT (1 << 9)
148 #define UART_IER_BITMASK (0x307)
149 #define UART1_IER_BITMASK (0x38F)
161 STATIC INLINE void IP_UART_IntEnable(IP_USART_001_T *pUART, uint32_t intMask)
162 {
163 pUART->IER |= intMask;
164 }
165
176 STATIC INLINE void IP_UART_IntDisable(IP_USART_001_T *pUART, uint32_t intMask)
177 {
178 pUART->IER &= ~intMask;
179 }
180
184 #define UART_IIR_INTSTAT_PEND (1 << 0)
185 #define UART_IIR_INTID_RLS (3 << 1)
186 #define UART_IIR_INTID_RDA (2 << 1)
187 #define UART_IIR_INTID_CTI (6 << 1)
188 #define UART_IIR_INTID_THRE (1 << 1)
189 #define UART_IIR_INTID_MODEM (0 << 1)
190 #define UART_IIR_INTID_MASK (7 << 1)
191 #define UART_IIR_FIFO_EN (3 << 6)
192 #define UART_IIR_ABEO_INT (1 << 8)
193 #define UART_IIR_ABTO_INT (1 << 9)
194 #define UART_IIR_BITMASK (0x3CF)
201 STATIC INLINE uint32_t IP_UART_ReadIntIDReg(IP_USART_001_T *pUART)
202 {
203 return pUART->IIR;
204 }
205
209 #define UART_FCR_FIFO_EN (1 << 0)
210 #define UART_FCR_RX_RS (1 << 1)
211 #define UART_FCR_TX_RS (1 << 2)
212 #define UART_FCR_DMAMODE_SEL (1 << 3)
213 #define UART_FCR_TRG_LEV0 (0)
214 #define UART_FCR_TRG_LEV1 (1 << 6)
215 #define UART_FCR_TRG_LEV2 (2 << 6)
216 #define UART_FCR_TRG_LEV3 (3 << 6)
217 #define UART_FCR_BITMASK (0xCF)
218 #define UART_TX_FIFO_SIZE (16)
219
228 STATIC INLINE void IP_UART_SetupFIFOS(IP_USART_001_T *pUART, uint32_t fcr)
229 {
230 pUART->FCR = fcr;
231 }
232
236 #define UART_LCR_WLEN5 (0)
237 #define UART_LCR_WLEN6 (1 << 0)
238 #define UART_LCR_WLEN7 (2 << 0)
239 #define UART_LCR_WLEN8 (3 << 0)
240 #define UART_LCR_SBS_1BIT (0 << 2)
241 #define UART_LCR_SBS_2BIT (1 << 2)
242 #define UART_LCR_PARITY_EN (1 << 3)
243 #define UART_LCR_PARITY_DIS (0 << 3)
244 #define UART_LCR_PARITY_ODD (0)
245 #define UART_LCR_PARITY_EVEN (1 << 4)
246 #define UART_LCR_PARITY_F_1 (2 << 4)
247 #define UART_LCR_PARITY_F_0 (3 << 4)
248 #define UART_LCR_BREAK_EN (1 << 6)
249 #define UART_LCR_DLAB_EN (1 << 7)
250 #define UART_LCR_BITMASK (0xFF)
263 STATIC INLINE void IP_UART_SetMode(IP_USART_001_T *pUART, uint32_t lcr)
264 {
265 pUART->LCR = lcr;
266 }
267
273 STATIC INLINE void IP_UART_EnableDivisorAccess(IP_USART_001_T *pUART)
274 {
275 pUART->LCR |= UART_LCR_DLAB_EN;
276 }
277
283 STATIC INLINE void IP_UART_DisableDivisorAccess(IP_USART_001_T *pUART)
284 {
285 pUART->LCR &= ~UART_LCR_DLAB_EN;
286 }
287
288 #define UART_DLL_MASKBIT (0xFF)
289 #define UART_DLM_MASKBIT (0xFF)
301 STATIC INLINE void IP_UART_SetDivisorLatches(IP_USART_001_T *pUART, uint8_t dll, uint8_t dlm)
302 {
303 pUART->DLL = (uint32_t) dll;
304 pUART->DLM = (uint32_t) dlm;
305 }
306
310 #define UART_MCR_DTR_CTRL (1 << 0)
311 #define UART_MCR_RTS_CTRL (1 << 1)
312 #define UART_MCR_LOOPB_EN (1 << 4)
313 #define UART_MCR_AUTO_RTS_EN (1 << 6)
314 #define UART_MCR_AUTO_CTS_EN (1 << 7)
315 #define UART_MCR_BITMASK (0x0F3)
324 STATIC INLINE uint32_t IP_UART_ReadModemControl(IP_USART_001_T *pUART)
325 {
326 return pUART->MCR;
327 }
328
337 STATIC INLINE void IP_UART_SetModemControl(IP_USART_001_T *pUART, uint32_t mcr)
338 {
339 pUART->MCR |= mcr;
340 }
341
350 STATIC INLINE void IP_UART_ClearModemControl(IP_USART_001_T *pUART, uint32_t mcr)
351 {
352 pUART->MCR &= ~mcr;
353 }
354
358 #define UART_LSR_RDR (1 << 0)
359 #define UART_LSR_OE (1 << 1)
360 #define UART_LSR_PE (1 << 2)
361 #define UART_LSR_FE (1 << 3)
362 #define UART_LSR_BI (1 << 4)
363 #define UART_LSR_THRE (1 << 5)
364 #define UART_LSR_TEMT (1 << 6)
365 #define UART_LSR_RXFE (1 << 7)
366 #define UART_LSR_BITMASK (0xFF)
375 STATIC INLINE uint32_t IP_UART_ReadLineStatus(IP_USART_001_T *pUART)
376 {
377 return pUART->LSR;
378 }
379
383 #define UART_MSR_DELTA_CTS (1 << 0)
384 #define UART_MSR_DELTA_DSR (1 << 1)
385 #define UART_MSR_LO2HI_RI (1 << 2)
386 #define UART_MSR_DELTA_DCD (1 << 3)
387 #define UART_MSR_CTS (1 << 4)
388 #define UART_MSR_DSR (1 << 5)
389 #define UART_MSR_RI (1 << 6)
390 #define UART_MSR_DCD (1 << 7)
391 #define UART_MSR_BITMASK (0xFF)
400 STATIC INLINE uint32_t IP_UART_ReadModemStatus(IP_USART_001_T *pUART)
401 {
402 return pUART->MSR;
403 }
404
411 STATIC INLINE void IP_UART_SetScratch(IP_USART_001_T *pUART, uint8_t data)
412 {
413 pUART->SCR = (uint32_t) data;
414 }
415
421 STATIC INLINE uint8_t IP_UART_ReadScratch(IP_USART_001_T *pUART)
422 {
423 return (uint8_t) (pUART->SCR & 0xFF);
424 }
425
429 #define UART_ACR_START (1 << 0)
430 #define UART_ACR_MODE (1 << 1)
431 #define UART_ACR_AUTO_RESTART (1 << 2)
432 #define UART_ACR_ABEOINT_CLR (1 << 8)
433 #define UART_ACR_ABTOINT_CLR (1 << 9)
434 #define UART_ACR_BITMASK (0x307)
444 STATIC INLINE void IP_UART_SetAutoBaudReg(IP_USART_001_T *pUART, uint32_t acr)
445 {
446 pUART->ACR |= acr;
447 }
448
457 STATIC INLINE void IP_UART_ClearAutoBaudReg(IP_USART_001_T *pUART, uint32_t acr)
458 {
459 pUART->ACR &= ~acr;
460 }
461
467 STATIC INLINE void IP_UART_TXEnable(IP_USART_001_T *pUART)
468 {
469 pUART->TER1 = (1 << 7);
470 }
471
477 STATIC INLINE void IP_UART_TXDisable(IP_USART_001_T *pUART)
478 {
479 pUART->TER1 = 0;
480 }
481
485 #define UART_RS485CTRL_NMM_EN (1 << 0)
486 #define UART_RS485CTRL_RX_DIS (1 << 1)
487 #define UART_RS485CTRL_AADEN (1 << 2)
488 #define UART_RS485CTRL_SEL_DTR (1 << 3)
490 #define UART_RS485CTRL_DCTRL_EN (1 << 4)
491 #define UART_RS485CTRL_OINV_1 (1 << 5)
494 #define UART_RS485CTRL_BITMASK (0x3F)
504 STATIC INLINE void IP_UART_SetRS485Flags(IP_USART_001_T *pUART, uint32_t ctrl)
505 {
506 pUART->RS485CTRL |= ctrl;
507 }
508
517 STATIC INLINE void IP_UART_ClearRS485Flags(IP_USART_001_T *pUART, uint32_t ctrl)
518 {
519 pUART->RS485CTRL &= ~ctrl;
520 }
521
528 STATIC INLINE void IP_UART_SetRS485Addr(IP_USART_001_T *pUART, uint8_t addr)
529 {
530 pUART->RS485ADRMATCH = (uint32_t) addr;
531 }
532
538 STATIC INLINE uint8_t IP_UART_GetRS485Addr(IP_USART_001_T *pUART)
539 {
540 return (uint8_t) (pUART->RS485ADRMATCH & 0xFF);
541 }
542
551 STATIC INLINE void IP_UART_SetRS485Delay(IP_USART_001_T *pUART, uint8_t dly)
552 {
553 pUART->RS485DLY = (uint32_t) dly;
554 }
555
563 STATIC INLINE uint8_t IP_UART_GetRS485Delay(IP_USART_001_T *pUART)
564 {
565 return (uint8_t) (pUART->RS485DLY & 0xFF);
566 }
567
577 uint32_t IP_UART_SetBaud(IP_USART_001_T *pUART, uint32_t baudrate, uint32_t uClk);
578
579 #if 0 // FIXME
580 // FIXME
581 // FDR handled at chip layer
582 // OSR not ready
583 // TER1 not ready
584 // HDEN handled at chip layer
585 // SCICTRL handled at chip layer
586 // TER2 handled at chip layer
587
591 #define UART_ICR_IRDAEN ((uint32_t) (1 << 0))
592 #define UART_ICR_IRDAINV ((uint32_t) (1 << 1))
593 #define UART_ICR_FIXPULSE_EN ((uint32_t) (1 << 2))
594 #define UART_ICR_PULSEDIV(n) ((uint32_t) ((n & 0x07) << 3))
595 #define UART_ICR_BITMASK ((uint32_t) (0x3F))
600 #define UART_HDEN_HDEN ((uint32_t) (1 << 0))
605 #define UART_SCICTRL_SCIEN ((uint32_t) (1 << 0))
606 #define UART_SCICTRL_NACKDIS ((uint32_t) (1 << 1))
607 #define UART_SCICTRL_PROTSEL_T1 ((uint32_t) (1 << 2))
608 #define UART_SCICTRL_TXRETRY(n) ((uint32_t) ((n & 0x07) << 5))
609 #define UART_SCICTRL_GUARDTIME(n) ((uint32_t) ((n & 0xFF) << 8))
614 #define UART_FDR_DIVADDVAL(n) ((uint32_t) (n & 0x0F))
615 #define UART_FDR_MULVAL(n) ((uint32_t) ((n << 4) & 0xF0))
616 #define UART_FDR_BITMASK ((uint32_t) (0xFF))
621 #define UART_TER1_TXEN ((uint8_t) (1 << 7))
622 #define UART_TER1_BITMASK ((uint8_t) (0x80))
623 #define UART_TER2_TXEN ((uint8_t) (1 << 0))
624 #define UART_TER2_BITMASK ((uint8_t) (0x01))
629 #define UART_SYNCCTRL_SYNC ((uint32_t) (1 << 0))
630 #define UART_SYNCCTRL_CSRC_MASTER ((uint32_t) (1 << 1))
631 #define UART_SYNCCTRL_FES ((uint32_t) (1 << 2))
632 #define UART_SYNCCTRL_TSBYPASS ((uint32_t) (1 << 3))
633 #define UART_SYNCCTRL_CSCEN ((uint32_t) (1 << 4))
634 #define UART_SYNCCTRL_STARTSTOPDISABLE ((uint32_t) (1 << 5))
635 #define UART_SYNCCTRL_CCCLR ((uint32_t) (1 << 6))
637 #endif
638
643 #ifdef __cplusplus
644 }
645 #endif
646
647 #endif /* __USART_004_H_ */