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sdmmc_17xx_40xx.h
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1 /*
2 * @brief LPC17xx/40xx SDMMC Card Interface driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __SDMMC_17XX_40XX_H_
33 #define __SDMMC_17XX_40XX_H_
34
35 #include "lpc_sdmmc.h"
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
46 /*
47 * SDMMC Card bus clock rate definitions
48 */
50 #define SDC_IDENT_CLOCK_RATE (400000) /* 400KHz */
51
52 #define SDC_TRAN_CLOCK_RATE (20000000) /* 20MHz */
53
54 /*
55 * SD/MMC Response type definitions
56 */
57 #define CMDRESP_NONE_TYPE (SDC_COMMAND_NO_RSP)
58 #define CMDRESP_R1_TYPE (SDC_COMMAND_SHORT_RSP)
59 #define CMDRESP_R1b_TYPE (SDC_COMMAND_SHORT_RSP)
60 #define CMDRESP_R2_TYPE (SDC_COMMAND_LONG_RSP)
61 #define CMDRESP_R3_TYPE (SDC_COMMAND_SHORT_RSP)
62 #define CMDRESP_R6_TYPE (SDC_COMMAND_SHORT_RSP)
63 #define CMDRESP_R7_TYPE (SDC_COMMAND_SHORT_RSP)
64
65 #ifdef SDC_DMA_ENABLE
66
70 typedef struct {
71 uint8_t DmaChannel;
72 } SDMMC_EVENT_T;
73
74 #else
75
79 typedef struct {
80 void *Buffer;
81 uint32_t Size;
82 uint32_t Index;
83 uint8_t Dir;
84 } SDMMC_EVENT_T;
85 #endif /* SDC_DMA_ENABLE */
86
87 /*
88 * SD command values (Command Index, Response)
89 */
90 #define SD_GO_IDLE_STATE (SDC_COMMAND_INDEX(MMC_GO_IDLE_STATE) | CMDRESP_NONE_TYPE | SDC_COMMAND_INTERRUPT)
91 #define SD_CMD1_SEND_OP_COND (SDC_COMMAND_INDEX(MMC_SEND_OP_COND) | CMDRESP_R3_TYPE | 0)
92 #define SD_CMD2_ALL_SEND_CID (SDC_COMMAND_INDEX(MMC_ALL_SEND_CID) | CMDRESP_R2_TYPE | 0)
93 #define SD_CMD3_SET_RELATIVE_ADDR (SDC_COMMAND_INDEX(MMC_SET_RELATIVE_ADDR) | CMDRESP_R1_TYPE | 0)
94 #define SD_CMD3_SEND_RELATIVE_ADDR (SDC_COMMAND_INDEX(SD_SEND_RELATIVE_ADDR) | CMDRESP_R6_TYPE | 0)
95 #define SD_CMD7_SELECT_CARD (SDC_COMMAND_INDEX(MMC_SELECT_CARD) | CMDRESP_R1b_TYPE | 0)
96 #define SD_CMD8_SEND_IF_COND (SDC_COMMAND_INDEX(SD_CMD8) | CMDRESP_R7_TYPE | 0)
97 #define SD_CMD9_SEND_CSD (SDC_COMMAND_INDEX(MMC_SEND_CSD) | CMDRESP_R2_TYPE | 0)
98 #define SD_CMD12_STOP_TRANSMISSION (SDC_COMMAND_INDEX(MMC_STOP_TRANSMISSION) | CMDRESP_R1_TYPE | 0)
99 #define SD_CMD13_SEND_STATUS (SDC_COMMAND_INDEX(MMC_SEND_STATUS) | CMDRESP_R1_TYPE | 0)
101 /* Block-Oriented Read Commands (class 2) */
102 #define SD_CMD16_SET_BLOCKLEN (SDC_COMMAND_INDEX(MMC_SET_BLOCKLEN) | CMDRESP_R1_TYPE | 0)
103 #define SD_CMD17_READ_SINGLE_BLOCK (SDC_COMMAND_INDEX(MMC_READ_SINGLE_BLOCK) | CMDRESP_R1_TYPE | 0)
104 #define SD_CMD18_READ_MULTIPLE_BLOCK (SDC_COMMAND_INDEX(MMC_READ_MULTIPLE_BLOCK) | CMDRESP_R1_TYPE | 0)
106 /* Block-Oriented Write Commands (class 4) */
107 #define SD_CMD24_WRITE_BLOCK (SDC_COMMAND_INDEX(MMC_WRITE_BLOCK) | CMDRESP_R1_TYPE | 0)
108 #define SD_CMD25_WRITE_MULTIPLE_BLOCK (SDC_COMMAND_INDEX(MMC_WRITE_MULTIPLE_BLOCK) | CMDRESP_R1_TYPE | 0)
110 /* Erase Commands (class 5) */
111 #define SD_CMD32_ERASE_WR_BLK_START (SDC_COMMAND_INDEX(SD_ERASE_WR_BLK_START) | CMDRESP_R1_TYPE | 0)
112 #define SD_CMD33_ERASE_WR_BLK_END (SDC_COMMAND_INDEX(SD_ERASE_WR_BLK_END) | CMDRESP_R1_TYPE | 0)
113 #define SD_CMD38_ERASE (SDC_COMMAND_INDEX(SD_ERASE) | CMDRESP_R1b_TYPE | 0)
115 /* Application-Specific Commands (class 8) */
116 #define SD_CMD55_APP_CMD (SDC_COMMAND_INDEX(MMC_APP_CMD) | CMDRESP_R1_TYPE | 0)
117 #define SD_ACMD6_SET_BUS_WIDTH (SDC_COMMAND_INDEX(SD_APP_SET_BUS_WIDTH) | CMDRESP_R1_TYPE | 0)
118 #define SD_ACMD13_SEND_SD_STATUS (SDC_COMMAND_INDEX(MMC_SEND_STATUS) | CMDRESP_R1_TYPE | 0)
119 #define SD_ACMD41_SD_SEND_OP_COND (SDC_COMMAND_INDEX(SD_APP_OP_COND) | CMDRESP_R3_TYPE | 0)
132 int32_t Chip_SDMMC_IRQHandler (LPC_SDC_T *pSDC, uint8_t *txBuf, uint32_t *txCnt,
133 uint8_t *rxBuf, uint32_t *rxCnt);
134
141 int32_t Chip_SDMMC_Acquire(LPC_SDC_T *pSDC, SDMMC_CARD_T *pCardInfo);
142
149 SDMMC_STATE_T Chip_SDMMC_GetCardState(LPC_SDC_T *pSDC, SDMMC_CARD_T *pCardInfo);
150
157 uint32_t Chip_SDMMC_GetCardStatus(LPC_SDC_T *pSDC, SDMMC_CARD_T *pCardInfo);
158
166 int32_t Chip_SDMMC_GetSDStatus(LPC_SDC_T *pSDC, SDMMC_CARD_T *pCardInfo, uint32_t *pStatus);
167
177 int32_t Chip_SDMMC_ReadBlocks(LPC_SDC_T *pSDC,
178 SDMMC_CARD_T *pCardInfo,
179 void *buffer,
180 int32_t startblock,
181 int32_t blockNum);
182
192 int32_t Chip_SDMMC_WriteBlocks(LPC_SDC_T *pSDC,
193 SDMMC_CARD_T *pCardInfo,
194 void *buffer,
195 int32_t startblock,
196 int32_t blockNum);
197
202 #ifdef __cplusplus
203 }
204 #endif
205
206 #endif /* __SDC_17XX_40XX_H_ */