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emc_001.h
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1 /*
2 * @brief EMC Registers and control functions
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __EMC_001_H_
33 #define __EMC_001_H_
34
35 #include "sys_config.h"
36 #include "cmsis.h"
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
51 typedef struct {
52 __IO uint32_t CONTROL;
53 __I uint32_t STATUS;
54 __IO uint32_t CONFIG;
55 __I uint32_t RESERVED0[5];
56 __IO uint32_t DYNAMICCONTROL;
57 __IO uint32_t DYNAMICREFRESH;
58 __IO uint32_t DYNAMICREADCONFIG;
59 __I uint32_t RESERVED1;
60 __IO uint32_t DYNAMICRP;
61 __IO uint32_t DYNAMICRAS;
62 __IO uint32_t DYNAMICSREX;
63 __IO uint32_t DYNAMICAPR;
64 __IO uint32_t DYNAMICDAL;
65 __IO uint32_t DYNAMICWR;
66 __IO uint32_t DYNAMICRC;
67 __IO uint32_t DYNAMICRFC;
68 __IO uint32_t DYNAMICXSR;
69 __IO uint32_t DYNAMICRRD;
70 __IO uint32_t DYNAMICMRD;
71 __I uint32_t RESERVED2[9];
72 __IO uint32_t STATICEXTENDEDWAIT;
73 __I uint32_t RESERVED3[31];
74 __IO uint32_t DYNAMICCONFIG0;
75 __IO uint32_t DYNAMICRASCAS0;
76 __I uint32_t RESERVED4[6];
77 __IO uint32_t DYNAMICCONFIG1;
78 __IO uint32_t DYNAMICRASCAS1;
79 __I uint32_t RESERVED5[6];
80 __IO uint32_t DYNAMICCONFIG2;
81 __IO uint32_t DYNAMICRASCAS2;
82 __I uint32_t RESERVED6[6];
83 __IO uint32_t DYNAMICCONFIG3;
84 __IO uint32_t DYNAMICRASCAS3;
85 __I uint32_t RESERVED7[38];
86 __IO uint32_t STATICCONFIG0;
87 __IO uint32_t STATICWAITWEN0;
88 __IO uint32_t STATICWAITOEN0;
89 __IO uint32_t STATICWAITRD0;
90 __IO uint32_t STATICWAITPAG0;
91 __IO uint32_t STATICWAITWR0;
92 __IO uint32_t STATICWAITTURN0;
93 __I uint32_t RESERVED8;
94 __IO uint32_t STATICCONFIG1;
95 __IO uint32_t STATICWAITWEN1;
96 __IO uint32_t STATICWAITOEN1;
97 __IO uint32_t STATICWAITRD1;
98 __IO uint32_t STATICWAITPAG1;
99 __IO uint32_t STATICWAITWR1;
100 __IO uint32_t STATICWAITTURN1;
101 __I uint32_t RESERVED9;
102 __IO uint32_t STATICCONFIG2;
103 __IO uint32_t STATICWAITWEN2;
104 __IO uint32_t STATICWAITOEN2;
105 __IO uint32_t STATICWAITRD2;
106 __IO uint32_t STATICWAITPAG2;
107 __IO uint32_t STATICWAITWR2;
108 __IO uint32_t STATICWAITTURN2;
109 __I uint32_t RESERVED10;
110 __IO uint32_t STATICCONFIG3;
111 __IO uint32_t STATICWAITWEN3;
112 __IO uint32_t STATICWAITOEN3;
113 __IO uint32_t STATICWAITRD3;
114 __IO uint32_t STATICWAITPAG3;
115 __IO uint32_t STATICWAITWR3;
116 __IO uint32_t STATICWAITTURN3;
117 } IP_EMC_001_T;
118
122 /* Reserve for extending support to ARM9 or nextgen LPC */
123 #define EMC_SUPPORT_ONLY_PL172
125 #define EMC_CONFIG_ENDIAN_LITTLE (0)
126 #define EMC_CONFIG_ENDIAN_BIG (1)
128 #define EMC_CONFIG_BUFFER_ENABLE (1 << 19)
129 #define EMC_CONFIG_WRITE_PROTECT (1 << 20)
131 /* Dynamic Memory Configuration Register Bit Definitions */
132 #define EMC_DYN_CONFIG_MD_BIT (3)
133 #define EMC_DYN_CONFIG_MD_SDRAM (0 << EMC_DYN_CONFIG_MD_BIT)
134 #define EMC_DYN_CONFIG_MD_LPSDRAM (1 << EMC_DYN_CONFIG_MD_BIT)
136 #define EMC_DYN_CONFIG_LPSDRAM_BIT (12)
137 #define EMC_DYN_CONFIG_LPSDRAM (1 << EMC_DYN_CONFIG_LPSDRAM_BIT)
139 #define EMC_DYN_CONFIG_DEV_SIZE_BIT (9)
140 #define EMC_DYN_CONFIG_DEV_SIZE_16Mb (0x00 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
141 #define EMC_DYN_CONFIG_DEV_SIZE_64Mb (0x01 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
142 #define EMC_DYN_CONFIG_DEV_SIZE_128Mb (0x02 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
143 #define EMC_DYN_CONFIG_DEV_SIZE_256Mb (0x03 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
144 #define EMC_DYN_CONFIG_DEV_SIZE_512Mb (0x04 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
146 #define EMC_DYN_CONFIG_DEV_BUS_BIT (7)
147 #define EMC_DYN_CONFIG_DEV_BUS_8 (0x00 << EMC_DYN_CONFIG_DEV_BUS_BIT)
148 #define EMC_DYN_CONFIG_DEV_BUS_16 (0x01 << EMC_DYN_CONFIG_DEV_BUS_BIT)
149 #define EMC_DYN_CONFIG_DEV_BUS_32 (0x02 << EMC_DYN_CONFIG_DEV_BUS_BIT)
151 #define EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT (14)
152 #define EMC_DYN_CONFIG_DATA_BUS_16 (0x00 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT)
153 #define EMC_DYN_CONFIG_DATA_BUS_32 (0x01 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT)
156 #define EMC_DYN_CONFIG_2Mx8_2BANKS_11ROWS_9COLS ((0x0 << 9) | (0x0 << 7))
157 #define EMC_DYN_CONFIG_1Mx16_2BANKS_11ROWS_8COLS ((0x0 << 9) | (0x1 << 7))
158 #define EMC_DYN_CONFIG_8Mx8_4BANKS_12ROWS_9COLS ((0x1 << 9) | (0x0 << 7))
159 #define EMC_DYN_CONFIG_4Mx16_4BANKS_12ROWS_8COLS ((0x1 << 9) | (0x1 << 7))
160 #define EMC_DYN_CONFIG_2Mx32_4BANKS_11ROWS_8COLS ((0x1 << 9) | (0x2 << 7))
161 #define EMC_DYN_CONFIG_16Mx8_4BANKS_12ROWS_10COLS ((0x2 << 9) | (0x0 << 7))
162 #define EMC_DYN_CONFIG_8Mx16_4BANKS_12ROWS_9COLS ((0x2 << 9) | (0x1 << 7))
163 #define EMC_DYN_CONFIG_4Mx32_4BANKS_12ROWS_8COLS ((0x2 << 9) | (0x2 << 7))
164 #define EMC_DYN_CONFIG_32Mx8_4BANKS_13ROWS_10COLS ((0x3 << 9) | (0x0 << 7))
165 #define EMC_DYN_CONFIG_16Mx16_4BANKS_13ROWS_9COLS ((0x3 << 9) | (0x1 << 7))
166 #define EMC_DYN_CONFIG_8Mx32_4BANKS_13ROWS_8COLS ((0x3 << 9) | (0x2 << 7))
167 #define EMC_DYN_CONFIG_64Mx8_4BANKS_13ROWS_11COLS ((0x4 << 9) | (0x0 << 7))
168 #define EMC_DYN_CONFIG_32Mx16_4BANKS_13ROWS_10COLS ((0x4 << 9) | (0x1 << 7))
171 #define EMC_DYN_MODE_BURST_LEN_BIT (0)
172 #define EMC_DYN_MODE_BURST_LEN_1 (0)
173 #define EMC_DYN_MODE_BURST_LEN_2 (1)
174 #define EMC_DYN_MODE_BURST_LEN_4 (2)
175 #define EMC_DYN_MODE_BURST_LEN_8 (3)
176 #define EMC_DYN_MODE_BURST_LEN_FULL (7)
178 #define EMC_DYN_MODE_BURST_TYPE_BIT (3)
179 #define EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL (0 << EMC_DYN_MODE_BURST_TYPE_BIT)
180 #define EMC_DYN_MODE_BURST_TYPE_INTERLEAVE (1 << EMC_DYN_MODE_BURST_TYPE_BIT)
183 #define EMC_DYN_MODE_CAS_BIT (4)
184 #define EMC_DYN_MODE_CAS_1 (1 << EMC_DYN_MODE_CAS_BIT)
185 #define EMC_DYN_MODE_CAS_2 (2 << EMC_DYN_MODE_CAS_BIT)
186 #define EMC_DYN_MODE_CAS_3 (3 << EMC_DYN_MODE_CAS_BIT)
189 #define EMC_DYN_MODE_OPMODE_BIT (7)
190 #define EMC_DYN_MODE_OPMODE_STANDARD (0 << EMC_DYN_MODE_OPMODE_BIT)
193 #define EMC_DYN_MODE_WBMODE_BIT (9)
194 #define EMC_DYN_MODE_WBMODE_PROGRAMMED (0 << EMC_DYN_MODE_WBMODE_BIT)
195 #define EMC_DYN_MODE_WBMODE_SINGLE_LOC (1 << EMC_DYN_MODE_WBMODE_BIT)
198 #define EMC_DYN_CONTROL_ENABLE (0x03)
201 #define EMC_STATIC_CONFIG_MEM_WIDTH_8 (0)
202 #define EMC_STATIC_CONFIG_MEM_WIDTH_16 (1)
203 #define EMC_STATIC_CONFIG_MEM_WIDTH_32 (2)
205 #define EMC_STATIC_CONFIG_PAGE_MODE_BIT (3)
206 #define EMC_STATIC_CONFIG_PAGE_MODE_ENABLE (1 << EMC_STATIC_CONFIG_PAGE_MODE_BIT)
208 #define EMC_STATIC_CONFIG_CS_POL_BIT (6)
209 #define EMC_STATIC_CONFIG_CS_POL_ACTIVE_HIGH (1 << EMC_STATIC_CONFIG_CS_POL_BIT)
210 #define EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW (0 << EMC_STATIC_CONFIG_CS_POL_BIT)
212 #define EMC_STATIC_CONFIG_BLS_BIT (7)
213 #define EMC_STATIC_CONFIG_BLS_HIGH (1 << EMC_STATIC_CONFIG_BLS_BIT)
214 #define EMC_STATIC_CONFIG_BLS_LOW (0 << EMC_STATIC_CONFIG_BLS_BIT)
216 #define EMC_STATIC_CONFIG_EW_BIT (8)
217 #define EMC_STATIC_CONFIG_EW_ENABLE (1 << EMC_STATIC_CONFIG_EW_BIT)
218 #define EMC_STATIC_CONFIG_EW_DISABLE (0 << EMC_STATIC_CONFIG_EW_BIT)
221 #define Q24_8_FP(x) ((x) * 256)
222 #define EMC_NANOSECOND(x) Q24_8_FP(x)
223 #define EMC_CLOCK(x) Q24_8_FP(-(x))
224
228 typedef struct {
229 uint32_t BaseAddr;
230 uint8_t RAS;
231 uint32_t ModeRegister;
232 uint32_t DynConfig;
233 } IP_EMC_DYN_DEVICE_CONFIG_T;
234
238 typedef struct {
239 int32_t RefreshPeriod;
240 uint32_t ReadConfig;
241 int32_t tRP;
242 int32_t tRAS;
243 int32_t tSREX;
244 int32_t tAPR;
245 int32_t tDAL;
246 int32_t tWR;
247 int32_t tRC;
248 int32_t tRFC;
249 int32_t tXSR;
250 int32_t tRRD;
251 int32_t tMRD;
252 IP_EMC_DYN_DEVICE_CONFIG_T DevConfig[4];
253 } IP_EMC_DYN_CONFIG_T;
254
258 typedef struct {
259 uint8_t ChipSelect;
260 uint32_t Config;
261 int32_t WaitWen;
262 int32_t WaitOen;
263 int32_t WaitRd;
264 int32_t WaitPage;
265 int32_t WaitWr;
266 int32_t WaitTurn;
267 } IP_EMC_STATIC_CONFIG_T;
268
278 void IP_EMC_Dynamic_Init(IP_EMC_001_T *pEMC, IP_EMC_DYN_CONFIG_T *Dynamic_Config, uint32_t EMC_Clock);
279
286 void IP_EMC_Dynamic_Enable(IP_EMC_001_T *pEMC, uint8_t Enable);
287
296 void IP_EMC_Static_Init(IP_EMC_001_T *pEMC, IP_EMC_STATIC_CONFIG_T *Static_Config, uint32_t EMC_Clock);
297
304 void IP_EMC_Mirror(IP_EMC_001_T *pEMC, uint32_t Enable);
305
312 void IP_EMC_Enable(IP_EMC_001_T *pEMC, uint32_t Enable);
313
322 void IP_EMC_LowPowerMode(IP_EMC_001_T *pEMC, uint32_t Enable);
323
332 void IP_EMC_Init(IP_EMC_001_T *pEMC, uint32_t Enable, uint32_t ClockRatio, uint32_t EndianMode);
333
340 void IP_EMC_SetStaticExtendedWait(IP_EMC_001_T *pEMC, uint32_t Wait16Clks);
341
346 #ifdef __cplusplus
347 }
348 #endif
349
350 #endif /* __EMC_001_H_ */