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clock_8xx.c
Go to the documentation of this file.
1 /*
2 * @brief LPC8xx clock driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licenser disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #include "chip.h"
33
34 /*****************************************************************************
35 * Private types/enumerations/variables
36 ****************************************************************************/
37
38 /* Inprecise clock rates for the watchdog oscillator */
39 static const uint32_t wdtOSCRate[WDTLFO_OSC_4_60 + 1] = {
40 0, /* WDT_OSC_ILLEGAL */
41 600000, /* WDT_OSC_0_60 */
42 1050000, /* WDT_OSC_1_05 */
43 1400000, /* WDT_OSC_1_40 */
44 1750000, /* WDT_OSC_1_75 */
45 2100000, /* WDT_OSC_2_10 */
46 2400000, /* WDT_OSC_2_40 */
47 2700000, /* WDT_OSC_2_70 */
48 3000000, /* WDT_OSC_3_00 */
49 3250000, /* WDT_OSC_3_25 */
50 3500000, /* WDT_OSC_3_50 */
51 3750000, /* WDT_OSC_3_75 */
52 4000000, /* WDT_OSC_4_00 */
53 4200000, /* WDT_OSC_4_20 */
54 4400000, /* WDT_OSC_4_40 */
55 4600000 /* WDT_OSC_4_60 */
56 };
57
58 /*****************************************************************************
59 * Public types/enumerations/variables
60 ****************************************************************************/
61
62 /*****************************************************************************
63 * Private functions
64 ****************************************************************************/
65
66 /* Compute a WDT or LFO rate */
67 static uint32_t Chip_Clock_GetWDTLFORate(uint32_t reg)
68 {
69 uint32_t div;
70 CHIP_WDTLFO_OSC_T clk;
71
72 /* Get WDT oscillator settings */
73 clk = (CHIP_WDTLFO_OSC_T) ((reg >> 5) & 0xF);
74 div = reg & 0x1F;
75
76 /* Compute clock rate and divided by divde value */
77 return wdtOSCRate[clk] / ((div + 1) << 1);
78 }
79
80 /* Compute a PLL frequency */
81 static uint32_t Chip_Clock_GetPllFreq(uint32_t PllReg, uint32_t inputRate)
82 {
83 uint32_t msel = ((PllReg & 0x1F) + 1);
84
85 return inputRate * msel;
86 }
87
88 /*****************************************************************************
89 * Public functions
90 ****************************************************************************/
91
92 /* Set System PLL clock source */
93 void Chip_Clock_SetSystemPllSource(CHIP_SYSCTL_PLLCLKSRC_T src)
94 {
95 LPC_SYSCTL->SYSPLLCLKSEL = (uint32_t) src;
96 LPC_SYSCTL->SYSPLLCLKUEN = 0;
97 LPC_SYSCTL->SYSPLLCLKUEN = 1;
98 }
99
100 /* Bypass System Oscillator and set oscillator frequency range */
101 void Chip_Clock_SetPLLBypass(bool bypass, bool highfr)
102 {
103 uint32_t ctrl = 0;
104
105 if (bypass) {
106 ctrl |= (1 << 0);
107 }
108 if (highfr) {
109 ctrl |= (1 << 1);
110 }
111
112 LPC_SYSCTL->SYSOSCCTRL = ctrl;
113 }
114
115 /* Set main system clock source */
116 void Chip_Clock_SetMainClockSource(CHIP_SYSCTL_MAINCLKSRC_T src)
117 {
118 LPC_SYSCTL->MAINCLKSEL = (uint32_t) src;
119 LPC_SYSCTL->MAINCLKUEN = 0;
120 LPC_SYSCTL->MAINCLKUEN = 1;
121 }
122
123 /* Set CLKOUT clock source and divider */
124 void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div)
125 {
126 LPC_SYSCTL->CLKOUTSEL = (uint32_t) src;
127 LPC_SYSCTL->CLKOUTUEN = 0;
128 LPC_SYSCTL->CLKOUTUEN = 1;
129 LPC_SYSCTL->CLKOUTDIV = div;
130 }
131
132 /* Return estimated watchdog oscillator rate */
133 uint32_t Chip_Clock_GetWDTOSCRate(void)
134 {
135 return Chip_Clock_GetWDTLFORate(LPC_SYSCTL->WDTOSCCTRL);
136 }
137
138 /* Return System PLL input clock rate */
139 uint32_t Chip_Clock_GetSystemPllInClockRate(void)
140 {
141 uint32_t clkRate;
142
143 switch ((CHIP_SYSCTL_PLLCLKSRC_T) (LPC_SYSCTL->SYSPLLCLKSEL & 0x3)) {
144 case SYSCTL_PLLCLKSRC_IRC:
145 clkRate = Chip_Clock_GetIntOscRate();
146 break;
147
148 case SYSCTL_PLLCLKSRC_SYSOSC:
149 clkRate = Chip_Clock_GetMainOscRate();
150 break;
151
152 case SYSCTL_PLLCLKSRC_EXT_CLKIN:
153 clkRate = Chip_Clock_GetExtClockInRate();
154 break;
155
156 default:
157 clkRate = 0;
158 }
159
160 return clkRate;
161 }
162
163 /* Return System PLL output clock rate */
164 uint32_t Chip_Clock_GetSystemPllOutClockRate(void)
165 {
166 return Chip_Clock_GetPllFreq(LPC_SYSCTL->SYSPLLCTRL,
167 Chip_Clock_GetSystemPllInClockRate());
168 }
169
170 /* Return main clock rate */
171 uint32_t Chip_Clock_GetMainClockRate(void)
172 {
173 uint32_t clkRate = 0;
174
175 switch ((CHIP_SYSCTL_MAINCLKSRC_T) (LPC_SYSCTL->MAINCLKSEL & 0x3)) {
176 case SYSCTL_MAINCLKSRC_IRC:
177 clkRate = Chip_Clock_GetIntOscRate();
178 break;
179
180 case SYSCTL_MAINCLKSRC_PLLIN:
181 clkRate = Chip_Clock_GetSystemPllInClockRate();
182 break;
183
184 case SYSCTL_MAINCLKSRC_WDTOSC:
185 clkRate = Chip_Clock_GetWDTOSCRate();
186 break;
187
188 case SYSCTL_MAINCLKSRC_PLLOUT:
189 clkRate = Chip_Clock_GetSystemPllOutClockRate();
190 break;
191 }
192
193 return clkRate;
194 }
195
196 /* Return system clock rate */
197 uint32_t Chip_Clock_GetSystemClockRate(void)
198 {
199 /* No point in checking for divide by 0 */
200 return Chip_Clock_GetMainClockRate() / LPC_SYSCTL->SYSAHBCLKDIV;
201 }