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CHIP: LPC18xx/43xx Clock Driver
LPC18xx/43xx chip specific drivers

## Detailed Description

## Data Structures
struct | CGU_USBAUDIO_PLL_SETUP_T

## Modules
| CHIP: LPC18xx/43xx Clock Driver driver options

## Macros
#define | CGU_IRC_FREQ (12000000)
#define | MAX_CLOCK_FREQ (180000000)
#define | CGU_PLL_LOCKED (1 << 0) /* PLL locked status */
#define | CGU_PLL_FR (1 << 1) /* PLL free running indicator status */

## Functions
void | Chip_Clock_EnableCrystal (void)
| Enables the crystal oscillator.
void | Chip_Clock_DisableCrystal (void)
| Disables the crystal oscillator.
uint32_t | Chip_Clock_SetupMainPLLHz (CHIP_CGU_CLKIN_T Input, uint32_t MinHz, uint32_t DesiredHz, uint32_t MaxHz)
| Configures the main PLL.
uint32_t | Chip_Clock_SetupMainPLLMult (CHIP_CGU_CLKIN_T Input, uint32_t mult)
| Directly set the PLL multipler.
uint32_t | Chip_Clock_GetMainPLLHz (void)
| Returns the frequency of the main PLL.
void | Chip_Clock_DisableMainPLL (void)
| Disables the main PLL.
void | Chip_Clock_EnableMainPLL (void)
| Enbles the main PLL.
bool | Chip_Clock_MainPLLLocked (void)
| Returns the lock status of the main PLL.
void | Chip_Clock_SetDivider (CHIP_CGU_IDIV_T Divider, CHIP_CGU_CLKIN_T Input, uint32_t Divisor)
| Sets up a CGU clock divider and it's input clock.
CHIP_CGU_CLKIN_T | Chip_Clock_GetDividerSource (CHIP_CGU_IDIV_T Divider)
| Gets a CGU clock divider source.
uint32_t | Chip_Clock_GetDividerDivisor (CHIP_CGU_IDIV_T Divider)
| Gets a CGU clock divider divisor.
uint32_t | Chip_Clock_GetClockInputHz (CHIP_CGU_CLKIN_T input)
| Returns the frequency of the specified input clock source.
uint32_t | Chip_Clock_GetBaseClocktHz (CHIP_CGU_BASE_CLK_T clock)
| Returns the frequency of the specified base clock source.
void | Chip_Clock_SetBaseClock (CHIP_CGU_BASE_CLK_T BaseClock, CHIP_CGU_CLKIN_T Input, bool autoblocken, bool powerdn)
| Sets a CGU Base Clock clock source.
void | Chip_Clock_GetBaseClockOpts (CHIP_CGU_BASE_CLK_T BaseClock, CHIP_CGU_CLKIN_T *Input, bool *autoblocken, bool *powerdn)
| Get CGU Base Clock clock source information.
CHIP_CGU_CLKIN_T | Chip_Clock_GetBaseClock (CHIP_CGU_BASE_CLK_T BaseClock)
| Gets a CGU Base Clock clock source.
void | Chip_Clock_EnableBaseClock (CHIP_CGU_BASE_CLK_T BaseClock)
| Enables a base clock source.
void | Chip_Clock_DisableBaseClock (CHIP_CGU_BASE_CLK_T BaseClock)
| Disables a base clock source.
bool | Chip_Clock_IsBaseClockEnabled (CHIP_CGU_BASE_CLK_T BaseClock)
| Returns base clock enable state.
void | Chip_Clock_EnableOpts (CHIP_CCU_CLK_T clk, bool autoen, bool wakeupen, int div)
| Enables a peripheral clock and sets clock states.
void | Chip_Clock_Enable (CHIP_CCU_CLK_T clk)
| Enables a peripheral clock.
void | Chip_Clock_Disable (CHIP_CCU_CLK_T clk)
| Disables a peripheral clock.
uint32_t | Chip_Clock_GetRate (CHIP_CCU_CLK_T clk)
| Returns a peripheral clock rate.
void | Chip_Clock_StartPowerDown (void)
| Start the power down sequence by disabling the branch output clocks with wake up mechanism (Only the clocks which wake up mechanism bit enabled will be disabled)
void | Chip_Clock_ClearPowerDown (void)
| Clear the power down mode bit & proceed normal operation of branch output clocks (Only the clocks which wake up mechanism bit enabled will be enabled after the wake up event)
void | Chip_Clock_SetupPLL (CHIP_CGU_CLKIN_T Input, CHIP_CGU_USB_AUDIO_PLL_T pllnum, const CGU_USBAUDIO_PLL_SETUP_T *pPLLSetup)
| Sets up the audio or USB PLL.
void | Chip_Clock_EnablePLL (CHIP_CGU_USB_AUDIO_PLL_T pllnum)
| Enables the audio or USB PLL.
void | Chip_Clock_DisablePLL (CHIP_CGU_USB_AUDIO_PLL_T pllnum)
| Disables the audio or USB PLL.
uint32_t | Chip_Clock_GetPLLStatus (CHIP_CGU_USB_AUDIO_PLL_T pllnum)
| Returns the PLL status.

## Macro Definition Documentation

#define CGU_IRC_FREQ (12000000)

Definition at line 67 of file clock_18xx_43xx.h.

#define CGU_PLL_FR (1 << 1) /* PLL free running indicator status */

Definition at line 314 of file clock_18xx_43xx.h.

#define CGU_PLL_LOCKED (1 << 0) /* PLL locked status */

Definition at line 313 of file clock_18xx_43xx.h.

#define MAX_CLOCK_FREQ (180000000)

Definition at line 73 of file clock_18xx_43xx.h.

## Enumeration Type Documentation

enum CHIP_CCU_CLK_T

Peripheral clocks Peripheral clocks are individual clocks routed to peripherals. Although multiple peripherals may share a same base clock, each peripheral's clock can be enabled or disabled individually. Some peripheral clocks also have additional dividers associated with them.

Enumerator:

  CLK_APB3_BUS | APB3 bus clock from base clock CLK_BASE_APB3
  CLK_APB3_I2C1 | I2C1 register/perigheral clock from base clock CLK_BASE_APB3
  CLK_APB3_DAC | DAC peripheral clock from base clock CLK_BASE_APB3
  CLK_APB3_ADC0 | ADC0 register/perigheral clock from base clock CLK_BASE_APB3
  CLK_APB3_ADC1 | ADC1 register/perigheral clock from base clock CLK_BASE_APB3
  CLK_APB3_CAN0 | CAN0 register/perigheral clock from base clock CLK_BASE_APB3
  CLK_APB1_BUS | APB1 bus clock clock from base clock CLK_BASE_APB1
  CLK_APB1_MOTOCON | Motor controller register/perigheral clock from base clock CLK_BASE_APB1
  CLK_APB1_I2C0 | I2C0 register/perigheral clock from base clock CLK_BASE_APB1
  CLK_APB1_I2S | I2S register/perigheral clock from base clock CLK_BASE_APB1
  CLK_APB1_CAN1 | CAN1 register/perigheral clock from base clock CLK_BASE_APB1
  CLK_SPIFI | SPIFI SCKI input clock from base clock CLK_BASE_SPIFI
  CLK_MX_BUS | M3/M4 BUS core clock from base clock CLK_BASE_MX
  CLK_MX_SPIFI | SPIFI register clock from base clock CLK_BASE_MX
  CLK_MX_GPIO | GPIO register clock from base clock CLK_BASE_MX
  CLK_MX_LCD | LCD register clock from base clock CLK_BASE_MX
  CLK_MX_ETHERNET | ETHERNET register clock from base clock CLK_BASE_MX
  CLK_MX_USB0 | USB0 register clock from base clock CLK_BASE_MX
  CLK_MX_EMC | EMC clock from base clock CLK_BASE_MX
  CLK_MX_SDIO | SDIO register clock from base clock CLK_BASE_MX
  CLK_MX_DMA | DMA register clock from base clock CLK_BASE_MX
  CLK_MX_MXCORE | M3/M4 CPU core clock from base clock CLK_BASE_MX
  RESERVED_ALIGN |
  CLK_MX_SCT | SCT register clock from base clock CLK_BASE_MX
  CLK_MX_USB1 | USB1 register clock from base clock CLK_BASE_MX
  CLK_MX_EMC_DIV | ENC divider clock from base clock CLK_BASE_MX
  CLK_MX_FLASHA | FLASHA bank clock from base clock CLK_BASE_MX
  CLK_MX_FLASHB | FLASHB bank clock from base clock CLK_BASE_MX
  CLK_RESERVED1 |
  CLK_RESERVED2 |
  CLK_MX_EEPROM | EEPROM clock from base clock CLK_BASE_MX
  CLK_MX_WWDT | WWDT register clock from base clock CLK_BASE_MX
  CLK_MX_UART0 | UART0 register clock from base clock CLK_BASE_MX
  CLK_MX_UART1 | UART1 register clock from base clock CLK_BASE_MX
  CLK_MX_SSP0 | SSP0 register clock from base clock CLK_BASE_MX
  CLK_MX_TIMER0 | TIMER0 register/perigheral clock from base clock CLK_BASE_MX
  CLK_MX_TIMER1 | TIMER1 register/perigheral clock from base clock CLK_BASE_MX
  CLK_MX_SCU | SCU register/perigheral clock from base clock CLK_BASE_MX
  CLK_MX_CREG | CREG clock from base clock CLK_BASE_MX
  CLK_MX_RITIMER | RITIMER register/perigheral clock from base clock CLK_BASE_MX
  CLK_MX_UART2 | UART3 register clock from base clock CLK_BASE_MX
  CLK_MX_UART3 | UART4 register clock from base clock CLK_BASE_MX
  CLK_MX_TIMER2 | TIMER2 register/perigheral clock from base clock CLK_BASE_MX
  CLK_MX_TIMER3 | TIMER3 register/perigheral clock from base clock CLK_BASE_MX
  CLK_MX_SSP1 | SSP1 register clock from base clock CLK_BASE_MX
  CLK_MX_QEI | QEI register/perigheral clock from base clock CLK_BASE_MX
  CLK_RESERVED3 |
  CLK_RESERVED3A |
  CLK_RESERVED4 |
  CLK_RESERVED5 |
  CLK_USB0 | USB0 clock from base clock CLK_BASE_USB0
  CLK_USB1 | USB1 clock from base clock CLK_BASE_USB1
  CLK_RESERVED7 |
  CLK_RESERVED8 |
  CLK_CCU1_LAST |
  CLK_CCU2_START |
  CLK_APLL | Audio PLL clock from base clock CLK_BASE_APLL
  RESERVED_ALIGNB |
  CLK_APB2_UART3 | UART3 clock from base clock CLK_BASE_UART3
  RESERVED_ALIGNC |
  CLK_APB2_UART2 | UART2 clock from base clock CLK_BASE_UART2
  RESERVED_ALIGND |
  CLK_APB0_UART1 | UART1 clock from base clock CLK_BASE_UART1
  RESERVED_ALIGNE |
  CLK_APB0_UART0 | UART0 clock from base clock CLK_BASE_UART0
  RESERVED_ALIGNF |
  CLK_APB2_SSP1 | SSP1 clock from base clock CLK_BASE_SSP1
  RESERVED_ALIGNG |
  CLK_APB0_SSP0 | SSP0 clock from base clock CLK_BASE_SSP0
  RESERVED_ALIGNH |
  CLK_APB2_SDIO | SDIO clock from base clock CLK_BASE_SDIO
  CLK_CCU2_LAST |

Definition at line 149 of file chip_clocks.h.

enum CHIP_CGU_BASE_CLK_T

CGU base clocks CGU base clocks are clocks that are associated with a single input clock and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH clock can be configured to use the CLKIN_MAINPLL input clock, which will in turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and CLK_PERIPH_SGPIO periphral clocks.

Enumerator:

  CLK_BASE_SAFE | Base clock for WDT oscillator, IRC input only
  CLK_BASE_USB0 | Base USB clock for USB0, USB PLL input only
  CLK_BASE_RESERVED1 |
  CLK_BASE_USB1 | Base USB clock for USB1
  CLK_BASE_MX | Base clock for CPU core
  CLK_BASE_SPIFI | Base clock for SPIFI
  CLK_BASE_RESERVED2 |
  CLK_BASE_PHY_RX | Base clock for PHY RX
  CLK_BASE_PHY_TX | Base clock for PHY TX
  CLK_BASE_APB1 | Base clock for APB1 group
  CLK_BASE_APB3 | Base clock for APB3 group
  CLK_BASE_LCD | Base clock for LCD pixel clock
  CLK_BASE_RESERVED3 |
  CLK_BASE_SDIO | Base clock for SDIO
  CLK_BASE_SSP0 | Base clock for SSP0
  CLK_BASE_SSP1 | Base clock for SSP1
  CLK_BASE_UART0 | Base clock for UART0
  CLK_BASE_UART1 | Base clock for UART1
  CLK_BASE_UART2 | Base clock for UART2
  CLK_BASE_UART3 | Base clock for UART3
  CLK_BASE_OUT | Base clock for CLKOUT pin
  CLK_BASE_RESERVED4 |
  CLK_BASE_RESERVED5 |
  CLK_BASE_RESERVED6 |
  CLK_BASE_RESERVED7 |
  CLK_BASE_APLL | Base clock for audio PLL
  CLK_BASE_CGU_OUT0 | Base clock for CGUOUT0 pin
  CLK_BASE_CGU_OUT1 | Base clock for CGUOUT1 pin
  CLK_BASE_LAST |
  CLK_BASE_NONE |

Definition at line 80 of file chip_clocks.h.

enum CHIP_CGU_CLKIN_T

CGU clock input list These are possible input clocks for the CGU and can come from both external (crystal) and internal (PLL) sources. These clock inputs can be routed to the base clocks (CHIP_CGU_BASE_CLK_T).

Enumerator:

  CLKIN_32K | External 32KHz input
  CLKIN_IRC | Internal IRC (12MHz) input
  CLKIN_ENET_RX | External ENET_RX pin input
  CLKIN_ENET_TX | External ENET_TX pin input
  CLKIN_CLKIN | External GPCLKIN pin input
  CLKIN_RESERVED1 |
  CLKIN_CRYSTAL | External (main) crystal pin input
  CLKIN_USBPLL | Internal USB PLL input
  CLKIN_AUDIOPLL | Internal Audio PLL input
  CLKIN_MAINPLL | Internal Main PLL input
  CLKIN_RESERVED2 |
  CLKIN_RESERVED3 |
  CLKIN_IDIVA | Internal divider A input
  CLKIN_IDIVB | Internal divider B input
  CLKIN_IDIVC | Internal divider C input
  CLKIN_IDIVD | Internal divider D input
  CLKIN_IDIVE | Internal divider E input
  CLKINPUT_PD | External 32KHz input

Definition at line 51 of file chip_clocks.h.

enum CHIP_CGU_IDIV_T

CGU dividers CGU dividers provide an extra clock state where a specific clock can be divided before being routed to a peripheral group. A divider accepts an input clock and then divides it. To use the divided clock for a base clock group, use the divider as the input clock for the base clock (for example, use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider).

Enumerator:

  CLK_IDIV_A | CGU clock divider A
  CLK_IDIV_B | CGU clock divider B
  CLK_IDIV_C | CGU clock divider A
  CLK_IDIV_D | CGU clock divider D
  CLK_IDIV_E | CGU clock divider E
  CLK_IDIV_LAST |

Definition at line 133 of file chip_clocks.h.

enum CHIP_CGU_USB_AUDIO_PLL_T

Audio or USB PLL selection

Enumerator:

  CGU_USB_PLL |
  CGU_AUDIO_PLL |

Definition at line 49 of file cguccu_18xx_43xx.h.

## Function Documentation

void Chip_Clock_ClearPowerDown | ( | void |  | ) |

Clear the power down mode bit & proceed normal operation of branch output clocks (Only the clocks which wake up mechanism bit enabled will be enabled after the wake up event)

Returns
  Nothing

Enable all branch output clocks after the wake up event. Only the clocks with wake up mechanism enabled will be enabled

Definition at line 599 of file clock_18xx_43xx.c.

void Chip_Clock_Disable | ( | CHIP_CCU_CLK_T | clk | ) |

Disables a peripheral clock.

Parameters

  clk | : CHIP_CCU_CLK_T value indicating which clock to disable

Returns
  Nothing

Definition at line 572 of file clock_18xx_43xx.c.

void Chip_Clock_DisableBaseClock | ( | CHIP_CGU_BASE_CLK_T | BaseClock | ) |

Disables a base clock source.

Parameters

  BaseClock | : CHIP_CGU_BASE_CLK_T value indicating which base clock to disable

Returns
  Nothing

Definition at line 491 of file clock_18xx_43xx.c.

void Chip_Clock_DisableCrystal | ( | void |  | ) |

Disables the crystal oscillator.

Returns
  Nothing

Definition at line 145 of file clock_18xx_43xx.c.

void Chip_Clock_DisableMainPLL | ( | void |  | ) |

Disables the main PLL.

Returns
  none Make sure the main PLL is not needed to clock the part before disabling it. Saves power if the main PLL is not needed.

Definition at line 283 of file clock_18xx_43xx.c.

void Chip_Clock_DisablePLL | ( | CHIP_CGU_USB_AUDIO_PLL_T | pllnum | ) |

Disables the audio or USB PLL.

Parameters

  pllnum | : PLL identifier

Returns
  Nothing

Definition at line 668 of file clock_18xx_43xx.c.

void Chip_Clock_Enable | ( | CHIP_CCU_CLK_T | clk | ) |

Enables a peripheral clock.

Parameters

  clk | : CHIP_CCU_CLK_T value indicating which clock to enable

Returns
  Nothing

Definition at line 560 of file clock_18xx_43xx.c.

void Chip_Clock_EnableBaseClock | ( | CHIP_CGU_BASE_CLK_T | BaseClock | ) |

Enables a base clock source.

Parameters

  BaseClock | : CHIP_CGU_BASE_CLK_T value indicating which base clock to enable

Returns
  Nothing

Definition at line 483 of file clock_18xx_43xx.c.

void Chip_Clock_EnableCrystal | ( | void |  | ) |

Enables the crystal oscillator.

Returns
  Nothing

Definition at line 125 of file clock_18xx_43xx.c.

void Chip_Clock_EnableMainPLL | ( | void |  | ) |

Enbles the main PLL.

Returns
  none Make sure the main PLL is enabled.

Definition at line 290 of file clock_18xx_43xx.c.

void Chip_Clock_EnableOpts | ( | CHIP_CCU_CLK_T | clk,
|  | bool | autoen,
|  | bool | wakeupen,
|  | int | div
| ) |  |

Enables a peripheral clock and sets clock states.

Parameters

  clk | : CHIP_CCU_CLK_T value indicating which clock to enable
  autoen | : true to enable autoblocking on a clock rate change, false to disable
  wakeupen | : true to enable wakeup mechanism, false to disable
  div | : Divider for the clock, must be 1 for most clocks, 2 supported on others

Returns
  Nothing

Definition at line 533 of file clock_18xx_43xx.c.

void Chip_Clock_EnablePLL | ( | CHIP_CGU_USB_AUDIO_PLL_T | pllnum | ) |

Enables the audio or USB PLL.

Parameters

  pllnum | : PLL identifier

Returns
  Nothing

Definition at line 662 of file clock_18xx_43xx.c.

CHIP_CGU_CLKIN_T Chip_Clock_GetBaseClock | ( | CHIP_CGU_BASE_CLK_T | BaseClock | ) |

Gets a CGU Base Clock clock source.

Parameters

  BaseClock | : CHIP_CGU_BASE_CLK_T value indicating which base clock to get inpuot clock for

Returns
  CHIP_CGU_CLKIN_T indicating which clock source is set or CLOCKINPUT_PD

Definition at line 514 of file clock_18xx_43xx.c.

void Chip_Clock_GetBaseClockOpts | ( | CHIP_CGU_BASE_CLK_T | BaseClock,
|  | CHIP_CGU_CLKIN_T * | Input,
|  | bool * | autoblocken,
|  | bool * | powerdn
| ) |  |

Get CGU Base Clock clock source information.

Parameters

  BaseClock | : CHIP_CGU_BASE_CLK_T value indicating which base clock to get
  Input | : Pointer to CHIP_CGU_CLKIN_T value of the base clock
  autoblocken | : Pointer to autoblocking value of the base clock
  powerdn | : Pointer to power down flag

Returns
  Nothing

Definition at line 463 of file clock_18xx_43xx.c.

uint32_t Chip_Clock_GetBaseClocktHz | ( | CHIP_CGU_BASE_CLK_T | clock | ) |

Returns the frequency of the specified base clock source.

Parameters

  clock | : which base clock to return the frequency of.

Returns
  Frequency of base source in Hz This function returns an ideal frequency and not the actual frequency. Returns zero if the clock source is disabled.

Definition at line 429 of file clock_18xx_43xx.c.

uint32_t Chip_Clock_GetClockInputHz | ( | CHIP_CGU_CLKIN_T | input | ) |

Returns the frequency of the specified input clock source.

Parameters

  input | : Which clock input to return the frequency of

Returns
  Frequency of input source in Hz This function returns an ideal frequency and not the actual frequency. Returns zero if the clock source is disabled.

Definition at line 341 of file clock_18xx_43xx.c.

uint32_t Chip_Clock_GetDividerDivisor | ( | CHIP_CGU_IDIV_T | Divider | ) |

Gets a CGU clock divider divisor.

Parameters

  Divider | : CHIP_CGU_IDIV_T value indicating which divider to get the source of

Returns
  the divider value for the divider

Definition at line 335 of file clock_18xx_43xx.c.

CHIP_CGU_CLKIN_T Chip_Clock_GetDividerSource | ( | CHIP_CGU_IDIV_T | Divider | ) |

Gets a CGU clock divider source.

Parameters

  Divider | : CHIP_CGU_IDIV_T value indicating which divider to get the source of

Returns
  CHIP_CGU_CLKIN_T indicating which clock source is set or CLOCKINPUT_PD

Definition at line 323 of file clock_18xx_43xx.c.

uint32_t Chip_Clock_GetMainPLLHz | ( | void |  | ) |

Returns the frequency of the main PLL.

Returns
  Frequency of the PLL in Hz Returns zero if the main PLL is not running.

Definition at line 252 of file clock_18xx_43xx.c.

uint32_t Chip_Clock_GetPLLStatus | ( | CHIP_CGU_USB_AUDIO_PLL_T | pllnum | ) |

Returns the PLL status.

Parameters

  pllnum | : PLL identifier

Returns
  An OR'ed value of CGU_PLL_LOCKED or CGU_PLL_FR

Definition at line 674 of file clock_18xx_43xx.c.

uint32_t Chip_Clock_GetRate | ( | CHIP_CCU_CLK_T | clk | ) |

Returns a peripheral clock rate.

Parameters

  clk | : CHIP_CCU_CLK_T value indicating which clock to get rate for

Returns
  0 if the clock is disabled, or the rate of the clock

Definition at line 607 of file clock_18xx_43xx.c.

bool Chip_Clock_IsBaseClockEnabled | ( | CHIP_CGU_BASE_CLK_T | BaseClock | ) |

Returns base clock enable state.

Parameters

  BaseClock | : CHIP_CGU_BASE_CLK_T value indicating which base clock to check

Returns
  true if the base clock is enabled, false if disabled

Definition at line 499 of file clock_18xx_43xx.c.

bool Chip_Clock_MainPLLLocked | ( | void |  | ) |

Returns the lock status of the main PLL.

Returns
  true if the PLL is locked, otherwise false The main PLL should be locked prior to using it as a clock input for a base clock.

Definition at line 297 of file clock_18xx_43xx.c.

void Chip_Clock_SetBaseClock | ( | CHIP_CGU_BASE_CLK_T | BaseClock,
|  | CHIP_CGU_CLKIN_T | Input,
|  | bool | autoblocken,
|  | bool | powerdn
| ) |  |

Sets a CGU Base Clock clock source.

Parameters

  BaseClock | : CHIP_CGU_BASE_CLK_T value indicating which base clock to set
  Input | : CHIP_CGU_CLKIN_T value indicating which clock source to use or CLOCKINPUT_PD to power down base clock
  autoblocken | : Enables autoblocking during frequency change if true
  powerdn | : The clock base is setup, but powered down if true

Returns
  Nothing

Definition at line 435 of file clock_18xx_43xx.c.

void Chip_Clock_SetDivider | ( | CHIP_CGU_IDIV_T | Divider,
|  | CHIP_CGU_CLKIN_T | Input,
|  | uint32_t | Divisor
| ) |  |

Sets up a CGU clock divider and it's input clock.

Parameters

  Divider | : CHIP_CGU_IDIV_T value indicating which divider to configure
  Input | : CHIP_CGU_CLKIN_T value indicating which clock source to use or CLOCKINPUT_PD to power down divider
  Divisor | : value to divide Input clock by

Returns
  Nothing Maximum divider on A = 4, B/C/D = 16, E = 256. See the user manual for allowable combinations for input clock.

Definition at line 304 of file clock_18xx_43xx.c.

uint32_t Chip_Clock_SetupMainPLLHz | ( | CHIP_CGU_CLKIN_T | Input,
|  | uint32_t | MinHz,
|  | uint32_t | DesiredHz,
|  | uint32_t | MaxHz
| ) |  |

Configures the main PLL.

Parameters

  Input | : Which clock input to use as the PLL input
  MinHz | : Minimum allowable PLL output frequency
  DesiredHz | : Desired PLL output frequency
  MaxHz | : Maximum allowable PLL output frequency

Returns
  Frequency of the PLL in Hz Returns the configured PLL frequency or zero if the PLL can not be configured between MinHz and MaxHz. This will not wait for PLL lock. Call Chip_Clock_MainPLLLocked() to determine if the PLL is locked.

Definition at line 152 of file clock_18xx_43xx.c.

uint32_t Chip_Clock_SetupMainPLLMult | ( | CHIP_CGU_CLKIN_T | Input,
|  | uint32_t | mult
| ) |  |

Directly set the PLL multipler.

Parameters

  Input | : Which clock input to use as the PLL input
  mult | : How many times to multiply the input clock

Returns
  Frequency of the PLL in Hz

Definition at line 212 of file clock_18xx_43xx.c.

void Chip_Clock_SetupPLL | ( | CHIP_CGU_CLKIN_T | Input,
|  | CHIP_CGU_USB_AUDIO_PLL_T | pllnum,
|  | const CGU_USBAUDIO_PLL_SETUP_T * | pPLLSetup
| ) |  |

Sets up the audio or USB PLL.

Parameters

  Input | : Input clock
  pllnum | : PLL identifier
  pPLLSetup | : Pointer to PLL setup structure

Returns
  Nothing Sets up the PLL with the passed structure values.

Definition at line 646 of file clock_18xx_43xx.c.

void Chip_Clock_StartPowerDown | ( | void |  | ) |

Start the power down sequence by disabling the branch output clocks with wake up mechanism (Only the clocks which wake up mechanism bit enabled will be disabled)

Returns
  Nothing

Disable all branch output clocks with wake up mechanism enabled. Only the clocks with wake up mechanism enabled will be disabled & power down sequence started

Definition at line 588 of file clock_18xx_43xx.c.