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pinint_8xx.h
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1 /*
2 * @brief LPC8xx Pin Interrupt and Pattern Match Registers and driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __PIN_INT_8XX_H_
33 #define __PIN_INT_8XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
47 typedef struct {
48 __IO uint32_t ISEL;
49 __IO uint32_t IENR;
50 __IO uint32_t SIENR;
51 __IO uint32_t CIENR;
52 __IO uint32_t IENF;
53 __IO uint32_t SIENF;
54 __IO uint32_t CIENF;
55 __IO uint32_t RISE;
56 __IO uint32_t FALL;
57 __IO uint32_t IST;
58 __IO uint32_t PMCTRL;
59 __IO uint32_t PMSRC;
60 __IO uint32_t PMCFG;
61 } LPC_PIN_INT_T;
62
68 #define PMODE_EDGE (0)
69 #define PMODE_LEVEL (1)
71 #define PMODE_SET(t, p, x) (x ? (t->ISEL |= (x << p)) : (t->ISEL &= ~(1 << p)))
72
73 #define ENRL_DISABLE (0)
74 #define ENRL_ENABLE (1)
76 #define ENRL_SET(t, p, x) (x ? (t->IENR |= (x << p)) : (t->IENR &= ~(1 << p)))
77
78 #define SETENRL(t, p) (t->SIENR |= (1 << p))
79 #define CENRL(t, p) (t->CIENR |= (1 << p))
81 #define ENAF_LOW (0)
82 #define ENAF_HIGH (1)
84 #define ENAF_SET(t, p, x) (x ? (t->IENF |= (x << p)) : (t->IENF &= ~(1 << p)))
85
86 #define SETENAF(t, p) (t->SIENF |= (1 << p))
87 #define CENAF(t, p) (t->CIENF |= (1 << p))
90 #define RDET_CLR(t, p) (t->RISE |= (1 << p))
91
92 #define FDET_CLR(t, p) (t->FALL |= (1 << p))
93
94 #define PSTAT_CRL(t, p) (t->IST |= (1 << p))
95
99 typedef enum CHIP_PMI_PIN {
100 PMI0 = 0,
101 PMI1 = 1,
102 PMI2 = 2,
103 PMI3 = 3,
104 PMI4 = 4,
105 PMI5 = 5,
106 PMI6 = 6,
107 PMI7 = 7
108 } CHIP_PMI_PIN_T;
109
113 typedef enum CHIP_PINT_CFG {
114 PINT_ACTIVE_LOW = 0,
115 PINT_ACTIVE_HIGH = 1,
116 PINT_EDGE_DET = 2,
117 PINT_LEVEL_DET = 4,
118 PINT_RISING = 8,
119 PINT_FALLING = 16
120 } CHIP_PINT_CFG_T;
121
128 void Chip_PININT_Config(CHIP_PMI_PIN_T pin, CHIP_PINT_CFG_T cfg);
129
134 #ifdef __cplusplus
135 }
136 #endif
137
138 #endif /* __PIN_INT_8XX_H_ */