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ssp_11xx.h
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1 /*
2 * @brief LPC11xx SSP driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __SSP_11XX_H_
33 #define __SSP_11XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
43 #if defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11AXX) || defined(CHIP_LPC11UXX)
44 #define SSP1_SUPPORT /* SSP1 is not supported in LPC110X and LPC11XXLV */
45 #endif
46
47 /*
48 * @brief SSP clock format
49 */
50 typedef enum CHIP_SSP_CLOCK_FORMAT {
51 SSP_CLOCK_CPHA0_CPOL0 = (0 << 6),
52 SSP_CLOCK_CPHA0_CPOL1 = (1u << 6),
53 SSP_CLOCK_CPHA1_CPOL0 = (2u << 6),
54 SSP_CLOCK_CPHA1_CPOL1 = (3u << 6),
55 SSP_CLOCK_MODE0 = SSP_CLOCK_CPHA0_CPOL0,
56 SSP_CLOCK_MODE1 = SSP_CLOCK_CPHA1_CPOL0,
57 SSP_CLOCK_MODE2 = SSP_CLOCK_CPHA0_CPOL1,
58 SSP_CLOCK_MODE3 = SSP_CLOCK_CPHA1_CPOL1,
59 } CHIP_SSP_CLOCK_MODE_T;
60
61 /*
62 * @brief SSP frame format
63 */
64 typedef enum CHIP_SSP_FRAME_FORMAT {
65 SSP_FRAMEFORMAT_SPI = (0 << 4),
66 CHIP_SSP_FRAME_FORMAT_TI = (1u << 4),
67 SSP_FRAMEFORMAT_MICROWIRE = (2u << 4),
68 } CHIP_SSP_FRAME_FORMAT_T;
69
70 /*
71 * @brief Number of bits per frame
72 */
73 typedef enum CHIP_SSP_BITS {
74 SSP_BITS_4 = (3u << 0),
75 SSP_BITS_5 = (4u << 0),
76 SSP_BITS_6 = (5u << 0),
77 SSP_BITS_7 = (6u << 0),
78 SSP_BITS_8 = (7u << 0),
79 SSP_BITS_9 = (8u << 0),
80 SSP_BITS_10 = (9u << 0),
81 SSP_BITS_11 = (10u << 0),
82 SSP_BITS_12 = (11u << 0),
83 SSP_BITS_13 = (12u << 0),
84 SSP_BITS_14 = (13u << 0),
85 SSP_BITS_15 = (14u << 0),
86 SSP_BITS_16 = (15u << 0),
87 } CHIP_SSP_BITS_T;
88
89 /*
90 * @brief SSP config format
91 */
92 typedef struct SSP_ConfigFormat {
93 CHIP_SSP_BITS_T bits;
94 CHIP_SSP_CLOCK_MODE_T clockMode;
95 CHIP_SSP_FRAME_FORMAT_T frameFormat;
96 } SSP_ConfigFormat;
97
98 /*
99 * @brief SSP mode
100 */
101 typedef enum CHIP_SSP_MODE {
102 SSP_MODE_MASTER = (0 << 2),
103 SSP_MODE_SLAVE = (1u << 2),
104 } CHIP_SSP_MODE_T;
105
106 /*
107 * @brief SPI address
108 */
109 typedef struct {
110 uint8_t port;
111 uint8_t pin;
112 } SPI_Address_t;
113
114 /*
115 * @brief SSP data setup structure
116 */
117 typedef struct {
118 void *tx_data;
119 uint32_t tx_cnt;
120 void *rx_data;
121 uint32_t rx_cnt;
122 uint32_t length;
123 } Chip_SSP_DATA_SETUP_T;
124
127 #define SSP_CPHA_FIRST SSP_CR0_CPHA_FIRST
128 #define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND
129
131 /* There's no bug here!!!
132 * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
133 * That means the active clock is in HI state.
134 * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
135 * high between frames. That means the active clock is in LO state.
136 */
137 #define SSP_CPOL_HI SSP_CR0_CPOL_LO
138 #define SSP_CPOL_LO SSP_CR0_CPOL_HI
139
141 #define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN
142 #define SSP_MASTER_MODE SSP_CR1_MASTER_EN
143
155 STATIC INLINE FlagStatus Chip_SSP_GetStatus(LPC_SSP_T *pSSP, IP_SSP_STATUS_T Stat)
156 {
157 return IP_SSP_GetStatus(pSSP, Stat);
158 }
159
165 STATIC INLINE void Chip_SSP_Enable(LPC_SSP_T *pSSP)
166 {
167 IP_SSP_Enable(pSSP);
168 }
169
175 STATIC INLINE void Chip_SSP_Disable(LPC_SSP_T *pSSP)
176 {
177 IP_SSP_Disable(pSSP);
178 }
179
187 STATIC INLINE void Chip_SSP_EnableLoopBack(LPC_SSP_T *pSSP)
188 {
189 IP_SSP_EnableLoopBack(pSSP);
190 }
191
199 STATIC INLINE void Chip_SSP_DisableLoopBack(LPC_SSP_T *pSSP)
200 {
201 IP_SSP_DisableLoopBack(pSSP);
202 }
203
209 void Chip_SSP_Int_FlushData(LPC_SSP_T *pSSP);
210
218 Status Chip_SSP_Int_RWFrames8Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
219
227 Status Chip_SSP_Int_RWFrames16Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
228
240 uint32_t Chip_SSP_RWFrames_Blocking(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
241
252 uint32_t Chip_SSP_WriteFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len);
253
264 uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len);
265
271 void Chip_SSP_Init(LPC_SSP_T *pSSP);
272
278 void Chip_SSP_DeInit(LPC_SSP_T *pSSP);
279
286 void Chip_SSP_SetMaster(LPC_SSP_T *pSSP, bool master);
287
294 void Chip_SSP_SetBitRate(LPC_SSP_T *pSSP, uint32_t bitRate);
295
302 STATIC INLINE void Chip_SSP_SetFormat(LPC_SSP_T *pSSP, SSP_ConfigFormat *format)
303 {
304 IP_SSP_SetFormat(pSSP, format->bits, format->frameFormat, format->clockMode);
305 }
306
312 STATIC INLINE void Chip_SSP_Int_Enable(LPC_SSP_T *pSSP)
313 {
314 IP_SSP_Int_Enable(pSSP, SSP_TXIM);
315 }
316
322 STATIC INLINE void Chip_SSP_Int_Disable(LPC_SSP_T *pSSP)
323 {
324 IP_SSP_Int_Disable(pSSP, SSP_TXIM);
325 }
326
331 #ifdef __cplusplus
332 }
333 #endif
334
335 #endif /* __SSP_11XX_H_ */