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sysctl_11xx.h
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1 /*
2 * @brief LPC11XX System Control registers and control functions
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __SYSCTL_11XX_H_
33 #define __SYSCTL_11XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
47 typedef struct {
48 __IO uint32_t SYSMEMREMAP;
49 __IO uint32_t PRESETCTRL;
50 __IO uint32_t SYSPLLCTRL;
51 __I uint32_t SYSPLLSTAT;
52 __IO uint32_t USBPLLCTRL;
53 __I uint32_t USBPLLSTAT;
54 __I uint32_t RESERVED1[2];
55 __IO uint32_t SYSOSCCTRL;
56 __IO uint32_t WDTOSCCTRL;
57 __IO uint32_t IRCCTRL;
58 __IO uint32_t LFOSCCTRL;
59 __IO uint32_t SYSRSTSTAT;
60 __I uint32_t RESERVED2[3];
61 __IO uint32_t SYSPLLCLKSEL;
62 __IO uint32_t SYSPLLCLKUEN;
63 __IO uint32_t USBPLLCLKSEL;
64 __IO uint32_t USBPLLCLKUEN;
65 __I uint32_t RESERVED3[8];
66 __IO uint32_t MAINCLKSEL;
67 __IO uint32_t MAINCLKUEN;
68 __IO uint32_t SYSAHBCLKDIV;
69 __I uint32_t RESERVED4;
70 __IO uint32_t SYSAHBCLKCTRL;
71 __I uint32_t RESERVED5[4];
72 __IO uint32_t SSP0CLKDIV;
73 __IO uint32_t USARTCLKDIV;
74 __IO uint32_t SSP1CLKDIV;
75 __I uint32_t RESERVED6[8];
76 __IO uint32_t USBCLKSEL;
77 __IO uint32_t USBCLKUEN;
78 __IO uint32_t USBCLKDIV;
79 __I uint32_t RESERVED7;
80 __IO uint32_t WDTCLKSEL;
81 __IO uint32_t WDTCLKUEN;
82 __IO uint32_t WDTCLKDIV;
83 __I uint32_t RESERVED8;
84 __IO uint32_t CLKOUTSEL;
85 __IO uint32_t CLKOUTUEN;
86 __IO uint32_t CLKOUTDIV;
87 __I uint32_t RESERVED9[5];
88 __I uint32_t PIOPORCAP[2];
89 __I uint32_t RESERVED10[18];
90 __IO uint32_t BODCTRL;
91 __IO uint32_t SYSTCKCAL;
92 __I uint32_t RESERVED11[6];
93 __IO uint32_t IRQLATENCY;
94 __IO uint32_t NMISRC;
95 __IO uint32_t PINTSEL[8];
96 __IO uint32_t USBCLKCTRL;
97 __I uint32_t USBCLKST;
98 __I uint32_t RESERVED12[24];
99 __IO uint32_t STARTAPRP0;
100 __IO uint32_t STARTERP0;
101 __IO uint32_t STARTRSRP0CLR;
102 __IO uint32_t STARTSRP0;
103 __I uint32_t RESERVED13;
104 __IO uint32_t STARTERP1;
105 __I uint32_t RESERVED14[6];
106 __IO uint32_t PDSLEEPCFG;
107 __IO uint32_t PDWAKECFG;
108 __IO uint32_t PDRUNCFG;
109 __I uint32_t RESERVED15[110];
110 __I uint32_t DEVICEID;
111 } LPC_SYSCTL_T;
112
116 typedef enum CHIP_SYSCTL_BOOT_MODE_REMAP {
117 REMAP_BOOT_LOADER_MODE,
118 REMAP_USER_RAM_MODE,
119 REMAP_USER_FLASH_MODE
120 } CHIP_SYSCTL_BOOT_MODE_REMAP_T;
121
127 STATIC INLINE void Chip_SYSCTL_Map(CHIP_SYSCTL_BOOT_MODE_REMAP_T remap)
128 {
129 LPC_SYSCTL->SYSMEMREMAP = (uint32_t) remap;
130 }
131
135 typedef enum {
136 RESET_SSP0,
137 RESET_I2C0,
138 RESET_SSP1,
139 RESET_CAN0,
140 RESET_UART0,
141 RESET_TIMER0_16,
142 RESET_TIMER1_16,
143 RESET_TIMER0_32,
144 RESET_TIMER1_32,
145 RESET_ACMP,
146 RESET_DAC0,
147 RESET_ADC0
148 } CHIP_SYSCTL_PERIPH_RESET_T;
149
157 STATIC INLINE void Chip_SYSCTL_AssertPeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
158 {
159 LPC_SYSCTL->PRESETCTRL &= ~(1 << (uint32_t) periph);
160 }
161
167 STATIC INLINE void Chip_SYSCTL_DeassertPeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
168 {
169 LPC_SYSCTL->PRESETCTRL |= (1 << (uint32_t) periph);
170 }
171
177 STATIC INLINE void Chip_SYSCTL_PeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
178 {
179 Chip_SYSCTL_AssertPeriphReset(periph);
180 Chip_SYSCTL_DeassertPeriphReset(periph);
181 }
182
186 #define SYSCTL_RST_POR (1 << 0)
187 #define SYSCTL_RST_EXTRST (1 << 1)
188 #define SYSCTL_RST_WDT (1 << 2)
189 #define SYSCTL_RST_BOD (1 << 3)
190 #define SYSCTL_RST_SYSRST (1 << 4)
195 #define SYSCTL_NMISRC_ENABLE ((uint32_t) 1 << 31)
202 STATIC INLINE uint32_t Chip_SYSCTL_GetSystemRSTStatus(void)
203 {
204 return LPC_SYSCTL->SYSRSTSTAT;
205 }
206
213 STATIC INLINE void Chip_SYSCTL_ClearSystemRSTStatus(uint32_t reset)
214 {
215 LPC_SYSCTL->SYSRSTSTAT = reset;
216 }
217
224 STATIC INLINE uint32_t Chip_SYSCTL_GetPORPIOStatus(int index)
225 {
226 return LPC_SYSCTL->PIOPORCAP[index];
227 }
228
232 typedef enum CHIP_SYSCTL_BODRSTLVL {
233 #if defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) || defined(CHIP_LPC11XXLV)
234 SYSCTL_BODRSTLVL_1_46V,
235 #else
236 SYSCTL_BODRSTLVL_RESERVED1,
237 #endif
238 #if defined(CHIP_LPC11XXLV)
239 SYSCTL_BODRSTLVL_RESERVED1,
240 SYSCTL_BODRSTLVL_RESERVED2,
241 SYSCTL_BODRSTLVL_RESERVED3,
242 #elif defined(CHIP_LPC11AXX)
243 SYSCTL_BODRSTLVL_RESERVED2,
244 SYSCTL_BODRSTLVL_2_52V,
245 SYSCTL_BODRSTLVL_2_80V,
246 #else
247 SYSCTL_BODRSTLVL_2_06V,
248 SYSCTL_BODRSTLVL_2_35V,
249 SYSCTL_BODRSTLVL_2_63V,
250 #endif
251 } CHIP_SYSCTL_BODRSTLVL_T;
252
256 typedef enum CHIP_SYSCTL_BODRINTVAL {
257 SYSCTL_BODINTVAL_RESERVED1,
258 #if defined(CHIP_LPC110X) || defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
259 SYSCTL_BODINTVAL_2_22V,
260 SYSCTL_BODINTVAL_2_52V,
261 SYSCTL_BODINTVAL_2_80V,
262 #endif
263 } CHIP_SYSCTL_BODRINTVAL_T;
264
273 STATIC INLINE void Chip_SYSCTL_SetBODLevels(CHIP_SYSCTL_BODRSTLVL_T rstlvl,
274 CHIP_SYSCTL_BODRINTVAL_T intlvl)
275 {
276 LPC_SYSCTL->BODCTRL = ((uint32_t) rstlvl) | (((uint32_t) intlvl) << 2);
277 }
278
279 #if defined(CHIP_LPC11AXX)
280
284 STATIC INLINE bool Chip_SYSCTL_GetBODIntStatus(void)
285 {
286 return (bool) ((LPC_SYSCTL->BODCTRL & (1 << 6)) != 0);
287 }
288
289 #else
290
294 STATIC INLINE void Chip_SYSCTL_EnableBODReset(void)
295 {
296 LPC_SYSCTL->BODCTRL |= (1 << 4);
297 }
298
303 STATIC INLINE void Chip_SYSCTL_DisableBODReset(void)
304 {
305 LPC_SYSCTL->BODCTRL &= ~(1 << 4);
306 }
307
308 #endif
309
315 STATIC INLINE void Chip_SYSCTL_SetSYSTCKCAL(uint32_t sysCalVal)
316 {
317 LPC_SYSCTL->SYSTCKCAL = sysCalVal;
318 }
319
320 #if defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
321
328 STATIC INLINE void Chip_SYSCTL_SetIRQLatency(uint32_t latency)
329 {
330 LPC_SYSCTL->IRQLATENCY = latency;
331 }
332
337 STATIC INLINE uint32_t Chip_SYSCTL_GetIRQLatency(void)
338 {
339 return LPC_SYSCTL->IRQLATENCY;
340 }
341
342 #endif
343
344 #if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
345
352 STATIC INLINE void Chip_SYSCTL_SetNMISource(uint32_t intsrc)
353 {
354 LPC_SYSCTL->NMISRC = intsrc;
355 }
356
361 STATIC INLINE void Chip_SYSCTL_EnableNMISource(void)
362 {
363 LPC_SYSCTL->NMISRC |= SYSCTL_NMISRC_ENABLE;
364 }
365
370 STATIC INLINE void Chip_SYSCTL_DisableNMISource(void)
371 {
372 LPC_SYSCTL->NMISRC &= ~(SYSCTL_NMISRC_ENABLE);
373 }
374
375 #endif
376
377 #if defined(CHIP_LPC11AXX)
378
385 STATIC INLINE void Chip_SYSCTL_SetPinInterrupt(uint32_t intno, uint8_t port, uint8_t pin)
386 {
387 LPC_SYSCTL->PINTSEL[intno] = (uint32_t) ((port<<5) | pin);
388 }
389
390 #elif defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
391
398 STATIC INLINE void Chip_SYSCTL_SetPinInterrupt(uint32_t intno, uint8_t port, uint8_t pin)
399
400 {
401 LPC_SYSCTL->PINTSEL[intno] = (uint32_t) (port*24 + pin);
402 }
403 #endif
404
405 #if defined(LPC11Uxx)
406
413 STATIC INLINE void Chip_SYSCTL_SetUSBCLKCTRL(uint32_t ap_clk, uint32_t pol_clk)
414 {
415 LPC_SYSCTL->USBCLKCTRL = ap_clk | (pol_clk << 1);
416 }
417
422 STATIC INLINE bool Chip_SYSCTL_GetUSBCLKStatus(void)
423 {
424 return (bool) ((LPC_SYSCTL->USBCLKST & 0x1) != 0);
425 }
426
427 #endif
428
429 #if defined(CHIP_LPC110X) || defined(CHIP_LPC11XXLV) || defined(CHIP_LPC11CXX)
430
437 STATIC INLINE void Chip_SYSCTL_SetStartPin(uint32_t pin, uint32_t edge)
438 {
439 if (edge) {
440 LPC_SYSCTL->STARTAPRP0 |= (1 << pin);
441 }
442 else {
443 LPC_SYSCTL->STARTAPRP0 &= ~(1 << pin);
444 }
445 }
446
453 STATIC INLINE void Chip_SYSCTL_EnableStartPin(uint32_t pin)
454 {
455 LPC_SYSCTL->STARTERP0 |= (1 << pin);
456 }
457
464 STATIC INLINE void Chip_SYSCTL_DisableStartPin(uint32_t pin)
465 {
466 LPC_SYSCTL->STARTERP0 &= ~(1 << pin);
467 }
468
475 STATIC INLINE void Chip_SYSCTL_ResetStartPin(uint32_t pin)
476 {
477 LPC_SYSCTL->STARTRSRP0CLR = (1 << pin);
478 }
479
486 STATIC INLINE bool Chip_SYSCTL_GetStartPinStatus(uint32_t pin)
487 {
488 return (bool) ((LPC_SYSCTL->STARTSRP0 & (1 << pin)) != 0);
489 }
490
491 #endif
492
493 #if defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
494
500 STATIC INLINE void Chip_SYSCTL_EnablePINTWakeup(uint32_t pin)
501 {
502 LPC_SYSCTL->STARTERP0 |= (1 << pin);
503 }
504
511 STATIC INLINE void Chip_SYSCTL_DisablePINTWakeup(uint32_t pin)
512 {
513 LPC_SYSCTL->STARTERP0 &= ~(1 << pin);
514 }
515
519 #define SYSCTL_WAKEUP_WWDTINT (1 << 12)
520 #define SYSCTL_WAKEUP_BODINT (1 << 13)
521 #define SYSCTL_WAKEUP_USB_WAKEUP (1 << 19)
522 #define SYSCTL_WAKEUP_GPIOINT0 (1 << 20)
523 #define SYSCTL_WAKEUP_GPIOINT1 (1 << 21)
530 STATIC INLINE void Chip_SYSCTL_EnablePeriphWakeup(uint32_t periphmask)
531 {
532 LPC_SYSCTL->STARTERP1 |= periphmask;
533 }
534
540 STATIC INLINE void Chip_SYSCTL_DisablePeriphWakeup(uint32_t periphmask)
541 {
542 LPC_SYSCTL->STARTERP1 &= ~periphmask;
543 }
544
545 #endif
546
547 #if !defined(LPC11AXX)
548
551 #define SYSCTL_DEEPSLP_BOD_PD (1 << 3)
552 #define SYSCTL_DEEPSLP_WDTOSC_PD (1 << 6)
553 #if defined(CHIP_LPC11XXLV)
554 #define SYSCTL_DEEPSLP_IRCOUT_PD (1 << 0)
555 #define SYSCTL_DEEPSLP_IRC_PD (1 << 1)
556 #endif
557
568 void Chip_SYSCTL_SetDeepSleepPD(uint32_t sleepmask);
569
575 STATIC INLINE uint32_t Chip_SYSCTL_GetDeepSleepPD(void)
576 {
577 return LPC_SYSCTL->PDSLEEPCFG;
578 }
579
583 #define SYSCTL_SLPWAKE_IRCOUT_PD (1 << 0)
584 #define SYSCTL_SLPWAKE_IRC_PD (1 << 1)
585 #define SYSCTL_SLPWAKE_FLASH_PD (1 << 2)
586 #define SYSCTL_SLPWAKE_BOD_PD (1 << 3)
587 #define SYSCTL_SLPWAKE_ADC_PD (1 << 4)
588 #define SYSCTL_SLPWAKE_SYSOSC_PD (1 << 5)
589 #define SYSCTL_SLPWAKE_WDTOSC_PD (1 << 6)
590 #define SYSCTL_SLPWAKE_SYSPLL_PD (1 << 7)
591 #if defined(CHIP_LPC11UXX)
592 #define SYSCTL_SLPWAKE_USBPLL_PD (1 << 8)
593 #define SYSCTL_SLPWAKE_USBPAD_PD (1 << 10)
594 #endif
595
606 void Chip_SYSCTL_SetWakeup(uint32_t wakeupmask);
607
613 STATIC INLINE uint32_t Chip_SYSCTL_GetWakeup(void)
614 {
615 return LPC_SYSCTL->PDWAKECFG;
616 }
617
618 #endif
619
623 #define SYSCTL_POWERDOWN_IRCOUT_PD (1 << 0)
624 #define SYSCTL_POWERDOWN_IRC_PD (1 << 1)
625 #define SYSCTL_POWERDOWN_FLASH_PD (1 << 2)
626 #if !defined(CHIP_LPC11AXX)
627 #define SYSCTL_POWERDOWN_BOD_PD (1 << 3)
628 #endif
629 #define SYSCTL_POWERDOWN_ADC_PD (1 << 4)
630 #define SYSCTL_POWERDOWN_SYSOSC_PD (1 << 5)
631 #define SYSCTL_POWERDOWN_WDTOSC_PD (1 << 6)
632 #define SYSCTL_POWERDOWN_SYSPLL_PD (1 << 7)
633 #if defined(CHIP_LPC11UXX)
634 #define SYSCTL_POWERDOWN_USBPLL_PD (1 << 8)
635 #define SYSCTL_POWERDOWN_USBPAD_PD (1 << 10)
636 #endif
637 #if defined(CHIP_LPC11AXX)
638 #define SYSCTL_POWERDOWN_LFOSC_PD (1 << 13)
639 #define SYSCTL_POWERDOWN_DAC_PD (1 << 14)
640 #define SYSCTL_POWERDOWN_TS_PD (1 << 15)
641 #define SYSCTL_POWERDOWN_ACOMP_PD (1 << 16)
642 #endif
643
649 void Chip_SYSCTL_PowerDown(uint32_t powerdownmask);
650
656 void Chip_SYSCTL_PowerUp(uint32_t powerupmask);
657
663 STATIC INLINE uint32_t Chip_SYSCTL_GetPowerStates(void)
664 {
665 return LPC_SYSCTL->PDRUNCFG;
666 }
667
672 STATIC INLINE uint32_t Chip_SYSCTL_GetDeviceID(void)
673 {
674 return LPC_SYSCTL->DEVICEID;
675 }
676
681 #ifdef __cplusplus
682 }
683 #endif
684
685 #endif