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LPC_CREG_T Struct Reference
CHIP: LPC18xx/43xx CREG driver

## Detailed Description

CREG Register Block.

Definition at line 47 of file creg_18xx_43xx.h.

`#include "creg_18xx_43xx.h"`

## Data Fields
__I uint32_t | RESERVED0
__IO uint32_t | CREG0
__I uint32_t | RESERVED1 [62]
__IO uint32_t | MXMEMMAP
__I uint32_t | RESERVED2
__I uint32_t | CREG1
__I uint32_t | CREG2
__I uint32_t | CREG3
__I uint32_t | CREG4
__IO uint32_t | CREG5
__IO uint32_t | DMAMUX
__IO uint32_t | FLASHCFGA
__IO uint32_t | FLASHCFGB
__IO uint32_t | ETBCFG
__IO uint32_t | CREG6
__IO uint32_t | M4TXEVENT
__I uint32_t | RESERVED4 [51]
__I uint32_t | CHIPID
__I uint32_t | RESERVED5 [127]
__IO uint32_t | M0TXEVENT
__IO uint32_t | M0APPMEMMAP
__I uint32_t | RESERVED6 [62]
__IO uint32_t | USB0FLADJ
__I uint32_t | RESERVED7 [63]
__IO uint32_t | USB1FLADJ

## Field Documentation

__I uint32_t CHIPID

Part ID

Definition at line 73 of file creg_18xx_43xx.h.

__IO uint32_t CREG0

Chip configuration register 32 kHz oscillator output and BOD control register.

Definition at line 49 of file creg_18xx_43xx.h.

__I uint32_t CREG1

Configuration Register 1

Definition at line 56 of file creg_18xx_43xx.h.

__I uint32_t CREG2

Configuration Register 2

Definition at line 57 of file creg_18xx_43xx.h.

__I uint32_t CREG3

Configuration Register 3

Definition at line 58 of file creg_18xx_43xx.h.

__I uint32_t CREG4

Configuration Register 4

Definition at line 59 of file creg_18xx_43xx.h.

__IO uint32_t CREG5

Chip configuration register 5. Controls JTAG access.

Definition at line 61 of file creg_18xx_43xx.h.

__IO uint32_t CREG6

Chip configuration register 6.

Definition at line 66 of file creg_18xx_43xx.h.

__IO uint32_t DMAMUX

DMA muxing control

Definition at line 62 of file creg_18xx_43xx.h.

__IO uint32_t ETBCFG

ETB RAM configuration

Definition at line 65 of file creg_18xx_43xx.h.

__IO uint32_t FLASHCFGA

Flash accelerator configuration register for flash bank A

Definition at line 63 of file creg_18xx_43xx.h.

__IO uint32_t FLASHCFGB

Flash accelerator configuration register for flash bank B

Definition at line 64 of file creg_18xx_43xx.h.

__IO uint32_t M0APPMEMMAP

ARM Cortex M0 memory mapping

Definition at line 79 of file creg_18xx_43xx.h.

__IO uint32_t M0TXEVENT

M0 IPC Event register

Definition at line 78 of file creg_18xx_43xx.h.

__IO uint32_t M4TXEVENT

M4 IPC event register

Definition at line 70 of file creg_18xx_43xx.h.

__IO uint32_t MXMEMMAP

ARM Cortex-M3/M4 memory mapping

Definition at line 51 of file creg_18xx_43xx.h.

__I uint32_t RESERVED0

< CREG Structure

Definition at line 48 of file creg_18xx_43xx.h.

__I uint32_t RESERVED1[62]

Definition at line 50 of file creg_18xx_43xx.h.

__I uint32_t RESERVED2

Definition at line 55 of file creg_18xx_43xx.h.

__I uint32_t RESERVED4[51]

Definition at line 71 of file creg_18xx_43xx.h.

__I uint32_t RESERVED5[127]

Definition at line 77 of file creg_18xx_43xx.h.

__I uint32_t RESERVED6[62]

Definition at line 80 of file creg_18xx_43xx.h.

__I uint32_t RESERVED7[63]

Definition at line 83 of file creg_18xx_43xx.h.

__IO uint32_t USB0FLADJ

USB0 frame length adjust register

Definition at line 82 of file creg_18xx_43xx.h.

__IO uint32_t USB1FLADJ

USB1 frame length adjust register

Definition at line 84 of file creg_18xx_43xx.h.

The documentation for this struct was generated from the following file:

- C:/nxp/v1.03/lpcopen_v1.03/lpcopen/software/lpc_core/lpc_chip/chip_18xx_43xx/creg_18xx_43xx.h