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i2c_001.h
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1 /*
2 * @brief I2C registers and driver functions
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __I2C_001_H_
33 #define __I2C_001_H_
34
35 #include "sys_config.h"
36 #include "cmsis.h"
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
50 typedef struct { /* I2C0 Structure */
51 __IO uint32_t CONSET;
52 __I uint32_t STAT;
53 __IO uint32_t DAT;
54 __IO uint32_t ADR0;
55 __IO uint32_t SCLH;
56 __IO uint32_t SCLL;
57 __O uint32_t CONCLR;
58 __IO uint32_t MMCTRL;
59 __IO uint32_t ADR1;
60 __IO uint32_t ADR2;
61 __IO uint32_t ADR3;
62 __I uint32_t DATA_BUFFER;
63 __IO uint32_t MASK[4];
64 } IP_I2C_001_T;
65
71 #define RET_SLAVE_TX 6
72 #define RET_SLAVE_RX 5
73 #define RET_SLAVE_IDLE 2
74 #define RET_SLAVE_BUSY 0
79 #define I2C_STA_STO_RECV 0x20
80
81 /*
82 * @brief I2C Control Set register description
83 */
84 #define I2C_I2CONSET_AA ((0x04))
85 #define I2C_I2CONSET_SI ((0x08))
86 #define I2C_I2CONSET_STO ((0x10))
87 #define I2C_I2CONSET_STA ((0x20))
88 #define I2C_I2CONSET_I2EN ((0x40))
90 /*
91 * @brief I2C Control Clear register description
92 */
93 #define I2C_I2CONCLR_AAC ((1 << 2))
94 #define I2C_I2CONCLR_SIC ((1 << 3))
95 #define I2C_I2CONCLR_STOC ((1 << 4))
96 #define I2C_I2CONCLR_STAC ((1 << 5))
97 #define I2C_I2CONCLR_I2ENC ((1 << 6))
99 /*
100 * @brief I2C Common Control register description
101 */
102 #define I2C_CON_AA (1UL << 2)
103 #define I2C_CON_SI (1UL << 3)
104 #define I2C_CON_STO (1UL << 4)
105 #define I2C_CON_STA (1UL << 5)
106 #define I2C_CON_I2EN (1UL << 6)
108 /*
109 * @brief I2C Status Code definition (I2C Status register)
110 */
111 #define I2C_STAT_CODE_BITMASK ((0xF8))
112 #define I2C_STAT_CODE_ERROR ((0xFF))
114 /*
115 * @brief I2C return status code definitions
116 */
117 #define I2C_I2STAT_NO_INF ((0xF8))
118 #define I2C_I2STAT_BUS_ERROR ((0x00))
120 /*
121 * @brief I2C Master transmit mode
122 */
123 #define I2C_I2STAT_M_TX_START ((0x08))
124 #define I2C_I2STAT_M_TX_RESTART ((0x10))
125 #define I2C_I2STAT_M_TX_SLAW_ACK ((0x18))
126 #define I2C_I2STAT_M_TX_SLAW_NACK ((0x20))
127 #define I2C_I2STAT_M_TX_DAT_ACK ((0x28))
128 #define I2C_I2STAT_M_TX_DAT_NACK ((0x30))
129 #define I2C_I2STAT_M_TX_ARB_LOST ((0x38))
131 /*
132 * @brief I2C Master receive mode
133 */
134 #define I2C_I2STAT_M_RX_START ((0x08))
135 #define I2C_I2STAT_M_RX_RESTART ((0x10))
136 #define I2C_I2STAT_M_RX_ARB_LOST ((0x38))
137 #define I2C_I2STAT_M_RX_SLAR_ACK ((0x40))
138 #define I2C_I2STAT_M_RX_SLAR_NACK ((0x48))
139 #define I2C_I2STAT_M_RX_DAT_ACK ((0x50))
140 #define I2C_I2STAT_M_RX_DAT_NACK ((0x58))
142 /*
143 * @brief I2C Slave receive mode
144 */
145 #define I2C_I2STAT_S_RX_SLAW_ACK ((0x60))
146 #define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68))
147 // #define I2C_I2STAT_S_RX_SLAW_ACK ((0x68))
148 #define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70))
149 #define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78))
150 // #define I2C_I2STAT_S_RX_GENCALL_ACK ((0x78))
151 #define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80))
152 #define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88))
153 #define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90))
154 #define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98))
155 #define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0))
158 /*
159 * @brief I2C Slave transmit mode
160 */
161 #define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8))
162 #define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0))
163 // #define I2C_I2STAT_S_TX_SLAR_ACK ((0xB0))
164 #define I2C_I2STAT_S_TX_DAT_ACK ((0xB8))
165 #define I2C_I2STAT_S_TX_DAT_NACK ((0xC0))
166 #define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8))
167 #define I2C_SLAVE_TIME_OUT 0x10000000UL
169 /*
170 * @brief I2C Data register definition
171 */
172 #define I2C_I2DAT_BITMASK ((0xFF))
173 #define I2C_I2DAT_IDLE_CHAR (0xFF)
176 /*
177 * @brief I2C Monitor mode control register description
178 */
179 #define I2C_I2MMCTRL_MM_ENA ((1 << 0))
180 #define I2C_I2MMCTRL_ENA_SCL ((1 << 1))
181 #define I2C_I2MMCTRL_MATCH_ALL ((1 << 2))
182 #define I2C_I2MMCTRL_BITMASK ((0x07))
184 /*
185 * @brief I2C Data buffer register description
186 */
187 #define I2DATA_BUFFER_BITMASK ((0xFF))
189 /*
190 * @brief I2C Slave Address registers definition
191 */
192 #define I2C_I2ADR_GC ((1 << 0))
193 #define I2C_I2ADR_BITMASK ((0xFF))
195 /*
196 * @brief I2C Mask Register definition
197 */
198 #define I2C_I2MASK_MASK(n) ((n & 0xFE))
200 /*
201 * @brief I2C SCL HIGH duty cycle Register definition
202 */
203 #define I2C_I2SCLH_BITMASK ((0xFFFF))
205 /*
206 * @brief I2C SCL LOW duty cycle Register definition
207 */
208 #define I2C_I2SCLL_BITMASK ((0xFFFF))
210 /*
211 * @brief I2C status values
212 */
213 #define I2C_SETUP_STATUS_ARBF (1 << 8)
214 #define I2C_SETUP_STATUS_NOACKF (1 << 9)
215 #define I2C_SETUP_STATUS_DONE (1 << 10)
217 /*
218 * @brief I2C state handle return values
219 */
220 #define I2C_OK 0x00
221 #define I2C_BYTE_SENT 0x01
222 #define I2C_BYTE_RECV 0x02
223 #define I2C_LAST_BYTE_RECV 0x04
224 #define I2C_SEND_END 0x08
225 #define I2C_RECV_END 0x10
226 #define I2C_STA_STO_RECV 0x20
227
228 #define I2C_ERR (0x10000000)
229 #define I2C_NAK_RECV (0x10000000 | 0x01)
230
231 #define I2C_CheckError(ErrorCode) (ErrorCode & 0x10000000)
232
233 /*
234 * @brief I2C monitor control configuration defines
235 */
236 #define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL
237 #define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL
242 typedef enum {
243 I2C_SLAVE_GENERAL,
244 I2C_SLAVE_0,
245 I2C_SLAVE_1,
246 I2C_SLAVE_2,
247 I2C_SLAVE_3,
248 I2C_SLAVE_NUM_INTERFACE
249 } I2C_SLAVE_ID;
250
254 typedef enum {
255 I2C_STATUS_DONE,
256 I2C_STATUS_NAK,
257 I2C_STATUS_ARBLOST,
258 I2C_STATUS_BUSERR,
259 I2C_STATUS_BUSY,
260 } I2C_STATUS_T;
261
265 typedef struct {
266 uint8_t slaveAddr;
267 const uint8_t *txBuff;
268 int txSz;
270 uint8_t *rxBuff;
271 int rxSz;
273 I2C_STATUS_T status;
274 } I2C_XFER_T;
275
281 STATIC INLINE void IP_I2C_Init(IP_I2C_001_T *pI2C)
282 {
283 /* Set I2C operation to default */
284 pI2C->CONCLR = (I2C_CON_AA | I2C_CON_SI | I2C_CON_STA | I2C_CON_I2EN);
285 }
286
292 STATIC INLINE void IP_I2C_DeInit(IP_I2C_001_T *pI2C)
293 {
294 /* Disable I2C control */
295 pI2C->CONCLR = I2C_CON_I2EN | I2C_CON_SI | I2C_CON_STO | I2C_CON_STA | I2C_CON_AA;
296 }
297
304 STATIC INLINE void IP_I2C_SetClockRate(IP_I2C_001_T *pI2C, uint32_t SCLValue)
305 {
306 pI2C->SCLH = (uint32_t) (SCLValue >> 1);
307 pI2C->SCLL = (uint32_t) (SCLValue - pI2C->SCLH);
308 }
309
315 STATIC INLINE uint32_t IP_I2C_GetClockDiv(IP_I2C_001_T *pI2C)
316 {
317 return pI2C->SCLH + pI2C->SCLL;
318 }
319
325 STATIC INLINE void IP_I2C_Master_StartXfer(IP_I2C_001_T *pI2C)
326 {
327 /* Reset STA, STO, SI */
328 pI2C->CONCLR = I2C_CON_SI | I2C_CON_STO | I2C_CON_STA | I2C_CON_AA;
329
330 /* Enter to Master Transmitter mode */
331 pI2C->CONSET = I2C_CON_I2EN | I2C_CON_STA;
332 }
333
344 int IP_I2C_MasterXfer_StateHandler(IP_I2C_001_T *pI2C, I2C_XFER_T *xfer);
345
351 STATIC INLINE int IP_I2C_IsStateChanged(IP_I2C_001_T *pI2C)
352 {
353 return (pI2C->CONSET & I2C_CON_SI) != 0;
354 }
355
361 STATIC INLINE void IP_I2C_Disable(IP_I2C_001_T *pI2C)
362 {
363 pI2C->CONCLR = I2C_I2CONCLR_I2ENC;
364 }
365
375 STATIC INLINE void IP_I2C_SetSlaveAddress(IP_I2C_001_T *pI2C, I2C_SLAVE_ID sid, uint8_t addr, uint8_t mask)
376 {
377 uint32_t index = (uint32_t) sid - 1;
378 pI2C->MASK[index] = mask;
379 if (sid == I2C_SLAVE_0) {
380 pI2C->ADR0 = addr;
381 }
382 else {
383 volatile uint32_t *abase = &pI2C->ADR1;
384 abase[index - 1] = addr;
385 }
386 }
387
393 STATIC INLINE int IP_I2C_GetCurrentState(IP_I2C_001_T *pI2C)
394 {
395 return (int) (pI2C->STAT & I2C_STAT_CODE_BITMASK);
396 }
397
403 I2C_SLAVE_ID IP_I2C_GetSlaveIndex(IP_I2C_001_T *pI2C);
404
420 int IP_I2C_SlaveXfer_StateHandler(IP_I2C_001_T *pI2C, I2C_XFER_T *xfer);
421
427 STATIC INLINE void IP_I2C_Slave_StartXfer(IP_I2C_001_T *pI2C)
428 {
429 /* Reset STA, STO, SI */
430 pI2C->CONCLR = I2C_CON_SI | I2C_CON_STO | I2C_CON_STA;
431
432 /* Enter to Master Transmitter mode */
433 pI2C->CONSET = I2C_CON_I2EN | I2C_CON_AA;
434 }
435
441 STATIC INLINE int IP_I2C_BusFree(IP_I2C_001_T *pI2C)
442 {
443 return !(pI2C->CONSET & I2C_CON_STO);
444 }
445
451 STATIC INLINE int IP_I2C_IsMasterState(IP_I2C_001_T *pI2C)
452 {
453 return IP_I2C_GetCurrentState(pI2C) < 0x60;
454 }
455
460 #ifdef __cplusplus
461 }
462 #endif
463
464 #endif /* __I2C_001_H_ */