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usart_001.h
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1 /*
2 * @brief UART/USART Registers and control functions
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __USART_001_H_
33 #define __USART_001_H_
34
35 #include "sys_config.h"
36 #include "cmsis.h"
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
50 typedef struct {
52 union {
53 __IO uint32_t DLL;
54 __O uint32_t THR;
55 __I uint32_t RBR;
56 };
57
58 union {
59 __IO uint32_t IER;
60 __IO uint32_t DLM;
61 };
62
63 union {
64 __O uint32_t FCR;
65 __I uint32_t IIR;
66 };
67
68 __IO uint32_t LCR;
69 __IO uint32_t MCR;
70 __I uint32_t LSR;
71 __I uint32_t MSR;
72 __IO uint32_t SCR;
73 __IO uint32_t ACR;
74 __IO uint32_t ICR;
75 __IO uint32_t FDR;
76 __IO uint32_t OSR;
77 __IO uint32_t TER1;
78 uint32_t RESERVED0[3];
79 __IO uint32_t HDEN;
80 __I uint32_t RESERVED1[1];
81 __IO uint32_t SCICTRL;
82 __IO uint32_t RS485CTRL;
83 __IO uint32_t RS485ADRMATCH;
84 __IO uint32_t RS485DLY;
85 union {
86 __IO uint32_t SYNCCTRL;
87 __I uint32_t FIFOLVL;
88 };
89
90 #if !defined CHIP_LPC11XX
91 __IO uint32_t TER2;
92 #endif
93 } IP_USART_001_T;
94
95 #define UART_BLOCKING_TIMEOUT (0xFFFFFFFFUL)
97 #define UART_ACCEPTED_BAUDRATE_ERROR (3)
99 /* --------------------- BIT DEFINITIONS -------------------------------------- */
100
103 #define UART_RBR_MASKBIT ((uint8_t) 0xFF)
108 #define UART_THR_MASKBIT ((uint8_t) 0xFF)
113 #define UART_LOAD_DLL(div) ((div) & 0xFF)
114 #define UART_DLL_MASKBIT ((uint8_t) 0xFF)
119 #define UART_DLM_MASKBIT ((uint8_t) 0xFF)
120 #define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF)
125 #define UART_IER_RBRINT_EN ((uint32_t) (1 << 0))
126 #define UART_IER_THREINT_EN ((uint32_t) (1 << 1))
127 #define UART_IER_RLSINT_EN ((uint32_t) (1 << 2))
128 #define UART_IER_MSINT_EN ((uint32_t) (1 << 3))
129 #define UART_IER_CTSINT_EN ((uint32_t) (1 << 7))
130 #define UART_IER_ABEOINT_EN ((uint32_t) (1 << 8))
131 #define UART_IER_ABTOINT_EN ((uint32_t) (1 << 9))
132 #define UART_IER_BITMASK ((uint32_t) (0x307))
133 #define UART1_IER_BITMASK ((uint32_t) (0x38F))
138 #define UART_IIR_INTSTAT_PEND ((uint32_t) (1 << 0))
139 #define UART_IIR_INTID_RLS ((uint32_t) (3 << 1))
140 #define UART_IIR_INTID_RDA ((uint32_t) (2 << 1))
141 #define UART_IIR_INTID_CTI ((uint32_t) (6 << 1))
142 #define UART_IIR_INTID_THRE ((uint32_t) (1 << 1))
143 #define UART_IIR_INTID_MODEM ((uint32_t) (0 << 1))
144 #define UART_IIR_INTID_MASK ((uint32_t) (7 << 1))
145 #define UART_IIR_FIFO_EN ((uint32_t) (3 << 6))
146 #define UART_IIR_ABEO_INT ((uint32_t) (1 << 8))
147 #define UART_IIR_ABTO_INT ((uint32_t) (1 << 9))
148 #define UART_IIR_BITMASK ((uint32_t) (0x3CF))
153 #define UART_FCR_FIFO_EN ((uint8_t) (1 << 0))
154 #define UART_FCR_RX_RS ((uint8_t) (1 << 1))
155 #define UART_FCR_TX_RS ((uint8_t) (1 << 2))
156 #define UART_FCR_DMAMODE_SEL ((uint8_t) (1 << 3))
157 #define UART_FCR_TRG_LEV0 ((uint8_t) (0))
158 #define UART_FCR_TRG_LEV1 ((uint8_t) (1 << 6))
159 #define UART_FCR_TRG_LEV2 ((uint8_t) (2 << 6))
160 #define UART_FCR_TRG_LEV3 ((uint8_t) (3 << 6))
161 #define UART_FCR_BITMASK ((uint8_t) (0xCF))
162 #define UART_TX_FIFO_SIZE (16)
163
167 #define UART_LCR_WLEN5 ((uint8_t) (0))
168 #define UART_LCR_WLEN6 ((uint8_t) (1 << 0))
169 #define UART_LCR_WLEN7 ((uint8_t) (2 << 0))
170 #define UART_LCR_WLEN8 ((uint8_t) (3 << 0))
171 #define UART_LCR_SBS_1BIT ((uint8_t) (0 << 2))
172 #define UART_LCR_SBS_2BIT ((uint8_t) (1 << 2))
173 #define UART_LCR_PARITY_EN ((uint8_t) (1 << 3))
174 #define UART_LCR_PARITY_DIS ((uint8_t) (0 << 3))
175 #define UART_LCR_PARITY_ODD ((uint8_t) (0))
176 #define UART_LCR_PARITY_EVEN ((uint8_t) (1 << 4))
177 #define UART_LCR_PARITY_F_1 ((uint8_t) (2 << 4))
178 #define UART_LCR_PARITY_F_0 ((uint8_t) (3 << 4))
179 #define UART_LCR_BREAK_EN ((uint8_t) (1 << 6))
180 #define UART_LCR_DLAB_EN ((uint8_t) (1 << 7))
181 #define UART_LCR_BITMASK ((uint8_t) (0xFF))
186 #define UART_MCR_DTR_CTRL ((uint8_t) (1 << 0))
187 #define UART_MCR_RTS_CTRL ((uint8_t) (1 << 1))
188 #define UART_MCR_LOOPB_EN ((uint8_t) (1 << 4))
189 #define UART_MCR_AUTO_RTS_EN ((uint8_t) (1 << 6))
190 #define UART_MCR_AUTO_CTS_EN ((uint8_t) (1 << 7))
191 #define UART_MCR_BITMASK ((uint8_t) (0x0F3))
196 #define UART_LSR_RDR ((uint8_t) (1 << 0))
197 #define UART_LSR_OE ((uint8_t) (1 << 1))
198 #define UART_LSR_PE ((uint8_t) (1 << 2))
199 #define UART_LSR_FE ((uint8_t) (1 << 3))
200 #define UART_LSR_BI ((uint8_t) (1 << 4))
201 #define UART_LSR_THRE ((uint8_t) (1 << 5))
202 #define UART_LSR_TEMT ((uint8_t) (1 << 6))
203 #define UART_LSR_RXFE ((uint8_t) (1 << 7))
204 #define UART_LSR_BITMASK ((uint8_t) (0xFF))
209 #define UART_MSR_DELTA_CTS ((uint8_t) (1 << 0))
210 #define UART_MSR_DELTA_DSR ((uint8_t) (1 << 1))
211 #define UART_MSR_LO2HI_RI ((uint8_t) (1 << 2))
212 #define UART_MSR_DELTA_DCD ((uint8_t) (1 << 3))
213 #define UART_MSR_CTS ((uint8_t) (1 << 4))
214 #define UART_MSR_DSR ((uint8_t) (1 << 5))
215 #define UART_MSR_RI ((uint8_t) (1 << 6))
216 #define UART_MSR_DCD ((uint8_t) (1 << 7))
217 #define UART_MSR_BITMASK ((uint8_t) (0xFF))
222 #define UART_SCR_BIMASK ((uint8_t) (0xFF))
227 #define UART_ACR_START ((uint32_t) (1 << 0))
228 #define UART_ACR_MODE ((uint32_t) (1 << 1))
229 #define UART_ACR_AUTO_RESTART ((uint32_t) (1 << 2))
230 #define UART_ACR_ABEOINT_CLR ((uint32_t) (1 << 8))
231 #define UART_ACR_ABTOINT_CLR ((uint32_t) (1 << 9))
232 #define UART_ACR_BITMASK ((uint32_t) (0x307))
237 #define UART_ICR_IRDAEN ((uint32_t) (1 << 0))
238 #define UART_ICR_IRDAINV ((uint32_t) (1 << 1))
239 #define UART_ICR_FIXPULSE_EN ((uint32_t) (1 << 2))
240 #define UART_ICR_PULSEDIV(n) ((uint32_t) ((n & 0x07) << 3))
241 #define UART_ICR_BITMASK ((uint32_t) (0x3F))
246 #define UART_HDEN_HDEN ((uint32_t) (1 << 0))
251 #define UART_SCICTRL_SCIEN ((uint32_t) (1 << 0))
252 #define UART_SCICTRL_NACKDIS ((uint32_t) (1 << 1))
253 #define UART_SCICTRL_PROTSEL_T1 ((uint32_t) (1 << 2))
254 #define UART_SCICTRL_TXRETRY(n) ((uint32_t) ((n & 0x07) << 5))
255 #define UART_SCICTRL_GUARDTIME(n) ((uint32_t) ((n & 0xFF) << 8))
260 #define UART_SYNCCTRL_SYNC ((uint32_t) (1 << 0))
261 #define UART_SYNCCTRL_CSRC_MASTER ((uint32_t) (1 << 1))
262 #define UART_SYNCCTRL_FES ((uint32_t) (1 << 2))
263 #define UART_SYNCCTRL_TSBYPASS ((uint32_t) (1 << 3))
264 #define UART_SYNCCTRL_CSCEN ((uint32_t) (1 << 4))
265 #define UART_SYNCCTRL_STARTSTOPDISABLE ((uint32_t) (1 << 5))
266 #define UART_SYNCCTRL_CCCLR ((uint32_t) (1 << 6))
271 #define UART_FDR_DIVADDVAL(n) ((uint32_t) (n & 0x0F))
272 #define UART_FDR_MULVAL(n) ((uint32_t) ((n << 4) & 0xF0))
273 #define UART_FDR_BITMASK ((uint32_t) (0xFF))
278 #define UART_TER1_TXEN ((uint8_t) (1 << 7))
279 #define UART_TER1_BITMASK ((uint8_t) (0x80))
280 #define UART_TER2_TXEN ((uint8_t) (1 << 0))
281 #define UART_TER2_BITMASK ((uint8_t) (0x01))
286 #define UART_RS485CTRL_NMM_EN ((uint32_t) (1 << 0))
287 #define UART_RS485CTRL_RX_DIS ((uint32_t) (1 << 1))
288 #define UART_RS485CTRL_AADEN ((uint32_t) (1 << 2))
289 #define UART_RS485CTRL_SEL_DTR ((uint32_t) (1 << 3))
291 #define UART_RS485CTRL_DCTRL_EN ((uint32_t) (1 << 4))
292 #define UART_RS485CTRL_OINV_1 ((uint32_t) (1 << 5))
295 #define UART_RS485CTRL_BITMASK ((uint32_t) (0x3F))
300 #define UART_RS485ADRMATCH_BITMASK ((uint8_t) (0xFF))
305 #define UART_RS485DLY_BITMASK ((uint8_t) (0xFF))
310 #define UART_FIFOLVL_RXFIFOLVL(n) ((uint32_t) (n & 0x0F))
311 #define UART_FIFOLVL_TXFIFOLVL(n) ((uint32_t) ((n >> 8) & 0x0F))
312 #define UART_FIFOLVL_BITMASK ((uint32_t) (0x0F0F))
317 #define UART_RING_BUFSIZE 256
318 #define __BUF_MASK (UART_RING_BUFSIZE - 1)
319 #define __BUF_IS_FULL(head, tail) ((tail & __BUF_MASK) == ((head + 1) & __BUF_MASK))
320 #define __BUF_WILL_FULL(head, tail) ((tail & __BUF_MASK) == ((head + 2) & __BUF_MASK))
321 #define __BUF_IS_EMPTY(head, tail) ((head & __BUF_MASK) == (tail & __BUF_MASK))
322 #define __BUF_RESET(bufidx) (bufidx = 0)
323 #define __BUF_INCR(bufidx) (bufidx = (bufidx + 1) & __BUF_MASK)
328 typedef struct {
329 __IO uint32_t tx_head;
330 __IO uint32_t tx_tail;
331 __IO uint32_t rx_head;
332 __IO uint32_t rx_tail;
333 __IO uint8_t tx[UART_RING_BUFSIZE];
334 __IO uint8_t rx[UART_RING_BUFSIZE];
335 } UART_RingBuffer_T;
336
340 typedef enum IP_UART_LS {
341 UART_LINESTAT_RDR = UART_LSR_RDR,
342 UART_LINESTAT_OE = UART_LSR_OE,
343 UART_LINESTAT_PE = UART_LSR_PE,
344 UART_LINESTAT_FE = UART_LSR_FE,
345 UART_LINESTAT_BI = UART_LSR_BI,
346 UART_LINESTAT_THRE = UART_LSR_THRE,
347 UART_LINESTAT_TEMT = UART_LSR_TEMT,
348 UART_LINESTAT_RXFE = UART_LSR_RXFE
349 } IP_UART_LS_T;
350
354 typedef enum IP_UART_SIGNAL_STATE {
355 INACTIVE = 0,
356 ACTIVE = !INACTIVE
357 } IP_UART_SIGNAL_STATE_T;
358
362 typedef enum IP_UART_MODEM_STAT {
363 UART_MODEM_STAT_DELTA_CTS = UART_MSR_DELTA_CTS,
364 UART_MODEM_STAT_DELTA_DSR = UART_MSR_DELTA_DSR,
365 UART_MODEM_STAT_LO2HI_RI = UART_MSR_LO2HI_RI,
366 UART_MODEM_STAT_DELTA_DCD = UART_MSR_DELTA_DCD,
367 UART_MODEM_STAT_CTS = UART_MSR_CTS,
368 UART_MODEM_STAT_DSR = UART_MSR_DSR,
369 UART_MODEM_STAT_RI = UART_MSR_RI,
370 UART_MODEM_STAT_DCD = UART_MSR_DCD
371 } IP_UART_MODEM_STAT_T;
372
376 typedef enum IP_UART_MODEM_PIN {
377 UART_MODEM_PIN_DTR = 0,
378 UART_MODEM_PIN_RTS
379 } IP_UART_MODEM_PIN_T;
380
384 typedef enum IP_UART_MODEM_MODE {
385 UART_MODEM_MODE_LOOPBACK = 0,
386 UART_MODEM_MODE_AUTO_RTS,
387 UART_MODEM_MODE_AUTO_CTS
388 } IP_UART_MODEM_MODE_T;
389
393 typedef enum IP_UART_INT {
394 UART_INTCFG_RBR = 0,
395 UART_INTCFG_THRE,
396 UART_INTCFG_RLS,
397 UART_INTCFG_MS,
398 UART_INTCFG_CTS,
399 UART_INTCFG_ABEO,
400 UART_INTCFG_ABTO
401 } IP_UART_INT_T;
402
406 typedef enum IP_UART_PARITY {
407 UART_PARITY_NONE = 0,
408 UART_PARITY_ODD = (4 << 3),
409 UART_PARITY_EVEN = (5 << 3),
410 UART_PARITY_SP_1 = (6 << 3),
411 UART_PARITY_SP_0 = (7 << 3)
412 } IP_UART_PARITY_T;
413
417 typedef enum IP_UART_FITO_LEVEL {
418 UART_FIFO_TRGLEV0 = 0,
419 UART_FIFO_TRGLEV1,
420 UART_FIFO_TRGLEV2,
421 UART_FIFO_TRGLEV3
422 } IP_UART_FITO_LEVEL_T;
423
427 typedef enum IP_UART_STOPBIT {
428 UART_STOPBIT_1 = 0,
429 UART_STOPBIT_2 = (1 << 2)
430 } IP_UART_STOPBIT_T;
431
435 typedef enum IP_UART_DATABIT {
436 UART_DATABIT_5 = 0,
437 UART_DATABIT_6,
438 UART_DATABIT_7,
439 UART_DATABIT_8
440 } IP_UART_DATABIT_T;
441
445 typedef enum IP_UART_ID {
446 UART_0 = 0,
447 UART_1,
448 UART_2,
449 UART_3,
450 UART_4,
451 } IP_UART_ID_T;
452
456 typedef enum IP_UART_INT_STATUS {
457 UART_INTSTS_ERROR = 1 << 0,
458 UART_INTSTS_RTS = 1 << 1,
459 UART_INTSTS_RTR = 1 << 2,
460 UART_INTSTS_ABEO = UART_IIR_ABEO_INT,
461 UART_INTSTS_ABTO = UART_IIR_ABTO_INT
462 } IP_UART_INT_STATUS_T;
463
467 typedef enum IP_UART_AB_MODE {
468 UART_AUTOBAUD_MODE0 = 0,
469 UART_AUTOBAUD_MODE1,
470 } IP_UART_AB_MODE_T;
471
475 typedef struct {
476 IP_UART_AB_MODE_T ABMode;
477 FunctionalState AutoRestart;
478 } UART_AB_CFG_T;
479
483 typedef struct {
484 FunctionalState FIFO_ResetRxBuf;
488 FunctionalState FIFO_ResetTxBuf;
492 FunctionalState FIFO_DMAMode;
496 IP_UART_FITO_LEVEL_T FIFO_Level;
502 } UART_FIFO_CFG_T;
503
510 void IP_UART_Init(IP_USART_001_T *pUART, IP_UART_ID_T UARTPort);
511
518 void IP_UART_DeInit(IP_USART_001_T *pUART, IP_UART_ID_T UARTPort);
519
527 Status IP_UART_SetBaud(IP_USART_001_T *pUART, uint32_t baudrate, uint32_t uClk);
528
548 void IP_UART_ConfigData(IP_USART_001_T *pUART,
549 IP_UART_DATABIT_T Databits,
550 IP_UART_PARITY_T Parity,
551 IP_UART_STOPBIT_T Stopbits);
552
553 /* UART Send/Receive functions -------------------------------------------------*/
560 Status IP_UART_SendByte(IP_USART_001_T *pUART, uint8_t data);
561
568 Status IP_UART_ReceiveByte(IP_USART_001_T *pUART, uint8_t *Data);
569
581 uint32_t IP_UART_Send(IP_USART_001_T *pUART, uint8_t *txbuf, uint32_t buflen, TRANSFER_BLOCK_T flag);
582
594 uint32_t IP_UART_Receive(IP_USART_001_T *pUART, uint8_t *rxbuf, uint32_t buflen, TRANSFER_BLOCK_T flag);
595
596 /* UART operate functions -------------------------------------------------------*/
613 void IP_UART_IntConfig(IP_USART_001_T *pUART, IP_UART_INT_T UARTIntCfg, FunctionalState NewState);
614
620 uint32_t IP_UART_IntGetStatus(IP_USART_001_T *pUART);
621
627 void IP_UART_ForceBreak(IP_USART_001_T *pUART);
628
640 uint8_t IP_UART_GetLineStatus(IP_USART_001_T *pUART);
641
647 FlagStatus IP_UART_CheckBusy(IP_USART_001_T *pUART);
648
656 void IP_UART_TxCmd(IP_USART_001_T *pUART, IP_UART_ID_T UARTPort, FunctionalState NewState);
657
658 /* UART FIFO functions ----------------------------------------------------------*/
665 void IP_UART_FIFOConfig(IP_USART_001_T *pUART, UART_FIFO_CFG_T *FIFOCfg);
666
677 void IP_UART_FIFOConfigStructInit(UART_FIFO_CFG_T *UART_FIFOInitStruct);
678
688 void IP_UART_ABCmd(IP_USART_001_T *pUART, UART_AB_CFG_T *ABConfigStruct, FunctionalState NewState);
689
698 void IP_UART_ABClearIntPending(IP_USART_001_T *pUART, IP_UART_INT_STATUS_T ABIntType);
699
704 #ifdef __cplusplus
705 }
706 #endif
707
708 #endif /* __USART_001_H_ */