| LPCOpen Platform v1.03 LPCOpen Platform for NXP LPC Microcontrollers

- Main Page
- Modules
- Data Structures
- Files
- Related Pages

- File List
- Globals

All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
cmsis.h
Go to the documentation of this file.
1 /*
2 * @brief Basic CMSIS include file
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __CMSIS_H_
33 #define __CMSIS_H_
34
35 #include "lpc_types.h"
36 #include "sys_config.h"
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
47 #if defined(__ARMCC_VERSION)
48 // Kill warning "#pragma push with no matching #pragma pop"
49 #pragma diag_suppress 2525
50 #pragma push
51 #pragma anon_unions
52 #elif defined(__CWCC__)
53 #pragma push
54 #pragma cpp_extensions on
55 #elif defined(__GNUC__)
56 /* anonymous unions are enabled by default */
57 #elif defined(__IAR_SYSTEMS_ICC__)
58 // #pragma push // FIXME not usable for IAR
59 #pragma language=extended
60 #else
61 #error Not supported compiler type
62 #endif
63
64 /*
65 * ==========================================================================
66 * ---------- Interrupt Number Definition -----------------------------------
67 * ==========================================================================
68 */
69 #if defined(CHIP_LPC110X)
70
75 typedef enum IRQn {
76 NonMaskableInt_IRQn = -14,
77 HardFault_IRQn = -13,
78 SVCall_IRQn = -5,
79 PendSV_IRQn = -2,
80 SysTick_IRQn = -1,
82 PIO0_0_IRQn = 0,
83 RESERVED1_IRQn = 1,
84 RESERVED2_IRQn = 2,
85 RESERVED3_IRQn = 3,
86 RESERVED4_IRQn = 4,
87 RESERVED5_IRQn = 5,
88 RESERVED6_IRQn = 6,
89 RESERVED7_IRQn = 7,
90 PIO0_8_IRQn = 8,
91 PIO0_9_IRQn = 9,
92 PIO0_10_IRQn = 10,
93 PIO0_11_IRQn = 11,
94 PIO1_0_IRQn = 12,
95 RESERVED13_IRQn = 13,
96 RESERVED14_IRQn = 14,
97 RESERVED15_IRQn = 15,
98 TIMER_16_0_IRQn = 16,
99 TIMER_16_1_IRQn = 17,
100 TIMER_32_0_IRQn = 18,
101 TIMER_32_1_IRQn = 19,
102 SSP0_IRQn = 20,
103 UART0_IRQn = 21,
104 RESERVED22_IRQn = 22,
105 RESERVED23_IRQn = 23,
106 ADC_IRQn = 24,
107 WDT_IRQn = 25,
108 BOD_IRQn = 26,
109 RESERVED27_IRQn = 27,
110 RESERVED28_IRQn = 28,
111 RESERVED29_IRQn = 29,
112 PIO1_IRQn = 30,
113 PIO0_IRQn = 31,
114 } IRQn_Type;
115
120 #elif defined(CHIP_LPC11XXLV)
121
125 typedef enum IRQn {
126 NonMaskableInt_IRQn = -14,
127 HardFault_IRQn = -13,
128 SVCall_IRQn = -5,
129 PendSV_IRQn = -2,
130 SysTick_IRQn = -1,
132 PIO0_0_IRQn = 0,
133 PIO0_1_IRQn = 1,
134 PIO0_2_IRQn = 2,
135 PIO0_3_IRQn = 3,
136 PIO0_4_IRQn = 4,
137 PIO0_5_IRQn = 5,
138 PIO0_6_IRQn = 6,
139 PIO0_7_IRQn = 7,
140 PIO0_8_IRQn = 8,
141 PIO0_9_IRQn = 9,
142 PIO0_10_IRQn = 10,
143 PIO0_11_IRQn = 11,
144 PIO1_0_IRQn = 12,
145 RESERVED13_IRQn = 13,
146 RESERVED14_IRQn = 14,
147 I2C0_IRQn = 15,
148 TIMER_16_0_IRQn = 16,
149 TIMER_16_1_IRQn = 17,
150 TIMER_32_0_IRQn = 18,
151 TIMER_32_1_IRQn = 19,
152 SSP0_IRQn = 20,
153 UART0_IRQn = 21,
154 RESERVED22_IRQn = 22,
155 RESERVED23_IRQn = 23,
156 ADC_IRQn = 24,
157 WDT_IRQn = 25,
158 BOD_IRQn = 26,
159 FMC_IRQn = 27,
160 PIO3_IRQn = 28,
161 PIO2_IRQn = 29,
162 PIO1_IRQn = 30,
163 PIO0_IRQn = 31,
164 } IRQn_Type;
165
170 #elif defined(CHIP_LPC11AXX)
171
175 typedef enum IRQn {
176 NonMaskableInt_IRQn = -14,
177 HardFault_IRQn = -13,
178 SVCall_IRQn = -5,
179 PendSV_IRQn = -2,
180 SysTick_IRQn = -1,
182 PIN_INT0_IRQn = 0,
183 PIN_INT1_IRQn = 1,
184 PIN_INT2_IRQn = 2,
185 PIN_INT3_IRQn = 3,
186 PIN_INT4_IRQn = 4,
187 PIN_INT5_IRQn = 5,
188 PIN_INT6_IRQn = 6,
189 PIN_INT7_IRQn = 7,
190 GINT0_IRQn = 8,
191 GINT1_IRQn = 9,
192 ACMP_IRQn = 10,
193 DAC_IRQn = 11,
194 RESERVED12_IRQn = 12,
195 RESERVED13_IRQn = 13,
196 SSP1_IRQn = 14,
197 I2C0_IRQn = 15,
198 TIMER_16_0_IRQn = 16,
199 TIMER_16_1_IRQn = 17,
200 TIMER_32_0_IRQn = 18,
201 TIMER_32_1_IRQn = 19,
202 SSP0_IRQn = 20,
203 UART0_IRQn = 21,
204 RESERVED22_IRQn = 22,
205 RESERVED23_IRQn = 23,
206 ADC_IRQn = 24,
207 WDT_IRQn = 25,
208 BOD_IRQn = 26,
209 FMC_IRQn = 27,
210 RESERVED28_IRQn = 28,
211 RESERVED29_IRQn = 29,
212 RESERVED30_IRQn = 30,
213 RESERVED31_IRQn = 31,
214 } IRQn_Type;
215
220 #elif defined(CHIP_LPC11CXX)
221
225 typedef enum IRQn {
226 NonMaskableInt_IRQn = -14,
227 HardFault_IRQn = -13,
228 SVCall_IRQn = -5,
229 PendSV_IRQn = -2,
230 SysTick_IRQn = -1,
232 PIO0_0_IRQn = 0,
233 PIO0_1_IRQn = 1,
234 PIO0_2_IRQn = 2,
235 PIO0_3_IRQn = 3,
236 PIO0_4_IRQn = 4,
237 PIO0_5_IRQn = 5,
238 PIO0_6_IRQn = 6,
239 PIO0_7_IRQn = 7,
240 PIO0_8_IRQn = 8,
241 PIO0_9_IRQn = 9,
242 PIO0_10_IRQn = 10,
243 PIO0_11_IRQn = 11,
244 PIO1_0_IRQn = 12,
245 CAN_IRQn = 13,
246 SSP1_IRQn = 14,
247 I2C0_IRQn = 15,
248 TIMER_16_0_IRQn = 16,
249 TIMER_16_1_IRQn = 17,
250 TIMER_32_0_IRQn = 18,
251 TIMER_32_1_IRQn = 19,
252 SSP0_IRQn = 20,
253 UART0_IRQn = 21,
254 Reserved22_IRQn = 22,
255 Reserved23_IRQn = 23,
256 ADC_IRQn = 24,
257 WDT_IRQn = 25,
258 BOD_IRQn = 26,
259 Reserved27_IRQn = 27,
260 EINT3_IRQn = 28,
261 EINT2_IRQn = 29,
262 EINT1_IRQn = 30,
263 EINT0_IRQn = 31,
264 } IRQn_Type;
265
270 #elif defined(CHIP_LPC11EXX)
271
275 typedef enum IRQn {
276 NonMaskableInt_IRQn = -14,
277 HardFault_IRQn = -13,
278 SVCall_IRQn = -5,
279 PendSV_IRQn = -2,
280 SysTick_IRQn = -1,
282 PIN_INT0_IRQn = 0,
283 PIN_INT1_IRQn = 1,
284 PIN_INT2_IRQn = 2,
285 PIN_INT3_IRQn = 3,
286 PIN_INT4_IRQn = 4,
287 PIN_INT5_IRQn = 5,
288 PIN_INT6_IRQn = 6,
289 PIN_INT7_IRQn = 7,
290 GINT0_IRQn = 8,
291 GINT1_IRQn = 9,
292 Reserved10_IRQn = 10,
293 Reserved11_IRQn = 11,
294 Reserved12_IRQn = 12,
295 Reserved13_IRQn = 13,
296 SSP1_IRQn = 14,
297 I2C0_IRQn = 15,
298 TIMER_16_0_IRQn = 16,
299 TIMER_16_1_IRQn = 17,
300 TIMER_32_0_IRQn = 18,
301 TIMER_32_1_IRQn = 19,
302 SSP0_IRQn = 20,
303 UART0_IRQn = 21,
304 Reserved22_IRQn = 22,
305 Reserved23_IRQn = 23,
306 ADC_IRQn = 24,
307 WDT_IRQn = 25,
308 BOD_IRQn = 26,
309 FMC_IRQn = 27,
310 RESERVED28_IRQn = 28,
311 RESERVED29_IRQn = 29,
312 RESERVED30_IRQn = 30,
313 RESERVED31_IRQn = 31,
314 } IRQn_Type;
315
320 #elif defined(CHIP_LPC11UXX)
321
325 typedef enum IRQn {
326 NonMaskableInt_IRQn = -14,
327 HardFault_IRQn = -13,
328 SVCall_IRQn = -5,
329 PendSV_IRQn = -2,
330 SysTick_IRQn = -1,
332 PIN_INT0_IRQn = 0,
333 PIN_INT1_IRQn = 1,
334 PIN_INT2_IRQn = 2,
335 PIN_INT3_IRQn = 3,
336 PIN_INT4_IRQn = 4,
337 PIN_INT5_IRQn = 5,
338 PIN_INT6_IRQn = 6,
339 PIN_INT7_IRQn = 7,
340 GINT0_IRQn = 8,
341 GINT1_IRQn = 9,
342 Reserved10_IRQn = 10,
343 Reserved11_IRQn = 11,
344 Reserved12_IRQn = 12,
345 Reserved13_IRQn = 13,
346 SSP1_IRQn = 14,
347 I2C0_IRQn = 15,
348 TIMER_16_0_IRQn = 16,
349 TIMER_16_1_IRQn = 17,
350 TIMER_32_0_IRQn = 18,
351 TIMER_32_1_IRQn = 19,
352 SSP0_IRQn = 20,
353 UART0_IRQn = 21,
354 USB0_IRQn = 22,
355 USB0_FIQ_IRQn = 23,
356 ADC_IRQn = 24,
357 WDT_IRQn = 25,
358 BOD_IRQn = 26,
359 FMC_IRQn = 27,
360 RESERVED28_IRQn = 28,
361 RESERVED29_IRQn = 29,
362 USB_WAKEUP_IRQn = 30,
363 RESERVED31_IRQn = 31,
364 } IRQn_Type;
365
370 #else
371 #error Incorrect or missing device variant (CHIP_11*)
372 #endif
373
374 /*
375 * ==========================================================================
376 * ----------- Processor and Core Peripheral Section ------------------------
377 * ==========================================================================
378 */
379
384 /* Configuration of the Cortex-M0 Processor and Core Peripherals */
385 #define __MPU_PRESENT 0
386 #define __NVIC_PRIO_BITS 2
387 #define __Vendor_SysTickConfig 0
393 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
394
399 #ifdef __cplusplus
400 }
401 #endif
402
403 #endif /* __CMSIS_H_ */