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gpdma_18xx_43xx.h
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1 /*
2 * @brief LPC18xx/43xx DMA driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __GPDMA_18XX_43XX_H_
33 #define __GPDMA_18XX_43XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
47 #define GPDMA_NUMBER_CHANNELS 8
48
52 #define GPDMA_CONN_MEMORY ((0UL))
53 #define GPDMA_CONN_MAT0_0 ((1UL))
54 #define GPDMA_CONN_UART0_Tx ((2UL))
55 #define GPDMA_CONN_MAT0_1 ((3UL))
56 #define GPDMA_CONN_UART0_Rx ((4UL))
57 #define GPDMA_CONN_MAT1_0 ((5UL))
58 #define GPDMA_CONN_UART1_Tx ((6UL))
59 #define GPDMA_CONN_MAT1_1 ((7UL))
60 #define GPDMA_CONN_UART1_Rx ((8UL))
61 #define GPDMA_CONN_MAT2_0 ((9UL))
62 #define GPDMA_CONN_UART2_Tx ((10UL))
63 #define GPDMA_CONN_MAT2_1 ((11UL))
64 #define GPDMA_CONN_UART2_Rx ((12UL))
65 #define GPDMA_CONN_MAT3_0 ((13UL))
66 #define GPDMA_CONN_UART3_Tx ((14UL))
67 #define GPDMA_CONN_SCT_0 ((15UL))
68 #define GPDMA_CONN_MAT3_1 ((16UL))
69 #define GPDMA_CONN_UART3_Rx ((17UL))
70 #define GPDMA_CONN_SCT_1 ((18UL))
71 #define GPDMA_CONN_SSP0_Rx ((19UL))
72 #define GPDMA_CONN_I2S_Tx_Channel_0 ((20UL))
73 #define GPDMA_CONN_SSP0_Tx ((21UL))
74 #define GPDMA_CONN_I2S_Rx_Channel_1 ((22UL))
75 #define GPDMA_CONN_SSP1_Rx ((23UL))
76 #define GPDMA_CONN_SSP1_Tx ((24UL))
77 #define GPDMA_CONN_ADC_0 ((25UL))
78 #define GPDMA_CONN_ADC_1 ((26UL))
79 #define GPDMA_CONN_DAC ((27UL))
80 #define GPDMA_CONN_I2S_Tx_Channel_1 ((28UL))
81 #define GPDMA_CONN_I2S_Rx_Channel_0 ((29UL))
86 #define GPDMA_BSIZE_1 ((0UL))
87 #define GPDMA_BSIZE_4 ((1UL))
88 #define GPDMA_BSIZE_8 ((2UL))
89 #define GPDMA_BSIZE_16 ((3UL))
90 #define GPDMA_BSIZE_32 ((4UL))
91 #define GPDMA_BSIZE_64 ((5UL))
92 #define GPDMA_BSIZE_128 ((6UL))
93 #define GPDMA_BSIZE_256 ((7UL))
98 #define GPDMA_WIDTH_BYTE ((0UL))
99 #define GPDMA_WIDTH_HALFWORD ((1UL))
100 #define GPDMA_WIDTH_WORD ((2UL))
105 #define DMA_CONTROLLER 0
106 #define SRC_PER_CONTROLLER 1
107 #define DST_PER_CONTROLLER 2
112 typedef struct {
113 FunctionalState ChannelStatus;
114 } DMA_ChannelHandle_t;
115
119 typedef struct DMA_TransferDescriptor {
120 uint32_t src;
121 uint32_t dst;
122 uint32_t lli;
123 uint32_t ctrl;
124 } DMA_TransferDescriptor_t;
125
139 STATIC INLINE IntStatus Chip_GPDMA_IntGetStatus(LPC_GPDMA_T *pGPDMA, IP_GPDMA_STATUS_T type, uint8_t channel)
140 {
141 return IP_GPDMA_IntGetStatus(pGPDMA, type, channel);
142 }
143
153 STATIC INLINE void Chip_GPDMA_ClearIntPending(LPC_GPDMA_T *pGPDMA, IP_GPDMA_STATECLEAR_T type, uint8_t channel)
154 {
155 IP_GPDMA_ClearIntPending(pGPDMA, type, channel);
156 }
157
165 STATIC INLINE void Chip_GPDMA_ChannelCmd(LPC_GPDMA_T *pGPDMA, uint8_t channelNum, FunctionalState NewState)
166 {
167 IP_GPDMA_ChannelCmd(pGPDMA, channelNum, NewState);
168 }
169
175 void Chip_GPDMA_Init(LPC_GPDMA_T *pGPDMA);
176
182 void Chip_GPDMA_DeInit(LPC_GPDMA_T *pGPDMA);
183
190 void Chip_DMA_Stop(LPC_GPDMA_T *pGPDMA, uint8_t ChannelNum);
191
200 Status Chip_DMA_Interrupt(LPC_GPDMA_T *pGPDMA, uint8_t ChannelNum);
201
208 uint8_t Chip_DMA_GetFreeChannel(LPC_GPDMA_T *pGPDMA, uint32_t PeripheralConnection_ID);
209
228 Status Chip_DMA_Transfer(LPC_GPDMA_T *pGPDMA,
229 uint8_t ChannelNum,
230 uint32_t src,
231 uint32_t dst,
232 IP_GPDMA_FLOW_CONTROL_T TransferType,
233 uint32_t Size);
234
243 Status Chip_DMA_SGTransfer(LPC_GPDMA_T *pGPDMA,
244 uint8_t ChannelNum,
245 const DMA_TransferDescriptor_t *DMADescriptor,
246 IP_GPDMA_FLOW_CONTROL_T TransferType);
247
261 Status Chip_DMA_PrepareDescriptor(LPC_GPDMA_T *pGPDMA,
262 DMA_TransferDescriptor_t *DMADescriptor,
263 uint32_t src,
264 uint32_t dst,
265 uint32_t Size,
266 IP_GPDMA_FLOW_CONTROL_T TransferType,
267 const DMA_TransferDescriptor_t *NextDescriptor);
268
282 int Chip_DMA_InitChannelCfg(LPC_GPDMA_T *pGPDMA,
283 GPDMA_Channel_CFG_T *GPDMACfg,
284 uint8_t ChannelNum,
285 uint32_t src,
286 uint32_t dst,
287 uint32_t Size,
288 IP_GPDMA_FLOW_CONTROL_T TransferType);
289
294 #ifdef __cplusplus
295 }
296 #endif
297
298 #endif /* __GPDMA_18XX_43XX_H_ */