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sysctl_13xx.h
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1 /*
2 * @brief LPC13XX System Control registers and control functions
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __SYSCTL_13XX_H_
33 #define __SYSCTL_13XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
44 #if defined(CHIP_LPC1343)
45
48 typedef struct {
49 __IO uint32_t STARTAPR;
50 __IO uint32_t STARTER;
51 __IO uint32_t STARTRSRCLR;
52 __IO uint32_t STARTSR;
53 } LPC_SYSCTL_STARTST_T;
54 #endif
55
59 typedef struct {
60 __IO uint32_t SYSMEMREMAP;
61 __IO uint32_t PRESETCTRL;
62 __IO uint32_t SYSPLLCTRL;
63 __I uint32_t SYSPLLSTAT;
64 __IO uint32_t USBPLLCTRL;
65 __I uint32_t USBPLLSTAT;
66 __I uint32_t RESERVED1[2];
67 __IO uint32_t SYSOSCCTRL;
68 __IO uint32_t WDTOSCCTRL;
69 #if defined(CHIP_LPC1347)
70 __I uint32_t RESERVED2[2];
71 #else
72 __IO uint32_t IRCCTRL;
73 __I uint32_t RESERVED2[1];
74 #endif
75
76 __IO uint32_t SYSRSTSTAT;
77 __I uint32_t RESERVED3[3];
78 __IO uint32_t SYSPLLCLKSEL;
79 #if defined(CHIP_LPC1347)
80 __I uint32_t RESERVED4;
81 #else
82 __IO uint32_t SYSPLLCLKUEN;
83 #endif
84 __IO uint32_t USBPLLCLKSEL;
85 #if defined(CHIP_LPC1347)
86 __I uint32_t RESERVED4A[1];
87 #else
88 __IO uint32_t USBPLLCLKUEN;
89 #endif
90 __I uint32_t RESERVED5[8];
91 __IO uint32_t MAINCLKSEL;
92 #if defined(CHIP_LPC1347)
93 __IO uint32_t RESERVED6;
94 #else
95 __IO uint32_t MAINCLKUEN;
96 #endif
97 __IO uint32_t SYSAHBCLKDIV;
98 __I uint32_t RESERVED6A;
99 __IO uint32_t SYSAHBCLKCTRL;
100 __I uint32_t RESERVED7[4];
101 __IO uint32_t SSP0CLKDIV;
102 __IO uint32_t USARTCLKDIV;
103 __IO uint32_t SSP1CLKDIV;
104 __I uint32_t RESERVED8[3];
105 __IO uint32_t TRACECLKDIV;
106 __IO uint32_t SYSTICKCLKDIV;
107 __I uint32_t RESERVED9[3];
108 __IO uint32_t USBCLKSEL;
109 #if defined(CHIP_LPC1347)
110 __I uint32_t RESERVED10;
111 #else
112 __IO uint32_t USBCLKUEN;
113 #endif
114 __IO uint32_t USBCLKDIV;
115 #if defined(CHIP_LPC1347)
116 __I uint32_t RESERVED11[4];
117 #else
118 __I uint32_t RESERVED11;
119 __IO uint32_t WDTCLKSEL;
120 __IO uint32_t WDTCLKUEN;
121 __IO uint32_t WDTCLKDIV;
122 #endif
123 __I uint32_t RESERVED13;
124 __IO uint32_t CLKOUTSEL;
125 #if defined(CHIP_LPC1347)
126 __I uint32_t RESERVED12;
127 #else
128 __IO uint32_t CLKOUTUEN;
129 #endif
130 __IO uint32_t CLKOUTDIV;
131 __I uint32_t RESERVED14[5];
132 __I uint32_t PIOPORCAP[2];
133 __I uint32_t RESERVED15[18];
134 __IO uint32_t BODCTRL;
135 __IO uint32_t SYSTCKCAL;
136 #if defined(CHIP_LPC1347)
137 __I uint32_t RESERVED16[6];
138 __IO uint32_t IRQLATENCY;
139 __IO uint32_t NMISRC;
140 __IO uint32_t PINTSEL[8];
141 __IO uint32_t USBCLKCTRL;
142 __I uint32_t USBCLKST;
143 __I uint32_t RESERVED17[25];
144 __IO uint32_t STARTERP0;
145 __I uint32_t RESERVED18[3];
146 __IO uint32_t STARTERP1;
147 __I uint32_t RESERVED19[6];
148 #else
149 __I uint32_t RESERVED16[42];
150 LPC_SYSCTL_STARTST_T STARTLOGIC[2];
151 __I uint32_t RESERVED17[4];
152 #endif
153 __IO uint32_t PDSLEEPCFG;
154 __IO uint32_t PDWAKECFG;
155 __IO uint32_t PDRUNCFG;
156 __I uint32_t RESERVED20[110];
157 __I uint32_t DEVICEID;
158 } LPC_SYSCTL_T;
159
163 typedef enum CHIP_SYSCTL_BOOT_MODE_REMAP {
164 REMAP_BOOT_LOADER_MODE,
165 REMAP_USER_RAM_MODE,
166 REMAP_USER_FLASH_MODE
167 } CHIP_SYSCTL_BOOT_MODE_REMAP_T;
168
174 STATIC INLINE void Chip_SYSCTL_Map(CHIP_SYSCTL_BOOT_MODE_REMAP_T remap)
175 {
176 LPC_SYSCTL->SYSMEMREMAP = (uint32_t) remap;
177 }
178
182 typedef enum CHIP_SYSCTL_PERIPH_RESET {
183 RESET_SSP0,
184 RESET_I2C0,
185 RESET_SSP1
186 } CHIP_SYSCTL_PERIPH_RESET_T;
187
195 STATIC INLINE void Chip_SYSCTL_AssertPeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
196 {
197 LPC_SYSCTL->PRESETCTRL &= ~(1 << (uint32_t) periph);
198 }
199
205 STATIC INLINE void Chip_SYSCTL_DeassertPeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
206 {
207 LPC_SYSCTL->PRESETCTRL |= (1 << (uint32_t) periph);
208 }
209
215 STATIC INLINE void Chip_SYSCTL_PeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
216 {
217 Chip_SYSCTL_AssertPeriphReset(periph);
218 Chip_SYSCTL_DeassertPeriphReset(periph);
219 }
220
224 #define SYSCTL_RST_POR (1 << 0)
225 #define SYSCTL_RST_EXTRST (1 << 1)
226 #define SYSCTL_RST_WDT (1 << 2)
227 #define SYSCTL_RST_BOD (1 << 3)
228 #define SYSCTL_RST_SYSRST (1 << 4)
235 STATIC INLINE uint32_t Chip_SYSCTL_GetSystemRSTStatus(void)
236 {
237 return LPC_SYSCTL->SYSRSTSTAT;
238 }
239
245 STATIC INLINE void Chip_SYSCTL_ClearSystemRSTStatus(uint32_t reset)
246 {
247 LPC_SYSCTL->SYSRSTSTAT = reset;
248 }
249
256 STATIC INLINE uint32_t Chip_SYSCTL_GetPORPIOStatus(int index)
257 {
258 return LPC_SYSCTL->PIOPORCAP[index];
259 }
260
264 typedef enum CHIP_SYSCTL_BODRSTLVL {
265 SYSCTL_BODRSTLVL_1_46V,
266 SYSCTL_BODRSTLVL_2_06V,
267 SYSCTL_BODRSTLVL_2_35V,
268 SYSCTL_BODRSTLVL_2_63V,
269 } CHIP_SYSCTL_BODRSTLVL_T;
270
274 typedef enum CHIP_SYSCTL_BODRINTVAL {
275 #if defined(CHIP_LPC1343)
276 SYSCTL_BODINTVAL_1_69V,
277 #else
278 SYSCTL_BODINTVAL_RESERVED1,
279 #endif
280 SYSCTL_BODINTVAL_2_22V,
281 SYSCTL_BODINTVAL_2_52V,
282 SYSCTL_BODINTVAL_2_80V,
283 } CHIP_SYSCTL_BODRINTVAL_T;
284
293 STATIC INLINE void Chip_SYSCTL_SetBODLevels(CHIP_SYSCTL_BODRSTLVL_T rstlvl,
294 CHIP_SYSCTL_BODRINTVAL_T intlvl)
295 {
296 LPC_SYSCTL->BODCTRL = ((uint32_t) rstlvl) | (((uint32_t) intlvl) << 2);
297 }
298
303 STATIC INLINE void Chip_SYSCTL_EnableBODReset(void)
304 {
305 LPC_SYSCTL->BODCTRL |= (1 << 4);
306 }
307
312 STATIC INLINE void Chip_SYSCTL_DisableBODReset(void)
313 {
314 LPC_SYSCTL->BODCTRL &= ~(1 << 4);
315 }
316
322 STATIC INLINE void Chip_SYSCTL_SetSYSTCKCAL(uint32_t sysCalVal)
323 {
324 LPC_SYSCTL->SYSTCKCAL = sysCalVal;
325 }
326
327 #if defined(CHIP_LPC1347)
328
335 STATIC INLINE void Chip_SYSCTL_SetIRQLatency(uint32_t latency)
336 {
337 LPC_SYSCTL->IRQLATENCY = latency;
338 }
339
344 STATIC INLINE uint32_t Chip_SYSCTL_GetIRQLatency(void)
345 {
346 return LPC_SYSCTL->IRQLATENCY;
347 }
348
352 #define SYSCTL_NMISRC_ENABLE ((uint32_t) 1 << 31)
361 STATIC INLINE void Chip_SYSCTL_SetNMISource(uint32_t intsrc)
362 {
363 LPC_SYSCTL->NMISRC = intsrc;
364 }
365
370 STATIC INLINE void Chip_SYSCTL_EnableNMISource(void)
371 {
372 LPC_SYSCTL->NMISRC |= SYSCTL_NMISRC_ENABLE;
373 }
374
379 STATIC INLINE void Chip_SYSCTL_DisableNMISource(void)
380 {
381 LPC_SYSCTL->NMISRC &= ~(SYSCTL_NMISRC_ENABLE);
382 }
383
391 STATIC INLINE void Chip_SYSCTL_SetPinInterrupt(uint32_t intno, uint8_t port, uint8_t pin)
392
393 {
394 LPC_SYSCTL->PINTSEL[intno] = (uint32_t) (port*24 + pin);
395 }
396
397
405 STATIC INLINE void Chip_SYSCTL_SetUSBCLKCTRL(uint32_t ap_clk, uint32_t pol_clk)
406 {
407 LPC_SYSCTL->USBCLKCTRL = ap_clk | (pol_clk << 1);
408 }
409
414 STATIC INLINE bool Chip_SYSCTL_GetUSBCLKStatus(void)
415 {
416 return (bool) ((LPC_SYSCTL->USBCLKST & 0x1) != 0);
417 }
418
419 #endif
420
421 #if defined(CHIP_LPC1347)
422
427 STATIC INLINE void Chip_SYSCTL_EnableStartPin(uint32_t pin)
428 {
429 LPC_SYSCTL->STARTERP0 |= (1 << pin);
430 }
431
437 STATIC INLINE void Chip_SYSCTL_DisableStartPin(uint32_t pin)
438 {
439 LPC_SYSCTL->STARTERP0 &= ~(1 << pin);
440 }
441
445 #define SYSCTL_WAKEUP_WWDTINT (1 << 12)
446 #define SYSCTL_WAKEUP_BODINT (1 << 13)
447 #define SYSCTL_WAKEUP_USB_WAKEUP (1 << 19)
448 #define SYSCTL_WAKEUP_GPIOINT0 (1 << 20)
449 #define SYSCTL_WAKEUP_GPIOINT1 (1 << 21)
456 STATIC INLINE void Chip_SYSCTL_EnablePeriphWakeup(uint32_t periphmask)
457 {
458 LPC_SYSCTL->STARTERP1 |= periphmask;
459 }
460
466 STATIC INLINE void Chip_SYSCTL_DisablePeriphWakeup(uint32_t periphmask)
467 {
468 LPC_SYSCTL->STARTERP1 &= ~periphmask;
469 }
470 #else /* defined(CHIP_LPC1343) */
471
472 /* Macro for Chip_SYSCTL_SetStartPinRising and Chip_SYSCTL_SetStartPinFalling
473 functions */
474 #define SYSCTL_STARTST_PIN_BIT(port, pin) (((port) * 12) + pin)
475 #define SYSCTL_STARTST_PIN_INDEX(port,pin) (SYSCTL_STARTST_PIN_BIT(port,pin)/32)
476 #define SYSCTL_STARTST_PIN(port,pin) (1 << (SYSCTL_STARTST_PIN_BIT(port,pin)%32))
477
493 STATIC INLINE void Chip_SYSCTL_SetStartPinRising(uint8_t index, uint32_t pins)
494 {
495 LPC_SYSCTL->STARTLOGIC[index].STARTAPR |= pins;
496 }
497
512 STATIC INLINE void Chip_SYSCTL_SetStartPinFalling(uint8_t index, uint32_t pins)
513 {
514 LPC_SYSCTL->STARTLOGIC[index].STARTAPR &= ~pins;
515 }
516
529 STATIC INLINE void Chip_SYSCTL_EnableStartPin(uint8_t index, uint32_t pins)
530 {
531 LPC_SYSCTL->STARTLOGIC[index].STARTER |= pins;
532 }
533
546 STATIC INLINE void Chip_SYSCTL_DisableStartPin(uint8_t index, uint32_t pins)
547 {
548 LPC_SYSCTL->STARTLOGIC[index].STARTER &= ~pins;
549 }
550
563 STATIC INLINE void Chip_SYSCTL_ResetStartPin(uint8_t index, uint32_t pins)
564 {
565 LPC_SYSCTL->STARTLOGIC[index].STARTRSRCLR |= pins;
566 }
567
576 STATIC INLINE uint32_t Chip_SYSCTL_GetStartPinStatus(uint8_t index)
577 {
578 return LPC_SYSCTL->STARTLOGIC[index].STARTSR;
579 }
580 #endif
581
585 #define SYSCTL_DEEPSLP_BOD_PD (1 << 3)
586 #define SYSCTL_DEEPSLP_WDTOSC_PD (1 << 6)
598 void Chip_SYSCTL_SetDeepSleepPD(uint32_t sleepmask);
599
605 STATIC INLINE uint32_t Chip_SYSCTL_GetDeepSleepPD(void)
606 {
607 return LPC_SYSCTL->PDSLEEPCFG;
608 }
609
613 #define SYSCTL_SLPWAKE_IRCOUT_PD (1 << 0)
614 #define SYSCTL_SLPWAKE_IRC_PD (1 << 1)
615 #define SYSCTL_SLPWAKE_FLASH_PD (1 << 2)
616 #define SYSCTL_SLPWAKE_BOD_PD (1 << 3)
617 #define SYSCTL_SLPWAKE_ADC_PD (1 << 4)
618 #define SYSCTL_SLPWAKE_SYSOSC_PD (1 << 5)
619 #define SYSCTL_SLPWAKE_WDTOSC_PD (1 << 6)
620 #define SYSCTL_SLPWAKE_SYSPLL_PD (1 << 7)
621 #define SYSCTL_SLPWAKE_USBPLL_PD (1 << 8)
622 #define SYSCTL_SLPWAKE_USBPAD_PD (1 << 10)
634 void Chip_SYSCTL_SetWakeup(uint32_t wakeupmask);
635
641 STATIC INLINE uint32_t Chip_SYSCTL_GetWakeup(void)
642 {
643 return LPC_SYSCTL->PDWAKECFG;
644 }
645
649 #define SYSCTL_POWERDOWN_IRCOUT_PD (1 << 0)
650 #define SYSCTL_POWERDOWN_IRC_PD (1 << 1)
651 #define SYSCTL_POWERDOWN_FLASH_PD (1 << 2)
652 #define SYSCTL_POWERDOWN_BOD_PD (1 << 3)
653 #define SYSCTL_POWERDOWN_ADC_PD (1 << 4)
654 #define SYSCTL_POWERDOWN_SYSOSC_PD (1 << 5)
655 #define SYSCTL_POWERDOWN_WDTOSC_PD (1 << 6)
656 #define SYSCTL_POWERDOWN_SYSPLL_PD (1 << 7)
657 #define SYSCTL_POWERDOWN_USBPLL_PD (1 << 8)
658 #define SYSCTL_POWERDOWN_USBPAD_PD (1 << 10)
665 void Chip_SYSCTL_PowerDown(uint32_t powerdownmask);
666
672 void Chip_SYSCTL_PowerUp(uint32_t powerupmask);
673
679 STATIC INLINE uint32_t Chip_SYSCTL_GetPowerStates(void)
680 {
681 return LPC_SYSCTL->PDRUNCFG;
682 }
683
688 STATIC INLINE uint32_t Chip_SYSCTL_GetDeviceID(void)
689 {
690 return LPC_SYSCTL->DEVICEID;
691 }
692
697 #ifdef __cplusplus
698 }
699 #endif
700
701 #endif /* __SYSCTL_13XX_H_ */