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otp_18xx_43xx.h
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1 /*
2 * @brief LPC18xx/43xx OTP Controller driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __OTP_18XX_43XX_H_
33 #define __OTP_18XX_43XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
47 typedef struct {
48 __IO uint32_t OTP0_0;
49 __IO uint32_t OTP0_1;
50 __IO uint32_t OTP0_2;
51 __IO uint32_t OTP0_3;
52 __IO uint32_t OTP1_0;
53 __IO uint32_t OTP1_1;
54 __IO uint32_t OTP1_2;
55 __IO uint32_t OTP1_3;
56 __IO uint32_t OTP2_0;
57 __IO uint32_t OTP2_1;
58 __IO uint32_t OTP2_2;
59 __IO uint32_t OTP2_3;
60 uint32_t RESERVED0[4];
61 __IO uint32_t UNIQUE_KEY0;
62 __IO uint32_t UNIQUE_KEY1;
63 __IO uint32_t UNIQUE_KEY2;
64 __IO uint32_t UNIQUE_KEY3;
65 __IO uint32_t RANDOM_NUM0;
66 __IO uint32_t RANDOM_NUM1;
67 __IO uint32_t RANDOM_NUM2;
68 __IO uint32_t RANDOM_NUM3;
69 __IO uint32_t USER_KEY0;
70 __IO uint32_t USER_KEY1;
71 __IO uint32_t USER_KEY2;
72 __IO uint32_t USER_KEY3;
73 uint32_t RESERVED1[4];
74 __IO uint32_t WRTMASK;
75 __O uint32_t STATUS;
76 uint32_t RESERVED2[2];
77 __IO uint32_t PROGRAM;
78 __IO uint32_t AES_SSEL;
79 __IO uint32_t SHUFFLE_CTRL;
80 uint32_t RESERVED3;
81 __IO uint32_t OTP0_WR_LOCK;
82 __IO uint32_t OTP0_RD_LOCK;
83 __IO uint32_t OTP1_WR_LOCK;
84 __IO uint32_t OTP1_RD_LOCK;
85 __IO uint32_t OTP2_WR_LOCK;
86 __IO uint32_t OTP2_RD_LOCK;
87 __IO uint32_t RESERVED4[2];
88 __IO uint32_t UNIQUE_KEY_WR_LOCK;
89 __IO uint32_t UNIQUE_KEY_RD_LOCK;
90 __IO uint32_t RANDOM_NUM_WR_LOCK;
91 __IO uint32_t RANDOM_NUM_RD_LOCK;
92 __IO uint32_t RESERVED5;
93 __IO uint32_t USER_KEY_RD_LOCK;
94 } LPC_OTP_T;
95
99 typedef enum CHIP_OTP_BOOT_SRC {
100 CHIP_OTP_BOOTSRC_PINS,
101 CHIP_OTP_BOOTSRC_UART0,
102 CHIP_OTP_BOOTSRC_SPIFI,
103 CHIP_OTP_BOOTSRC_EMC8,
104 CHIP_OTP_BOOTSRC_EMC16,
105 CHIP_OTP_BOOTSRC_EMC32,
106 CHIP_OTP_BOOTSRC_USB0,
107 CHIP_OTP_BOOTSRC_USB1,
108 CHIP_OTP_BOOTSRC_SPI,
109 CHIP_OTP_BOOTSRC_UART3
110 } CHIP_OTP_BOOT_SRC_T;
111
118 uint32_t Chip_OTP_Init(void);
119
125 uint32_t Chip_OTP_ProgBootSrc(CHIP_OTP_BOOT_SRC_T BootSrc);
126
131 uint32_t Chip_OTP_ProgJTAGDis(void);
132
139 uint32_t Chip_OTP_ProgUSBID(uint32_t ProductID, uint32_t VendorID);
140
149 uint32_t Chip_OTP_ProgGPWord(uint32_t WordNum, uint32_t Data, uint32_t Mask);
150
158 uint32_t Chip_OTP_ProgKey(uint32_t KeyNum, uint8_t *key);
159
164 uint32_t Chip_OTP_GenRand(void);
165
170 #ifdef __cplusplus
171 }
172 #endif
173
174 #endif /* __OTP_18XX_43XX_H_ */