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Data Structures | Macros | Enumerations | Functions
IP: SDC register block and driver
IP drivers: Common drivers used on multiple NXP devices

## Detailed Description

SD/MMC card Interface

## Data Structures
struct | IP_SDC_001_T
| SD/MMC card Interface (SDC) register block structure. More...
struct | IP_SDC_001_RESP_T
| SDC Command Response structure. More...
struct | IP_SDC_001_DATA_TRANSFER_T
| SDC Data Transfer Setup structure. More...

## Macros
#define | SDC_PWR_BITMASK ((uint32_t) 0xC3)
| SDC Power Control Register bit definitions.
#define | SDC_PWR_CTRL_BITMASK (((uint32_t) 0x03) << 0)
#define | SDC_PWR_CTRL(n) (((uint32_t) (n & 0x03)) << 0)
#define | SDC_PWR_OPENDRAIN (((uint32_t) 1) << 6)
#define | SDC_PWR_ROD (((uint32_t) 1) << 7)
#define | SDC_CLOCK_BITMASK ((uint32_t) 0xFFF)
| SDC Clock Control Register bit definitions.
#define | SDC_CLOCK_CLKDIV_BITMASK (((uint32_t) 0xFF ) << 0)
#define | SDC_CLOCK_CLKDIV(n) (((uint32_t) (n & 0x0FF)) << 0)
#define | SDC_COMMAND_BITMASK ((uint32_t) 0x7FF)
| SDC Command Register bit definitions.
#define | SDC_COMMAND_INDEX_BITMASK ((uint32_t) 0x3F)
#define | SDC_COMMAND_INDEX(n) ((uint32_t) n & 0x3F)
#define | SDC_COMMAND_NO_RSP (((uint32_t) 0 ) << 6)
#define | SDC_COMMAND_SHORT_RSP (((uint32_t) 1 ) << 6)
#define | SDC_COMMAND_LONG_RSP (((uint32_t) 3 ) << 6)
#define | SDC_COMMAND_RSP_BITMASK (((uint32_t) 3 ) << 6)
#define | SDC_COMMAND_INTERRUPT (((uint32_t) 1 ) << 8)
#define | SDC_COMMAND_PENDING (((uint32_t) 1 ) << 9)
#define | SDC_COMMAND_ENABLE (((uint32_t) 1 ) << 10)
#define | SDC_RESPCOMMAND_VAL(n) ((uint32_t) n & 0x3F)
| SDC Command Response Register bit definitions.
#define | SDC_DATALENGTH_LEN(n) ((uint32_t) n & 0xFFFF)
| SDC Data Length Register bit definitions.
#define | SDC_DATACTRL_BITMASK ((uint32_t) 0xFF)
| SDC Data Control Register bit definitions.
#define | SDC_DATACTRL_ENABLE (((uint32_t) 1 ) << 0)
#define | SDC_DATACTRL_DIR_FROMCARD (((uint32_t) 1 ) << 1)
#define | SDC_DATACTRL_DIR_TOCARD ((uint32_t) 0)
#define | SDC_DATACTRL_XFER_MODE_STREAM (((uint32_t) 1 ) << 2)
#define | SDC_DATACTRL_XFER_MODE_BLOCK ((uint32_t) 0)
#define | SDC_DATACTRL_DMA_ENABLE (((uint32_t) 1 ) << 3)
#define | SDC_DATACTRL_BLOCKSIZE(n) (((uint32_t) (n & 0x0F) ) << 4)
#define | SDC_DATACTRL_BLOCKSIZE_VAL(n) (((uint32_t) 1) << n)
#define | SDC_DATACNT_VAL(n) ((uint32_t) n & 0xFFFF)
| SDC Data Counter Register bit definitions.
#define | SDC_STATUS_CMDCRCFAIL (((uint32_t) 1 ) << 0)
| SDC Status Register bit definitions.
#define | SDC_STATUS_DATACRCFAIL (((uint32_t) 1 ) << 1)
#define | SDC_STATUS_CMDTIMEOUT (((uint32_t) 1 ) << 2)
#define | SDC_STATUS_DATATIMEOUT (((uint32_t) 1 ) << 3)
#define | SDC_STATUS_TXUNDERRUN (((uint32_t) 1 ) << 4)
#define | SDC_STATUS_RXOVERRUN (((uint32_t) 1 ) << 5)
#define | SDC_STATUS_CMDRESPEND (((uint32_t) 1 ) << 6)
#define | SDC_STATUS_CMDSENT (((uint32_t) 1 ) << 7)
#define | SDC_STATUS_DATAEND (((uint32_t) 1 ) << 8)
#define | SDC_STATUS_STARTBITERR (((uint32_t) 1 ) << 9)
#define | SDC_STATUS_DATABLOCKEND (((uint32_t) 1 ) << 10)
#define | SDC_STATUS_CMDACTIVE (((uint32_t) 1 ) << 11)
#define | SDC_STATUS_TXACTIVE (((uint32_t) 1 ) << 12)
#define | SDC_STATUS_RXACTIVE (((uint32_t) 1 ) << 13)
#define | SDC_STATUS_TXFIFOHALFEMPTY (((uint32_t) 1 ) << 14)
#define | SDC_STATUS_RXFIFOHALFFULL (((uint32_t) 1 ) << 15)
#define | SDC_STATUS_TXFIFOFULL (((uint32_t) 1 ) << 16)
#define | SDC_STATUS_RXFIFOFULL (((uint32_t) 1 ) << 17)
#define | SDC_STATUS_TXFIFOEMPTY (((uint32_t) 1 ) << 18)
#define | SDC_STATUS_RXFIFOEMPTY (((uint32_t) 1 ) << 19)
#define | SDC_STATUS_TXDATAAVLBL (((uint32_t) 1 ) << 20)
#define | SDC_STATUS_RXDATAAVLBL (((uint32_t) 1 ) << 21)
#define | SDC_STATUS_CMDERR (SDC_STATUS_CMDCRCFAIL | SDC_STATUS_CMDTIMEOUT | SDC_STATUS_STARTBITERR)
#define | SDC_STATUS_DATAERR
#define | SDC_STATUS_FIFO
#define | SDC_STATUS_DATA (SDC_STATUS_DATAEND )
#define | SDC_CLEAR_ALL ((uint32_t) 0x7FF)
| SDC Clear Register bit definitions.
#define | SDC_CLEAR_CMDCRCFAIL (((uint32_t) 1 ) << 0)
#define | SDC_CLEAR_DATACRCFAIL (((uint32_t) 1 ) << 1)
#define | SDC_CLEAR_CMDTIMEOUT (((uint32_t) 1 ) << 2)
#define | SDC_CLEAR_DATATIMEOUT (((uint32_t) 1 ) << 3)
#define | SDC_CLEAR_TXUNDERRUN (((uint32_t) 1 ) << 4)
#define | SDC_CLEAR_RXOVERRUN (((uint32_t) 1 ) << 5)
#define | SDC_CLEAR_CMDRESPEND (((uint32_t) 1 ) << 6)
#define | SDC_CLEAR_CMDSENT (((uint32_t) 1 ) << 7)
#define | SDC_CLEAR_DATAEND (((uint32_t) 1 ) << 8)
#define | SDC_CLEAR_STARTBITERR (((uint32_t) 1 ) << 9)
#define | SDC_CLEAR_DATABLOCKEND (((uint32_t) 1 ) << 10)
#define | SDC_MASK0_CMDCRCFAIL (((uint32_t) 1 ) << 0)
| SDC Interrupt Mask Register bit definitions.
#define | SDC_MASK0_DATACRCFAIL (((uint32_t) 1 ) << 1)
#define | SDC_MASK0_CMDTIMEOUT (((uint32_t) 1 ) << 2)
#define | SDC_MASK0_DATATIMEOUT (((uint32_t) 1 ) << 3)
#define | SDC_MASK0_TXUNDERRUN (((uint32_t) 1 ) << 4)
#define | SDC_MASK0_RXOVERRUN (((uint32_t) 1 ) << 5)
#define | SDC_MASK0_CMDRESPEND (((uint32_t) 1 ) << 6)
#define | SDC_MASK0_CMDSENT (((uint32_t) 1 ) << 7)
#define | SDC_MASK0_DATAEND (((uint32_t) 1 ) << 8)
#define | SDC_MASK0_STARTBITERR (((uint32_t) 1 ) << 9)
#define | SDC_MASK0_DATABLOCKEND (((uint32_t) 1 ) << 10)
#define | SDC_MASK0_CMDACTIVE (((uint32_t) 1 ) << 11)
#define | SDC_MASK0_TXACTIVE (((uint32_t) 1 ) << 12)
#define | SDC_MASK0_RXACTIVE (((uint32_t) 1 ) << 13)
#define | SDC_MASK0_TXFIFOHALFEMPTY (((uint32_t) 1 ) << 14)
#define | SDC_MASK0_RXFIFOHALFFULL (((uint32_t) 1 ) << 15)
#define | SDC_MASK0_TXFIFOFULL (((uint32_t) 1 ) << 16)
#define | SDC_MASK0_RXFIFOFULL (((uint32_t) 1 ) << 17)
#define | SDC_MASK0_TXFIFOEMPTY (((uint32_t) 1 ) << 18)
#define | SDC_MASK0_RXFIFOEMPTY (((uint32_t) 1 ) << 19)
#define | SDC_MASK0_TXDATAAVLBL (((uint32_t) 1 ) << 20)
#define | SDC_MASK0_RXDATAAVLBL (((uint32_t) 1 ) << 21)
#define | SDC_MASK0_CMDERR (SDC_MASK0_CMDCRCFAIL | SDC_MASK0_CMDTIMEOUT | SDC_MASK0_STARTBITERR)
#define | SDC_MASK0_TXDATAERR
#define | SDC_MASK0_RXDATAERR
#define | SDC_MASK0_TXFIFO (SDC_MASK0_TXFIFOHALFEMPTY | SDC_MASK0_DATABLOCKEND )
#define | SDC_MASK0_RXFIFO (SDC_MASK0_RXFIFOHALFFULL | SDC_MASK0_DATABLOCKEND )
#define | SDC_MASK0_DATA (SDC_MASK0_DATAEND | SDC_MASK0_DATABLOCKEND )
#define | SDC_FIFOCNT_VAL(n) ((uint32_t) n & 0x7FFF)
| SDC FIFO Counter Register bit definitions.
#define | SDC_CARDSTATUS_BYTENUM ((uint32_t) 4)

## Enumerations
enum | IP_SDC_001_PWR_CTRL_T { SDC_POWER_OFF = 0, SDC_POWER_UP = 2, SDC_POWER_ON = 3 }
| SDC Power Control Options. More...
enum | IP_SDC_001_CLOCK_CTRL_T { SDC_CLOCK_ENABLE = 8, SDC_CLOCK_POWER_SAVE = 9, SDC_CLOCK_DIVIDER_BYPASS = 10, SDC_CLOCK_WIDEBUS_MODE = 11 }
| SDC Clock Control Options. More...
enum | IP_SDC_001_RESPONSE_T { SDC_NO_RESPONSE = SDC_COMMAND_NO_RSP, SDC_SHORT_RESPONSE = SDC_COMMAND_SHORT_RSP, SDC_LONG_RESPONSE = SDC_COMMAND_LONG_RSP }
| SDC Response type. More...
enum | IP_SDC_001_TRANSFER_DIR_T { SDC_TRANSFER_DIR_FROMCARD = SDC_DATACTRL_DIR_FROMCARD, SDC_TRANSFER_DIR_TOCARD = SDC_DATACTRL_DIR_TOCARD }
| SDC Data Transfer Direction definitions. More...
enum | IP_SDC_001_TRANSFER_MODE_T { SDC_TRANSFER_MODE_STREAM = SDC_DATACTRL_XFER_MODE_STREAM, SDC_TRANSFER_MODE_BLOCK = SDC_DATACTRL_XFER_MODE_BLOCK }
| SDC Data Transfer Mode definitions. More...
enum | IP_SDC_001_BLOCK_SIZE_T { SDC_BLOCK_SIZE_1 = 0, SDC_BLOCK_SIZE_2, SDC_BLOCK_SIZE_4, SDC_BLOCK_SIZE_8, SDC_BLOCK_SIZE_16, SDC_BLOCK_SIZE_32, SDC_BLOCK_SIZE_64, SDC_BLOCK_SIZE_128, SDC_BLOCK_SIZE_256, SDC_BLOCK_SIZE_512, SDC_BLOCK_SIZE_1024, SDC_BLOCK_SIZE_2048 }
| SDC Data Block size definitions (in bytes) More...

## Functions
void | IP_SDC_PowerControl (IP_SDC_001_T *pSDC, IP_SDC_001_PWR_CTRL_T pwrMode, uint32_t flag)
| Set the power state of SDC peripheral.
void | IP_SDC_SetClockDiv (IP_SDC_001_T *pSDC, uint8_t div)
| Set clock divider value for SDC peripheral.
void | IP_SDC_ClockControl (IP_SDC_001_T *pSDC, IP_SDC_001_CLOCK_CTRL_T ctrlType, FunctionalState NewState)
| Set or Reset clock control of SDC peripheral.
void | IP_SDC_SetCommand (IP_SDC_001_T *pSDC, uint32_t Cmd, uint32_t Arg)
| Set SDC Command Information.
void | IP_SDC_ResetCommand (IP_SDC_001_T *pSDC)
| Reset SDC Command Information.
void | IP_SDC_GetResp (IP_SDC_001_T *pSDC, IP_SDC_001_RESP_T *pResp)
| Get SDC Response.
STATIC INLINE void | IP_SDC_SetDataTimer (IP_SDC_001_T *pSDC, uint32_t timeout)
| Set SDC Data Timeout Period.
void | IP_SDC_SetDataTransfer (IP_SDC_001_T *pSDC, IP_SDC_001_DATA_TRANSFER_T *pTransfer)
| Set SDC Data Transfer Information.
void | IP_SDC_WriteFIFO (IP_SDC_001_T *pSDC, uint32_t *pSrc, bool bFirstHalf)
| Write Data to FIFO.
void | IP_SDC_ReadFIFO (IP_SDC_001_T *pSDC, uint32_t *pDst, bool bFirstHalf)
| Write Data to FIFO.
STATIC INLINE uint32_t | IP_SDC_GetStatus (IP_SDC_001_T *pSDC)
| Get status of SDC Peripheral.
STATIC INLINE void | IP_SDC_ClearStatus (IP_SDC_001_T *pSDC, uint32_t flag)
| Clear status of SDC Peripheral.
STATIC INLINE void | IP_SDC_SetIntMask (IP_SDC_001_T *pSDC, uint32_t mask)
| Set interrupt mask for SDC Peripheral.
void | IP_SDC_Init (IP_SDC_001_T *pSDC)
| Initialize the SDC card controller.
STATIC INLINE void | IP_SDC_DeInit (IP_SDC_001_T *pSDC)
| Deinitialise the SDC peripheral.

## Macro Definition Documentation

#define SDC_CARDSTATUS_BYTENUM ((uint32_t) 4)

Definition at line 317 of file sdc_001.h.

#define SDC_CLEAR_ALL ((uint32_t) 0x7FF)

SDC Clear Register bit definitions.

Clear all status flag

Definition at line 223 of file sdc_001.h.

#define SDC_CLEAR_CMDCRCFAIL (((uint32_t) 1 ) << 0)

Clears CmdCrcFail flag.

Definition at line 225 of file sdc_001.h.

#define SDC_CLEAR_CMDRESPEND (((uint32_t) 1 ) << 6)

Clears CmdRespEnd flag.

Definition at line 237 of file sdc_001.h.

#define SDC_CLEAR_CMDSENT (((uint32_t) 1 ) << 7)

Clears CmdSent flag.

Definition at line 239 of file sdc_001.h.

#define SDC_CLEAR_CMDTIMEOUT (((uint32_t) 1 ) << 2)

Clears CmdTimeOut flag.

Definition at line 229 of file sdc_001.h.

#define SDC_CLEAR_DATABLOCKEND (((uint32_t) 1 ) << 10)

Clears DataBlockEnd flag.

Definition at line 245 of file sdc_001.h.

#define SDC_CLEAR_DATACRCFAIL (((uint32_t) 1 ) << 1)

Clears DataCrcFail flag.

Definition at line 227 of file sdc_001.h.

#define SDC_CLEAR_DATAEND (((uint32_t) 1 ) << 8)

Clears DataEnd flag.

Definition at line 241 of file sdc_001.h.

#define SDC_CLEAR_DATATIMEOUT (((uint32_t) 1 ) << 3)

Clears DataTimeOut flag.

Definition at line 231 of file sdc_001.h.

#define SDC_CLEAR_RXOVERRUN (((uint32_t) 1 ) << 5)

Clears RxOverrun flag.

Definition at line 235 of file sdc_001.h.

#define SDC_CLEAR_STARTBITERR (((uint32_t) 1 ) << 9)

Clears StartBitErr flag.

Definition at line 243 of file sdc_001.h.

#define SDC_CLEAR_TXUNDERRUN (((uint32_t) 1 ) << 4)

Clears TxUnderrun flag.

Definition at line 233 of file sdc_001.h.

#define SDC_CLOCK_BITMASK ((uint32_t) 0xFFF)

SDC Clock Control Register bit definitions.

SDC Clock Control Register Bitmask

Definition at line 89 of file sdc_001.h.

#define SDC_CLOCK_CLKDIV | ( |  | n | ) | (((uint32_t) (n & 0x0FF)) << 0)

Set SDC Clock Divide value

Definition at line 93 of file sdc_001.h.

#define SDC_CLOCK_CLKDIV_BITMASK (((uint32_t) 0xFF ) << 0)

SDC Clock Divider Bitmask

Definition at line 91 of file sdc_001.h.

#define SDC_COMMAND_BITMASK ((uint32_t) 0x7FF)

SDC Command Register bit definitions.

SDC Command Register Bitmask

Definition at line 99 of file sdc_001.h.

#define SDC_COMMAND_ENABLE (((uint32_t) 1 ) << 10)

Enable CPSM

Definition at line 117 of file sdc_001.h.

#define SDC_COMMAND_INDEX | ( |  | n | ) | ((uint32_t) n & 0x3F)

Set SDC Command Index

Definition at line 103 of file sdc_001.h.

#define SDC_COMMAND_INDEX_BITMASK ((uint32_t) 0x3F)

SDC Command Index Bitmask

Definition at line 101 of file sdc_001.h.

#define SDC_COMMAND_INTERRUPT (((uint32_t) 1 ) << 8)

Mark that command timer is disabled and CPSM waits for interrupt request

Definition at line 113 of file sdc_001.h.

#define SDC_COMMAND_LONG_RSP (((uint32_t) 3 ) << 6)

Long response is expected

Definition at line 109 of file sdc_001.h.

#define SDC_COMMAND_NO_RSP (((uint32_t) 0 ) << 6)

No response is expected

Definition at line 105 of file sdc_001.h.

#define SDC_COMMAND_PENDING (((uint32_t) 1 ) << 9)

Mark that CPSM waits for CmdPend before starting sending a command

Definition at line 115 of file sdc_001.h.

#define SDC_COMMAND_RSP_BITMASK (((uint32_t) 3 ) << 6)

Response bit mask

Definition at line 111 of file sdc_001.h.

#define SDC_COMMAND_SHORT_RSP (((uint32_t) 1 ) << 6)

Short response is expected

Definition at line 107 of file sdc_001.h.

#define SDC_DATACNT_VAL | ( |  | n | ) | ((uint32_t) n & 0xFFFF)

SDC Data Counter Register bit definitions.

Definition at line 156 of file sdc_001.h.

#define SDC_DATACTRL_BITMASK ((uint32_t) 0xFF)

SDC Data Control Register bit definitions.

SDC Data Control Register Bitmask

Definition at line 135 of file sdc_001.h.

#define SDC_DATACTRL_BLOCKSIZE | ( |  | n | ) | (((uint32_t) (n & 0x0F) ) << 4)

Set Data Block size

Definition at line 149 of file sdc_001.h.

#define SDC_DATACTRL_BLOCKSIZE_VAL | ( |  | n | ) | (((uint32_t) 1) << n)

Get Data Block size value

Definition at line 151 of file sdc_001.h.

#define SDC_DATACTRL_DIR_FROMCARD (((uint32_t) 1 ) << 1)

Mark that Data is transfer from card to controller

Definition at line 139 of file sdc_001.h.

#define SDC_DATACTRL_DIR_TOCARD ((uint32_t) 0)

Mark that Data is transfer from controller to card

Definition at line 141 of file sdc_001.h.

#define SDC_DATACTRL_DMA_ENABLE (((uint32_t) 1 ) << 3)

Enable DMA

Definition at line 147 of file sdc_001.h.

#define SDC_DATACTRL_ENABLE (((uint32_t) 1 ) << 0)

Enable Data Transfer

Definition at line 137 of file sdc_001.h.

#define SDC_DATACTRL_XFER_MODE_BLOCK ((uint32_t) 0)

Mark that the transfer mode is Block Data Transfer

Definition at line 145 of file sdc_001.h.

#define SDC_DATACTRL_XFER_MODE_STREAM (((uint32_t) 1 ) << 2)

Mark that the transfer mode is Stream Data Transfer

Definition at line 143 of file sdc_001.h.

#define SDC_DATALENGTH_LEN | ( |  | n | ) | ((uint32_t) n & 0xFFFF)

SDC Data Length Register bit definitions.

SDC Data Length set

Definition at line 129 of file sdc_001.h.

#define SDC_FIFOCNT_VAL | ( |  | n | ) | ((uint32_t) n & 0x7FFF)

SDC FIFO Counter Register bit definitions.

Definition at line 314 of file sdc_001.h.

#define SDC_MASK0_CMDACTIVE (((uint32_t) 1 ) << 11)

Mask CmdActive flag.

Definition at line 273 of file sdc_001.h.

#define SDC_MASK0_CMDCRCFAIL (((uint32_t) 1 ) << 0)

SDC Interrupt Mask Register bit definitions.

Mask CmdCrcFail flag.

Definition at line 251 of file sdc_001.h.

#define SDC_MASK0_CMDERR (SDC_MASK0_CMDCRCFAIL | SDC_MASK0_CMDTIMEOUT | SDC_MASK0_STARTBITERR)

CMD error interrupt mask

Definition at line 295 of file sdc_001.h.

#define SDC_MASK0_CMDRESPEND (((uint32_t) 1 ) << 6)

Mask CmdRespEnd flag.

Definition at line 263 of file sdc_001.h.

#define SDC_MASK0_CMDSENT (((uint32_t) 1 ) << 7)

Mask CmdSent flag.

Definition at line 265 of file sdc_001.h.

#define SDC_MASK0_CMDTIMEOUT (((uint32_t) 1 ) << 2)

Mask CmdTimeOut flag.

Definition at line 255 of file sdc_001.h.

#define SDC_MASK0_DATA (SDC_MASK0_DATAEND | SDC_MASK0_DATABLOCKEND )

Data Transfer interrupt mask

Definition at line 309 of file sdc_001.h.

#define SDC_MASK0_DATABLOCKEND (((uint32_t) 1 ) << 10)

Mask DataBlockEnd flag.

Definition at line 271 of file sdc_001.h.

#define SDC_MASK0_DATACRCFAIL (((uint32_t) 1 ) << 1)

Mask DataCrcFail flag.

Definition at line 253 of file sdc_001.h.

#define SDC_MASK0_DATAEND (((uint32_t) 1 ) << 8)

Mask DataEnd flag.

Definition at line 267 of file sdc_001.h.

#define SDC_MASK0_DATATIMEOUT (((uint32_t) 1 ) << 3)

Mask DataTimeOut flag.

Definition at line 257 of file sdc_001.h.

#define SDC_MASK0_RXACTIVE (((uint32_t) 1 ) << 13)

Mask RxActive flag.

Definition at line 277 of file sdc_001.h.

#define SDC_MASK0_RXDATAAVLBL (((uint32_t) 1 ) << 21)

Mask RxDataAvlbl flag.

Definition at line 293 of file sdc_001.h.

#define SDC_MASK0_RXDATAERR

Value:
(SDC_MASK0_DATACRCFAIL | SDC_MASK0_DATATIMEOUT | SDC_MASK0_RXOVERRUN | \
SDC_MASK0_STARTBITERR)

Data Receive Error interrupt mask

Definition at line 301 of file sdc_001.h.

#define SDC_MASK0_RXFIFO (SDC_MASK0_RXFIFOHALFFULL | SDC_MASK0_DATABLOCKEND )

RX FIFO interrupt mask

Definition at line 306 of file sdc_001.h.

#define SDC_MASK0_RXFIFOEMPTY (((uint32_t) 1 ) << 19)

Mask RxFifoEmpty flag.

Definition at line 289 of file sdc_001.h.

#define SDC_MASK0_RXFIFOFULL (((uint32_t) 1 ) << 17)

Mask RxFifoFull flag.

Definition at line 285 of file sdc_001.h.

#define SDC_MASK0_RXFIFOHALFFULL (((uint32_t) 1 ) << 15)

Mask RxFifoHalfFull flag.

Definition at line 281 of file sdc_001.h.

#define SDC_MASK0_RXOVERRUN (((uint32_t) 1 ) << 5)

Mask RxOverrun flag.

Definition at line 261 of file sdc_001.h.

#define SDC_MASK0_STARTBITERR (((uint32_t) 1 ) << 9)

Mask StartBitErr flag.

Definition at line 269 of file sdc_001.h.

#define SDC_MASK0_TXACTIVE (((uint32_t) 1 ) << 12)

Mask TxActive flag.

Definition at line 275 of file sdc_001.h.

#define SDC_MASK0_TXDATAAVLBL (((uint32_t) 1 ) << 20)

Mask TxDataAvlbl flag.

Definition at line 291 of file sdc_001.h.

#define SDC_MASK0_TXDATAERR

Value:
(SDC_MASK0_DATACRCFAIL | SDC_MASK0_DATATIMEOUT | SDC_MASK0_TXUNDERRUN | \
SDC_MASK0_STARTBITERR)

Data Transmit Error interrupt mask

Definition at line 297 of file sdc_001.h.

#define SDC_MASK0_TXFIFO (SDC_MASK0_TXFIFOHALFEMPTY | SDC_MASK0_DATABLOCKEND )

TX FIFO interrupt mask

Definition at line 304 of file sdc_001.h.

#define SDC_MASK0_TXFIFOEMPTY (((uint32_t) 1 ) << 18)

Mask TxFifoEmpty flag.

Definition at line 287 of file sdc_001.h.

#define SDC_MASK0_TXFIFOFULL (((uint32_t) 1 ) << 16)

Mask TxFifoFull flag.

Definition at line 283 of file sdc_001.h.

#define SDC_MASK0_TXFIFOHALFEMPTY (((uint32_t) 1 ) << 14)

Mask TxFifoHalfEmpty flag.

Definition at line 279 of file sdc_001.h.

#define SDC_MASK0_TXUNDERRUN (((uint32_t) 1 ) << 4)

Mask TxUnderrun flag.

Definition at line 259 of file sdc_001.h.

#define SDC_PWR_BITMASK ((uint32_t) 0xC3)

SDC Power Control Register bit definitions.

SDC Power Control Register Bitmask

Definition at line 75 of file sdc_001.h.

#define SDC_PWR_CTRL | ( |  | n | ) | (((uint32_t) (n & 0x03)) << 0)

SDC Power Control

Definition at line 79 of file sdc_001.h.

#define SDC_PWR_CTRL_BITMASK (((uint32_t) 0x03) << 0)

SDC Power Control Bit Mask

Definition at line 77 of file sdc_001.h.

#define SDC_PWR_OPENDRAIN (((uint32_t) 1) << 6)

SD_CMD Output Control

Definition at line 81 of file sdc_001.h.

#define SDC_PWR_ROD (((uint32_t) 1) << 7)

Rod Control

Definition at line 83 of file sdc_001.h.

#define SDC_RESPCOMMAND_VAL | ( |  | n | ) | ((uint32_t) n & 0x3F)

SDC Command Response Register bit definitions.

SDC Command Response value

Definition at line 123 of file sdc_001.h.

#define SDC_STATUS_CMDACTIVE (((uint32_t) 1 ) << 11)

Command transfer in progress.

Definition at line 184 of file sdc_001.h.

#define SDC_STATUS_CMDCRCFAIL (((uint32_t) 1 ) << 0)

SDC Status Register bit definitions.

Command Response received (CRC check failed)

Definition at line 162 of file sdc_001.h.

#define SDC_STATUS_CMDERR (SDC_STATUS_CMDCRCFAIL | SDC_STATUS_CMDTIMEOUT | SDC_STATUS_STARTBITERR)

Command Error Status

Definition at line 206 of file sdc_001.h.

#define SDC_STATUS_CMDRESPEND (((uint32_t) 1 ) << 6)

Command response received (CRC check passed).

Definition at line 174 of file sdc_001.h.

#define SDC_STATUS_CMDSENT (((uint32_t) 1 ) << 7)

Command sent (no response required).

Definition at line 176 of file sdc_001.h.

#define SDC_STATUS_CMDTIMEOUT (((uint32_t) 1 ) << 2)

Command response timeout..

Definition at line 166 of file sdc_001.h.

#define SDC_STATUS_DATA (SDC_STATUS_DATAEND )

Data Transfer Status

Definition at line 217 of file sdc_001.h.

#define SDC_STATUS_DATABLOCKEND (((uint32_t) 1 ) << 10)

Data block sent/received (CRC check passed).

Definition at line 182 of file sdc_001.h.

#define SDC_STATUS_DATACRCFAIL (((uint32_t) 1 ) << 1)

Data block sent/received (CRC check failed).

Definition at line 164 of file sdc_001.h.

#define SDC_STATUS_DATAEND (((uint32_t) 1 ) << 8)

Data end (data counter is zero).

Definition at line 178 of file sdc_001.h.

#define SDC_STATUS_DATAERR

Value:
(SDC_STATUS_DATACRCFAIL | SDC_STATUS_DATATIMEOUT | SDC_STATUS_TXUNDERRUN \
| SDC_STATUS_RXOVERRUN | SDC_STATUS_STARTBITERR)

Data Error Status

Definition at line 208 of file sdc_001.h.

#define SDC_STATUS_DATATIMEOUT (((uint32_t) 1 ) << 3)

Data timeout.

Definition at line 168 of file sdc_001.h.

#define SDC_STATUS_FIFO

Value:
(SDC_STATUS_TXFIFOHALFEMPTY | SDC_STATUS_RXFIFOHALFFULL \
| SDC_STATUS_TXFIFOFULL | SDC_STATUS_RXFIFOFULL \
| SDC_STATUS_TXFIFOEMPTY | SDC_STATUS_RXFIFOEMPTY \
| SDC_STATUS_DATABLOCKEND)

FIFO Status

Definition at line 211 of file sdc_001.h.

#define SDC_STATUS_RXACTIVE (((uint32_t) 1 ) << 13)

Data receive in progress.

Definition at line 188 of file sdc_001.h.

#define SDC_STATUS_RXDATAAVLBL (((uint32_t) 1 ) << 21)

Data available in receive FIFO.

Definition at line 204 of file sdc_001.h.

#define SDC_STATUS_RXFIFOEMPTY (((uint32_t) 1 ) << 19)

Receive FIFO empty.

Definition at line 200 of file sdc_001.h.

#define SDC_STATUS_RXFIFOFULL (((uint32_t) 1 ) << 17)

Receive FIFO full.

Definition at line 196 of file sdc_001.h.

#define SDC_STATUS_RXFIFOHALFFULL (((uint32_t) 1 ) << 15)

Receive FIFO half full.

Definition at line 192 of file sdc_001.h.

#define SDC_STATUS_RXOVERRUN (((uint32_t) 1 ) << 5)

Receive FIFO overrun error.

Definition at line 172 of file sdc_001.h.

#define SDC_STATUS_STARTBITERR (((uint32_t) 1 ) << 9)

Start bit not detected on all data signals in wide bus mode..

Definition at line 180 of file sdc_001.h.

#define SDC_STATUS_TXACTIVE (((uint32_t) 1 ) << 12)

Data transmit in progress.

Definition at line 186 of file sdc_001.h.

#define SDC_STATUS_TXDATAAVLBL (((uint32_t) 1 ) << 20)

Data available in transmit FIFO.

Definition at line 202 of file sdc_001.h.

#define SDC_STATUS_TXFIFOEMPTY (((uint32_t) 1 ) << 18)

Transmit FIFO empty.

Definition at line 198 of file sdc_001.h.

#define SDC_STATUS_TXFIFOFULL (((uint32_t) 1 ) << 16)

Transmit FIFO full.

Definition at line 194 of file sdc_001.h.

#define SDC_STATUS_TXFIFOHALFEMPTY (((uint32_t) 1 ) << 14)

Transmit FIFO half empty.

Definition at line 190 of file sdc_001.h.

#define SDC_STATUS_TXUNDERRUN (((uint32_t) 1 ) << 4)

Transmit FIFO underrun error.

Definition at line 170 of file sdc_001.h.

## Enumeration Type Documentation

enum IP_SDC_001_BLOCK_SIZE_T

SDC Data Block size definitions (in bytes)

Enumerator:

  SDC_BLOCK_SIZE_1 | Block size - 1 byte
  SDC_BLOCK_SIZE_2 | Block size - 2 bytes
  SDC_BLOCK_SIZE_4 | Block size - 4 bytes
  SDC_BLOCK_SIZE_8 | Block size - 8 bytes
  SDC_BLOCK_SIZE_16 | Block size - 16 bytes
  SDC_BLOCK_SIZE_32 | Block size - 32 bytes
  SDC_BLOCK_SIZE_64 | Block size - 64 bytes
  SDC_BLOCK_SIZE_128 | Block size - 128 bytes
  SDC_BLOCK_SIZE_256 | Block size - 256 bytes
  SDC_BLOCK_SIZE_512 | Block size - 512 bytes
  SDC_BLOCK_SIZE_1024 | Block size - 1024 bytes
  SDC_BLOCK_SIZE_2048 | Block size - 2048 bytes

Definition at line 366 of file sdc_001.h.

enum IP_SDC_001_CLOCK_CTRL_T

SDC Clock Control Options.

Enumerator:

  SDC_CLOCK_ENABLE | Enable SD Card Bus Clock
  SDC_CLOCK_POWER_SAVE | Disable SD_CLK output when bus is idle
  SDC_CLOCK_DIVIDER_BYPASS | Enable bypass of clock divide logic
  SDC_CLOCK_WIDEBUS_MODE | Enable wide bus mode (SD_DAT[3:0] is used instead of SD_DAT[0])

Definition at line 331 of file sdc_001.h.

enum IP_SDC_001_PWR_CTRL_T

SDC Power Control Options.

Enumerator:

  SDC_POWER_OFF | Power-off
  SDC_POWER_UP | Power-up
  SDC_POWER_ON | Power-on

Definition at line 322 of file sdc_001.h.

enum IP_SDC_001_RESPONSE_T

SDC Response type.

Enumerator:

  SDC_NO_RESPONSE | No response
  SDC_SHORT_RESPONSE | Short response
  SDC_LONG_RESPONSE | Long response

Definition at line 341 of file sdc_001.h.

enum IP_SDC_001_TRANSFER_DIR_T

SDC Data Transfer Direction definitions.

Enumerator:

  SDC_TRANSFER_DIR_FROMCARD | Transfer from card
  SDC_TRANSFER_DIR_TOCARD | Transfer to card

Definition at line 350 of file sdc_001.h.

enum IP_SDC_001_TRANSFER_MODE_T

SDC Data Transfer Mode definitions.

Enumerator:

  SDC_TRANSFER_MODE_STREAM | Stream transfer mode
  SDC_TRANSFER_MODE_BLOCK | Block transfer mode

Definition at line 358 of file sdc_001.h.

## Function Documentation

STATIC INLINE void IP_SDC_ClearStatus | ( | IP_SDC_001_T * | pSDC,
|  | uint32_t | flag
| ) |  |

Clear status of SDC Peripheral.

Parameters

  pSDC | : Pointer to SDC register block
  flag | : Status flag(s) to be cleared (Or-ed bit value of SDC_CLEAR_*)

Returns
  None

Definition at line 514 of file sdc_001.h.

void IP_SDC_ClockControl | ( | IP_SDC_001_T * | pSDC,
|  | IP_SDC_001_CLOCK_CTRL_T | ctrlType,
|  | FunctionalState | NewState
| ) |  |

Set or Reset clock control of SDC peripheral.

Parameters

  pSDC | : Pointer to SDC register block
  ctrlType | : Clock Control type
  NewState | : New State to set

Returns
  Nothing

Definition at line 74 of file sdc_001.c.

STATIC INLINE void IP_SDC_DeInit | ( | IP_SDC_001_T * | pSDC | ) |

Deinitialise the SDC peripheral.

Parameters

  pSDC | : Pointer to SDC register block

Returns
  None

Definition at line 542 of file sdc_001.h.

void IP_SDC_GetResp | ( | IP_SDC_001_T * | pSDC,
|  | IP_SDC_001_RESP_T * | pResp
| ) |  |

Get SDC Response.

Parameters

  pSDC | : Pointer to SDC register block
  pResp | : Pointer to buffer storing response data

Returns
  Nothing

Definition at line 140 of file sdc_001.c.

STATIC INLINE uint32_t IP_SDC_GetStatus | ( | IP_SDC_001_T * | pSDC | ) |

Get status of SDC Peripheral.

Parameters

  pSDC | : Pointer to SDC register block

Returns
  Status (Or-ed bit value of SDC_STATUS_*)

Definition at line 503 of file sdc_001.h.

void IP_SDC_Init | ( | IP_SDC_001_T * | pSDC | ) |

Initialize the SDC card controller.

Parameters

  pSDC | : Pointer to SDC register block

Returns
  None

Definition at line 87 of file sdc_001.c.

void IP_SDC_PowerControl | ( | IP_SDC_001_T * | pSDC,
|  | IP_SDC_001_PWR_CTRL_T | pwrMode,
|  | uint32_t | flag
| ) |  |

Set the power state of SDC peripheral.

Parameters

  pSDC | : Pointer to SDC register block
  pwrMode | : Power mode
  flag | : Output control flag

Returns
  Nothing

Note
  When the external power supply is switched on, the software first enters the power-up state, and waits until the supply output is stable before moving to the power-on state. During the power-up state, SD_PWR is set HIGH. The card bus outlets are disabled during both states. flag is or-ed bit value of SDC_PWR_OPENDRAIN and SDC_PWR_ROD

Definition at line 58 of file sdc_001.c.

void IP_SDC_ReadFIFO | ( | IP_SDC_001_T * | pSDC,
|  | uint32_t * | pDst,
|  | bool | bFirstHalf
| ) |  |

Write Data to FIFO.

Parameters

  pSDC | : Pointer to SDC register block
  pDst | : The buffer hold the data read
  bFirstHalf | : true (read the first half of FIFO) false (read the second half of FIFO)

Returns
  Nothing

Definition at line 179 of file sdc_001.c.

void IP_SDC_ResetCommand | ( | IP_SDC_001_T * | pSDC | ) |

Reset SDC Command Information.

Parameters

  pSDC | : Pointer to SDC register block

Returns
  Nothing

Definition at line 128 of file sdc_001.c.

void IP_SDC_SetClockDiv | ( | IP_SDC_001_T * | pSDC,
|  | uint8_t | div
| ) |  |

Set clock divider value for SDC peripheral.

Parameters

  pSDC | : Pointer to SDC register block
  div | : clock divider

Returns
  Nothing

Note
  While the SD card interface is in identification mode, the SD_CLK frequency must be less than 400 kHz. The clock frequency can be changed to the maximum card bus frequency when relative card addresses are assigned to all cards. SD_CLK frequency = MCLK / [2x(ClkDiv+1)].

Definition at line 65 of file sdc_001.c.

void IP_SDC_SetCommand | ( | IP_SDC_001_T * | pSDC,
|  | uint32_t | Cmd,
|  | uint32_t | Arg
| ) |  |

Set SDC Command Information.

Parameters

  pSDC | : Pointer to SDC register block
  Cmd | : Command value
  Arg | : Argument for the command

Returns
  Nothing

Definition at line 113 of file sdc_001.c.

STATIC INLINE void IP_SDC_SetDataTimer | ( | IP_SDC_001_T * | pSDC,
|  | uint32_t | timeout
| ) |  |

Set SDC Data Timeout Period.

Parameters

  pSDC | : Pointer to SDC register block
  timeout | : Data timeout value in card bus clock periods

Returns
  Nothing

Definition at line 467 of file sdc_001.h.

void IP_SDC_SetDataTransfer | ( | IP_SDC_001_T * | pSDC,
|  | IP_SDC_001_DATA_TRANSFER_T * | pTransfer
| ) |  |

Set SDC Data Transfer Information.

Parameters

  pSDC | : Pointer to SDC register block
  pTransfer | : Pointer to Data Transfer structure

Returns
  Nothing

Definition at line 150 of file sdc_001.c.

STATIC INLINE void IP_SDC_SetIntMask | ( | IP_SDC_001_T * | pSDC,
|  | uint32_t | mask
| ) |  |

Set interrupt mask for SDC Peripheral.

Parameters

  pSDC | : Pointer to SDC register block
  mask | : Interrupt mask (Or-ed bit value of SDC_MASK0_*)

Returns
  None

Definition at line 525 of file sdc_001.h.

void IP_SDC_WriteFIFO | ( | IP_SDC_001_T * | pSDC,
|  | uint32_t * | pSrc,
|  | bool | bFirstHalf
| ) |  |

Write Data to FIFO.

Parameters

  pSDC | : Pointer to SDC register block
  pSrc | : Pointer to data buffer
  bFirstHalf | : true (write to the first half of FIFO) false (write to the second half of FIFO)

Returns
  Nothing

Definition at line 165 of file sdc_001.c.