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sysinit_ngx_xplorer_18304330.c
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1 /*
2 * Copyright(C) NXP Semiconductors, 2012
3 * All rights reserved.
4 *
5 * Software that is described herein is for illustrative purposes only
6 * which provides customers with programming information regarding the
7 * LPC products. This software is supplied "AS IS" without any warranties of
8 * any kind, and NXP Semiconductors and its licensor disclaim any and
9 * all warranties, express or implied, including all implied warranties of
10 * merchantability, fitness for a particular purpose and non-infringement of
11 * intellectual property rights. NXP Semiconductors assumes no responsibility
12 * or liability for the use of the software, conveys no license or rights under any
13 * patent, copyright, mask work right, or any other intellectual property rights in
14 * or to any products. NXP Semiconductors reserves the right to make changes
15 * in the software without notification. NXP Semiconductors also makes no
16 * representation or warranty that such application will be suitable for the
17 * specified use without further testing or modification.
18 *
19 * Permission to use, copy, modify, and distribute this software and its
20 * documentation is hereby granted, under NXP Semiconductors' and its
21 * licensor's relevant copyrights in the software, without fee, provided that it
22 * is used in conjunction with NXP Semiconductors microcontrollers. This
23 * copyright, permission, and disclaimer notice must appear in all copies of
24 * this code.
25 */
26
27 #include "board.h"
28
51 #ifndef CORE_M0
52 /* SCR pin definitions for pin muxing */
53 typedef struct {
54 uint8_t pingrp; /* Pin group */
55 uint8_t pinnum; /* Pin number */
56 uint16_t modefunc; /* Pin mode and function for SCU */
57 } PINMUX_GRP_T;
58
59 /* Structure for initial base clock states */
60 struct CLK_BASE_STATES {
61 CHIP_CGU_BASE_CLK_T clk; /* Base clock */
62 CHIP_CGU_CLKIN_T clkin; /* Base clock source, see UM for allowable souorces per base clock */
63 bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */
64 bool powerdn; /* Set to true if the base clock is initially powered down */
65 };
66
67 /* Initial base clock states are mostly on */
68 STATIC const struct CLK_BASE_STATES InitClkStates[] = {
69 {CLK_BASE_SAFE, CLKIN_IRC, true, false},
70 {CLK_BASE_APB1, CLKIN_MAINPLL, true, false},
71 {CLK_BASE_APB3, CLKIN_MAINPLL, true, false},
72 {CLK_BASE_USB0, CLKIN_USBPLL, true, true},
73 #if defined(CHIP_LPC43XX)
74 {CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false},
75 {CLK_BASE_SPI, CLKIN_MAINPLL, true, false},
76 {CLK_BASE_VADC, CLKIN_MAINPLL, true, true},
77 #endif
78 {CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false},
79 #if defined(USE_RMII)
80 {CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false},
81 #else
82 {CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false},
83 #endif
84 {CLK_BASE_SDIO, CLKIN_MAINPLL, true, false},
85 {CLK_BASE_SSP0, CLKIN_MAINPLL, true, false},
86 {CLK_BASE_SSP1, CLKIN_MAINPLL, true, false},
87 {CLK_BASE_UART0, CLKIN_MAINPLL, true, false},
88 {CLK_BASE_UART1, CLKIN_MAINPLL, true, false},
89 {CLK_BASE_UART2, CLKIN_MAINPLL, true, false},
90 {CLK_BASE_UART3, CLKIN_MAINPLL, true, false},
91 {CLK_BASE_OUT, CLKINPUT_PD, true, false},
92 {CLK_BASE_APLL, CLKINPUT_PD, true, false},
93 {CLK_BASE_CGU_OUT0, CLKINPUT_PD, true, false},
94 {CLK_BASE_CGU_OUT1, CLKINPUT_PD, true, false},
95
96 /* Clocks derived from dividers */
97 {CLK_BASE_LCD, CLKIN_IDIVC, true, false},
98 {CLK_BASE_USB1, CLKIN_IDIVD, true, true}
99 };
100
101 /* SPIFI high speed pin mode setup */
102 STATIC const PINMUX_GRP_T spifipinmuxing[] = {
103 {0x3, 3, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI CLK */
104 {0x3, 4, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D3 */
105 {0x3, 5, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D2 */
106 {0x3, 6, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D1 */
107 {0x3, 7, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D0 */
108 {0x3, 8, (SCU_PINIO_FAST | SCU_MODE_FUNC3)} /* SPIFI CS/SSEL */
109 };
110
111 /* USB PLL pre-initialized setup values for 480MHz output rate */
112 static const CGU_USBAUDIO_PLL_SETUP_T usbPLLSetup = {
113 0x0000601D, /* Default control with main osc input, PLL disabled */
114 0x06167FFA, /* M-divider value for 480MHz output from 12MHz input */
115 0x00000000, /* N-divider value */
116 0x00000000 /* Not applicable for USB PLL */
117 };
118
119 /* Audio PLL pre-initialized setup values for FIXME output rate */
120 // static const CGU_USBAUDIO_PLL_SETUP_T audioPLLSetup = {
121 // 0x0000601D, /* Default control with main osc input, PLL disabled */
122 // 0x06167FFA, /* M-divider value for FIXME output from 12MHz input */
123 // 0x00000000, /* N-divider value */
124 // 0x00000000 /* FIXME */
125 // };
126
127 /* Setup system clocking */
128 STATIC void SystemSetupClocking(void)
129 {
130 int i;
131
132 /* Switch main system clocking to crystal */
133 Chip_Clock_EnableCrystal();
134 Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false);
135
136 /* Setup PLL for 100MHz and switch main system clocking */
137 Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000);
138 Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);
139
140 /* Setup PLL for maximum clock */
141 Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ);
142
143 /* Setup system base clocks and initial states. This won't enable and
144 disable individual clocks, but sets up the base clock sources for
145 each individual peripheral clock. */
146 for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
147 Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
148 InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
149 }
150
151 /* Reset and enable 32Khz oscillator */
152 LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
153 LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
154
155 /* SPIFI pin setup is done prior to setting up system clocking */
156 for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) {
157 Chip_SCU_PinMuxSet(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum,
158 spifipinmuxing[i].modefunc);
159 }
160
161 /* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
162 Divide rate is based on CPU speed and speed of SPI FLASH part. */
163 #if (MAX_CLOCK_FREQ > 180000000)
164 Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
165 #else
166 Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
167 #endif
168 Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
169
170 /* Attach main PLL clock to divider C with a divider of 2 */
171 Chip_Clock_SetDivider(CLK_IDIV_C, CLKIN_MAINPLL, 2);
172
173 /* Setup default USB PLL state for a 480MHz output and attach */
174 Chip_Clock_SetupPLL(CLKIN_CRYSTAL, CGU_USB_PLL, &usbPLLSetup);
175
176 /* USB1 needs a 60MHz clock. To get it, a divider of 4 and then 2 are
177 chained to make a divide by 8 function. Connect the output of
178 divider D to the USB1 base clock. */
179 Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_USBPLL, 4);
180 Chip_Clock_SetDivider(CLK_IDIV_D, CLKIN_IDIVA, 2);
181 Chip_Clock_SetBaseClock(CLK_BASE_USB1, CLKIN_IDIVD, true, true);
182
183 /* Setup default audio PLL state for a FIXME output */
184 // Chip_Clock_SetupPLL(CGU_AUDIO_PLL, &audioPLLSetup); // FIXME
185 }
186
187 STATIC const PINMUX_GRP_T pinmuxing[] = {
188 /* RMII pin group */
189 {0x1, 15,
190 (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
191 {0x0, 0,
192 (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2)},
193 {0x1, 16,
194 (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC7)},
195 {0x0, 1, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC6)},
196 {0x1, 19,
197 (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0)},
198 {0x1, 18, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
199 {0x1, 20, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
200 {0x1, 17,
201 (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
202 {0x2, 0, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC7)},
203 /* Board LEDs */
204 {0x2, 11, (SCU_MODE_MODE_REPEATER | SCU_MODE_FUNC0)},
205 {0x2, 12, (SCU_MODE_MODE_REPEATER | SCU_MODE_FUNC0)},
206 /* I2S */
207 {0x3, 0, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
208 {0x6, 0, (SCU_PINIO_FAST | SCU_MODE_FUNC4)},
209 {0x7, 2, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
210 {0x6, 2, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
211 {0x7, 1, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
212 {0x6, 1, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
213 };
214
215 /* Sets up system pin muxing */
216 STATIC void SystemSetupMuxing(void)
217 {
218 int i;
219
220 /* Setup system level pin muxing */
221 for (i = 0; i < (sizeof(pinmuxing) / sizeof(pinmuxing[0])); i++) {
222 Chip_SCU_PinMuxSet(pinmuxing[i].pingrp, pinmuxing[i].pinnum,
223 pinmuxing[i].modefunc);
224 }
225 }
226
227 /* Nothing to do for the Xplorer board */
228 STATIC void SystemSetupMemory(void)
229 {}
230
231 #endif
232
240 void SystemInit(void)
241 {
242 #if defined(CORE_M3) || defined(CORE_M4)
243 unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
244
245 #if defined(__IAR_SYSTEMS_ICC__)
246 extern void *__vector_table;
247
248 *pSCB_VTOR = (unsigned int) &__vector_table;
249 #elif defined(__CODE_RED)
250 extern void *g_pfnVectors;
251
252 *pSCB_VTOR = (unsigned int) &g_pfnVectors;
253 #elif defined(__ARMCC_VERSION)
254 extern void *__Vectors;
255
256 *pSCB_VTOR = (unsigned int) &__Vectors;
257 #endif
258
259 #if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
260 fpuInit();
261 #endif
262
263 /* Setup system clocking and memory. This is done early to allow the
264 application and tools to clear memory and use scatter loading to
265 external memory. */
266 SystemSetupClocking();
267 SystemSetupMuxing();
268 SystemSetupMemory();
269 #endif
270 }
271