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fpu_init.c
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1 /*
2 * @brief FPU init code
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #if defined(CORE_M4)
33
34 #include "stdint.h"
35
36 /*****************************************************************************
37 * Private types/enumerations/variables
38 ****************************************************************************/
39
40 #define LPC_CPACR 0xE000ED88
41
42 #define SCB_MVFR0 0xE000EF40
43 #define SCB_MVFR0_RESET 0x10110021
44
45 #define SCB_MVFR1 0xE000EF44
46 #define SCB_MVFR1_RESET 0x11000011
47
48 /*****************************************************************************
49 * Public types/enumerations/variables
50 ****************************************************************************/
51
52 /*****************************************************************************
53 * Private functions
54 ****************************************************************************/
55
56 /*****************************************************************************
57 * Public functions
58 ****************************************************************************/
59
60 /* Early initialization of the FPU */
61 void fpuInit(void)
62 {
63 // from arm trm manual:
64 // ; CPACR is located at address 0xE000ED88
65 // LDR.W R0, =0xE000ED88
66 // ; Read CPACR
67 // LDR R1, [R0]
68 // ; Set bits 20-23 to enable CP10 and CP11 coprocessors
69 // ORR R1, R1, #(0xF << 20)
70 // ; Write back the modified value to the CPACR
71 // STR R1, [R0]
72
73 volatile uint32_t *regCpacr = (uint32_t *) LPC_CPACR;
74 volatile uint32_t *regMvfr0 = (uint32_t *) SCB_MVFR0;
75 volatile uint32_t *regMvfr1 = (uint32_t *) SCB_MVFR1;
76 volatile uint32_t Cpacr;
77 volatile uint32_t Mvfr0;
78 volatile uint32_t Mvfr1;
79 char vfpPresent = 0;
80
81 Mvfr0 = *regMvfr0;
82 Mvfr1 = *regMvfr1;
83
84 vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
85
86 if (vfpPresent) {
87 Cpacr = *regCpacr;
88 Cpacr |= (0xF << 20);
89 *regCpacr = Cpacr; // enable CP10 and CP11 for full access
90 }
91
92 }
93
94 #endif /* defined(CORE_M4 */