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cpu.h
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1 /*
2 *********************************************************************************************************
3 * uC/CPU
4 * CPU CONFIGURATION & PORT LAYER
5 *
6 * (c) Copyright 2004-2011; Micrium, Inc.; Weston, FL
7 *
8 * All rights reserved. Protected by international copyright laws.
9 *
10 * uC/CPU is provided in source form to registered licensees ONLY. It is
11 * illegal to distribute this source code to any third party unless you receive
12 * written permission by an authorized Micrium representative. Knowledge of
13 * the source code may NOT be used to develop a similar product.
14 *
15 * Please help us continue to provide the Embedded community with the finest
16 * software available. Your honesty is greatly appreciated.
17 *
18 * You can contact us at www.micrium.com.
19 *********************************************************************************************************
20 */
21
22 /*
23 *********************************************************************************************************
24 *
25 * CPU PORT FILE
26 *
27 * ARM-Cortex-M4
28 * IAR Embedded Workbench
29 * IAR Tool chain
30 *
31 * Filename : cpu.h
32 * Version : V1.28.00.00
33 * Programmer(s) : JJL
34 * BAN
35 *********************************************************************************************************
36 */
37
38
39 /*
40 *********************************************************************************************************
41 * MODULE
42 *********************************************************************************************************
43 */
44
45 #ifndef CPU_MODULE_PRESENT
46 #define CPU_MODULE_PRESENT
47
48
49 /*
50 *********************************************************************************************************
51 * CPU INCLUDE FILES
52 *
53 * Note(s) : (1) The following CPU files are located in the following directories :
54 *
55 * (a) <Your Product Application>\cpu_cfg.h
56 *
57 * (b) <CPU-Compiler Directory>\cpu_def.h
58 *
59 * (c) <CPU-Compiler Directory><cpu><compiler>\cpu*.*
60 *
61 * where
62 * <Your Product Application> directory path for Your Product's Application
63 * <CPU-Compiler Directory> directory path for common CPU-compiler software
64 * <cpu> directory name for specific CPU
65 * <compiler> directory name for specific compiler
66 *
67 * (2) Compiler MUST be configured to include the '<CPU-Compiler Directory>\' directory the
68 * specific CPU-compiler directory, & '<Your Product Application>\' as additional include
69 * path directories.
70 *
71 * (3) Since NO custom library modules are included, 'cpu.h' may ONLY use configurations from
72 * CPU configuration file 'cpu_cfg.h' that do NOT reference any custom library definitions.
73 *
74 * In other words, 'cpu.h' may use 'cpu_cfg.h' configurations that are #define'd to numeric
75 * constants or to NULL (i.e. NULL-valued #define's); but may NOT use configurations to
76 * custom library #define's (e.g. DEF_DISABLED or DEF_ENABLED).
77 *********************************************************************************************************
78 */
79
80 #include <cpu_def.h>
81 #include <cpu_cfg.h> /* See Note #3. */
82
83
84 /*$PAGE*/
85 /*
86 *********************************************************************************************************
87 * CONFIGURE STANDARD DATA TYPES
88 *
89 * Note(s) : (1) Configure standard data types according to CPU-/compiler-specifications.
90 *
91 * (2) (a) (1) 'CPU_FNCT_VOID' data type defined to replace the commonly-used function pointer
92 * data type of a pointer to a function which returns void & has no arguments.
93 *
94 * (2) Example function pointer usage :
95 *
96 * CPU_FNCT_VOID FnctName;
97 *
98 * FnctName();
99 *
100 * (b) (1) 'CPU_FNCT_PTR' data type defined to replace the commonly-used function pointer
101 * data type of a pointer to a function which returns void & has a single void
102 * pointer argument.
103 *
104 * (2) Example function pointer usage :
105 *
106 * CPU_FNCT_PTR FnctName;
107 * void *p_obj
108 *
109 * FnctName(p_obj);
110 *********************************************************************************************************
111 */
112
113 typedef void CPU_VOID;
114 typedef char CPU_CHAR; /* 8-bit character */
115 typedef unsigned char CPU_BOOLEAN; /* 8-bit boolean or logical */
116 typedef unsigned char CPU_INT08U; /* 8-bit unsigned integer */
117 typedef signed char CPU_INT08S; /* 8-bit signed integer */
118 typedef unsigned short CPU_INT16U; /* 16-bit unsigned integer */
119 typedef signed short CPU_INT16S; /* 16-bit signed integer */
120 typedef unsigned int CPU_INT32U; /* 32-bit unsigned integer */
121 typedef signed int CPU_INT32S; /* 32-bit signed integer */
122 typedef unsigned long long CPU_INT64U; /* 64-bit unsigned integer */
123 typedef signed long long CPU_INT64S; /* 64-bit signed integer */
124
125 typedef float CPU_FP32; /* 32-bit floating point */
126 typedef double CPU_FP64; /* 64-bit floating point */
127
128
129 typedef volatile CPU_INT08U CPU_REG08; /* 8-bit register */
130 typedef volatile CPU_INT16U CPU_REG16; /* 16-bit register */
131 typedef volatile CPU_INT32U CPU_REG32; /* 32-bit register */
132 typedef volatile CPU_INT64U CPU_REG64; /* 64-bit register */
133
134
135 typedef void (*CPU_FNCT_VOID)(void); /* See Note #2a. */
136 typedef void (*CPU_FNCT_PTR )(void *p_obj); /* See Note #2b. */
137
138
139 /*$PAGE*/
140 /*
141 *********************************************************************************************************
142 * CPU WORD CONFIGURATION
143 *
144 * Note(s) : (1) Configure CPU_CFG_ADDR_SIZE & CPU_CFG_DATA_SIZE with CPU's word sizes :
145 *
146 * CPU_WORD_SIZE_08 8-bit word size
147 * CPU_WORD_SIZE_16 16-bit word size
148 * CPU_WORD_SIZE_32 32-bit word size
149 * CPU_WORD_SIZE_64 64-bit word size See Note #1a
150 *
151 * (a) 64-bit word size NOT currently supported.
152 *
153 * (2) Configure CPU_CFG_ENDIAN_TYPE with CPU's data-word-memory order :
154 *
155 * (a) CPU_ENDIAN_TYPE_BIG Big- endian word order (CPU words' most significant
156 * octet @ lowest memory address)
157 * (b) CPU_ENDIAN_TYPE_LITTLE Little-endian word order (CPU words' least significant
158 * octet @ lowest memory address)
159 *********************************************************************************************************
160 */
161
162 /* Define CPU word sizes (see Note #1) : */
163 #define CPU_CFG_ADDR_SIZE CPU_WORD_SIZE_32 /* Defines CPU address word size (in octets). */
164 #define CPU_CFG_DATA_SIZE CPU_WORD_SIZE_32 /* Defines CPU data word size (in octets). */
165
166 #define CPU_CFG_ENDIAN_TYPE CPU_ENDIAN_TYPE_LITTLE /* Defines CPU data word-memory order (see Note #2). */
167
168
169 /*
170 *********************************************************************************************************
171 * CONFIGURE CPU ADDRESS & DATA TYPES
172 *********************************************************************************************************
173 */
174
175 /* CPU address type based on address bus size. */
176 #if (CPU_CFG_ADDR_SIZE == CPU_WORD_SIZE_32)
177 typedef CPU_INT32U CPU_ADDR;
178 #elif (CPU_CFG_ADDR_SIZE == CPU_WORD_SIZE_16)
179 typedef CPU_INT16U CPU_ADDR;
180 #else
181 typedef CPU_INT08U CPU_ADDR;
182 #endif
183
184 /* CPU data type based on data bus size. */
185 #if (CPU_CFG_DATA_SIZE == CPU_WORD_SIZE_32)
186 typedef CPU_INT32U CPU_DATA;
187 #elif (CPU_CFG_DATA_SIZE == CPU_WORD_SIZE_16)
188 typedef CPU_INT16U CPU_DATA;
189 #else
190 typedef CPU_INT08U CPU_DATA;
191 #endif
192
193
194 typedef CPU_DATA CPU_ALIGN; /* Defines CPU data-word-alignment size. */
195 typedef CPU_ADDR CPU_SIZE_T; /* Defines CPU standard 'size_t' size. */
196
197
198 /*
199 *********************************************************************************************************
200 * CPU STACK CONFIGURATION
201 *
202 * Note(s) : (1) Configure CPU_CFG_STK_GROWTH in 'cpu.h' with CPU's stack growth order :
203 *
204 * (a) CPU_STK_GROWTH_LO_TO_HI CPU stack pointer increments to the next higher stack
205 * memory address after data is pushed onto the stack
206 * (b) CPU_STK_GROWTH_HI_TO_LO CPU stack pointer decrements to the next lower stack
207 * memory address after data is pushed onto the stack
208 *********************************************************************************************************
209 */
210
211 #define CPU_CFG_STK_GROWTH CPU_STK_GROWTH_HI_TO_LO /* Defines CPU stack growth order (see Note #1). */
212
213 typedef CPU_INT32U CPU_STK; /* Defines CPU stack word size (in octets). */
214 typedef CPU_ADDR CPU_STK_SIZE; /* Defines CPU stack size (in number of CPU_STKs). */
215
216
217 /*$PAGE*/
218 /*
219 *********************************************************************************************************
220 * CRITICAL SECTION CONFIGURATION
221 *
222 * Note(s) : (1) Configure CPU_CFG_CRITICAL_METHOD with CPU's/compiler's critical section method :
223 *
224 * Enter/Exit critical sections by ...
225 *
226 * CPU_CRITICAL_METHOD_INT_DIS_EN Disable/Enable interrupts
227 * CPU_CRITICAL_METHOD_STATUS_STK Push/Pop interrupt status onto stack
228 * CPU_CRITICAL_METHOD_STATUS_LOCAL Save/Restore interrupt status to local variable
229 *
230 * (a) CPU_CRITICAL_METHOD_INT_DIS_EN is NOT a preferred method since it does NOT support
231 * multiple levels of interrupts. However, with some CPUs/compilers, this is the only
232 * available method.
233 *
234 * (b) CPU_CRITICAL_METHOD_STATUS_STK is one preferred method since it supports multiple
235 * levels of interrupts. However, this method assumes that the compiler provides C-level
236 * &/or assembly-level functionality for the following :
237 *
238 * ENTER CRITICAL SECTION :
239 * (1) Push/save interrupt status onto a local stack
240 * (2) Disable interrupts
241 *
242 * EXIT CRITICAL SECTION :
243 * (3) Pop/restore interrupt status from a local stack
244 *
245 * (c) CPU_CRITICAL_METHOD_STATUS_LOCAL is one preferred method since it supports multiple
246 * levels of interrupts. However, this method assumes that the compiler provides C-level
247 * &/or assembly-level functionality for the following :
248 *
249 * ENTER CRITICAL SECTION :
250 * (1) Save interrupt status into a local variable
251 * (2) Disable interrupts
252 *
253 * EXIT CRITICAL SECTION :
254 * (3) Restore interrupt status from a local variable
255 *
256 * (2) Critical section macro's most likely require inline assembly. If the compiler does NOT
257 * allow inline assembly in C source files, critical section macro's MUST call an assembly
258 * subroutine defined in a 'cpu_a.asm' file located in the following software directory :
259 *
260 * <CPU-Compiler Directory><cpu><compiler>\
261 *
262 * where
263 * <CPU-Compiler Directory> directory path for common CPU-compiler software
264 * <cpu> directory name for specific CPU
265 * <compiler> directory name for specific compiler
266 *
267 * (3) (a) To save/restore interrupt status, a local variable 'cpu_sr' of type 'CPU_SR' MAY need
268 * to be declared (e.g. if 'CPU_CRITICAL_METHOD_STATUS_LOCAL' method is configured).
269 *
270 * (1) 'cpu_sr' local variable SHOULD be declared via the CPU_SR_ALLOC() macro which, if
271 * used, MUST be declared following ALL other local variables.
272 *
273 * Example :
274 *
275 * void Fnct (void)
276 * {
277 * CPU_INT08U val_08;
278 * CPU_INT16U val_16;
279 * CPU_INT32U val_32;
280 * CPU_SR_ALLOC(); MUST be declared after ALL other local variables
281 * :
282 * :
283 * }
284 *
285 * (b) Configure 'CPU_SR' data type with the appropriate-sized CPU data type large enough to
286 * completely store the CPU's/compiler's status word.
287 *********************************************************************************************************
288 */
289 /*$PAGE*/
290 /* Configure CPU critical method (see Note #1) : */
291 #define CPU_CFG_CRITICAL_METHOD CPU_CRITICAL_METHOD_STATUS_LOCAL
292
293 typedef CPU_INT32U CPU_SR; /* Defines CPU status register size (see Note #3b). */
294
295 /* Allocates CPU status register word (see Note #3a). */
296 #if (CPU_CFG_CRITICAL_METHOD == CPU_CRITICAL_METHOD_STATUS_LOCAL)
297 #define CPU_SR_ALLOC() CPU_SR cpu_sr = (CPU_SR)0
298 #else
299 #define CPU_SR_ALLOC()
300 #endif
301
302
303
304 #define CPU_INT_DIS() do { cpu_sr = CPU_SR_Save(); } while (0) /* Save CPU status word & disable interrupts.*/
305 #define CPU_INT_EN() do { CPU_SR_Restore(cpu_sr); } while (0) /* Restore CPU status word. */
306
307
308 #ifdef CPU_CFG_INT_DIS_MEAS_EN
309 /* Disable interrupts, ... */
310 /* & start interrupts disabled time measurement.*/
311 #define CPU_CRITICAL_ENTER() do { CPU_INT_DIS(); \
312 CPU_IntDisMeasStart(); } while (0)
313 /* Stop & measure interrupts disabled time, */
314 /* ... & re-enable interrupts. */
315 #define CPU_CRITICAL_EXIT() do { CPU_IntDisMeasStop(); \
316 CPU_INT_EN(); } while (0)
317
318 #else
319
320 #define CPU_CRITICAL_ENTER() do { CPU_INT_DIS(); } while (0) /* Disable interrupts. */
321 #define CPU_CRITICAL_EXIT() do { CPU_INT_EN(); } while (0) /* Re-enable interrupts. */
322
323 #endif
324
325
326 /*$PAGE*/
327 /*
328 *********************************************************************************************************
329 * FUNCTION PROTOTYPES
330 *
331 * Note(s) : (1) CPU_CntLeadZeros() prototyped/defined respectively in :
332 *
333 * (a) 'cpu.h'/'cpu_a.asm', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT #define'd in 'cpu.h'/
334 * 'cpu_cfg.h' to enable assembly-version function
335 *
336 * (b) 'cpu_core.h'/'cpu_core.c', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT NOT #define'd in 'cpu.h'/
337 * 'cpu_cfg.h' to enable C-source-version function otherwise
338 *
339 * See also 'cpu_core.h FUNCTION PROTOTYPES Note #2'.
340 *********************************************************************************************************
341 */
342
343 void CPU_IntDis (void);
344 void CPU_IntEn (void);
345
346 void CPU_IntSrcDis (CPU_INT08U pos);
347 void CPU_IntSrcEn (CPU_INT08U pos);
348 void CPU_IntSrcPendClr(CPU_INT08U pos);
349 CPU_INT16S CPU_IntSrcPrioGet(CPU_INT08U pos);
350 void CPU_IntSrcPrioSet(CPU_INT08U pos,
351 CPU_INT08U prio);
352
353
354 CPU_SR CPU_SR_Save (void);
355 void CPU_SR_Restore (CPU_SR cpu_sr);
356
357
358 #define CPU_CFG_LEAD_ZEROS_ASM_PRESENT /* See Note #1. */
359
360 CPU_DATA CPU_CntLeadZeros (CPU_DATA val);
361 CPU_DATA CPU_RevBits (CPU_DATA val);
362
363
364 void CPU_WaitForInt (void);
365 void CPU_WaitForExcept(void);
366
367
368 void CPU_BitBandClr (CPU_ADDR addr,
369 CPU_INT08U bit_nbr);
370 void CPU_BitBandSet (CPU_ADDR addr,
371 CPU_INT08U bit_nbr);
372
373
374 /*$PAGE*/
375 /*
376 *********************************************************************************************************
377 * INTERRUPT SOURCES
378 *********************************************************************************************************
379 */
380
381 #define CPU_INT_STK_PTR 0u
382 #define CPU_INT_RESET 1u
383 #define CPU_INT_NMI 2u
384 #define CPU_INT_HFAULT 3u
385 #define CPU_INT_MEM 4u
386 #define CPU_INT_BUSFAULT 5u
387 #define CPU_INT_USAGEFAULT 6u
388 #define CPU_INT_RSVD_07 7u
389 #define CPU_INT_RSVD_08 8u
390 #define CPU_INT_RSVD_09 9u
391 #define CPU_INT_RSVD_10 10u
392 #define CPU_INT_SVCALL 11u
393 #define CPU_INT_DBGMON 12u
394 #define CPU_INT_RSVD_13 13u
395 #define CPU_INT_PENDSV 14u
396 #define CPU_INT_SYSTICK 15u
397 #define CPU_INT_EXT0 16u
398
399
400 /*
401 *********************************************************************************************************
402 * CPU REGISTERS
403 *********************************************************************************************************
404 */
405
406 #define CPU_REG_NVIC_NVIC (*((CPU_REG32 *)(0xE000E004))) /* Int Ctrl'er Type Reg. */
407 #define CPU_REG_NVIC_ST_CTRL (*((CPU_REG32 *)(0xE000E010))) /* SysTick Ctrl & Status Reg. */
408 #define CPU_REG_NVIC_ST_RELOAD (*((CPU_REG32 *)(0xE000E014))) /* SysTick Reload Value Reg. */
409 #define CPU_REG_NVIC_ST_CURRENT (*((CPU_REG32 *)(0xE000E018))) /* SysTick Current Value Reg. */
410 #define CPU_REG_NVIC_ST_CAL (*((CPU_REG32 *)(0xE000E01C))) /* SysTick Calibration Value Reg. */
411
412 #define CPU_REG_NVIC_SETEN(n) (*((CPU_REG32 *)(0xE000E100 + (n) * 4u))) /* IRQ Set En Reg. */
413 #define CPU_REG_NVIC_CLREN(n) (*((CPU_REG32 *)(0xE000E180 + (n) * 4u))) /* IRQ Clr En Reg. */
414 #define CPU_REG_NVIC_SETPEND(n) (*((CPU_REG32 *)(0xE000E200 + (n) * 4u))) /* IRQ Set Pending Reg. */
415 #define CPU_REG_NVIC_CLRPEND(n) (*((CPU_REG32 *)(0xE000E280 + (n) * 4u))) /* IRQ Clr Pending Reg. */
416 #define CPU_REG_NVIC_ACTIVE(n) (*((CPU_REG32 *)(0xE000E300 + (n) * 4u))) /* IRQ Active Reg. */
417 #define CPU_REG_NVIC_PRIO(n) (*((CPU_REG32 *)(0xE000E400 + (n) * 4u))) /* IRQ Prio Reg. */
418
419 #define CPU_REG_NVIC_CPUID (*((CPU_REG32 *)(0xE000ED00))) /* CPUID Base Reg. */
420 #define CPU_REG_NVIC_ICSR (*((CPU_REG32 *)(0xE000ED04))) /* Int Ctrl State Reg. */
421 #define CPU_REG_NVIC_VTOR (*((CPU_REG32 *)(0xE000ED08))) /* Vect Tbl Offset Reg. */
422 #define CPU_REG_NVIC_AIRCR (*((CPU_REG32 *)(0xE000ED0C))) /* App Int/Reset Ctrl Reg. */
423 #define CPU_REG_NVIC_SCR (*((CPU_REG32 *)(0xE000ED10))) /* System Ctrl Reg. */
424 #define CPU_REG_NVIC_CCR (*((CPU_REG32 *)(0xE000ED14))) /* Cfg Ctrl Reg. */
425 #define CPU_REG_NVIC_SHPRI1 (*((CPU_REG32 *)(0xE000ED18))) /* System Handlers 4 to 7 Prio. */
426 #define CPU_REG_NVIC_SHPRI2 (*((CPU_REG32 *)(0xE000ED1C))) /* System Handlers 8 to 11 Prio. */
427 #define CPU_REG_NVIC_SHPRI3 (*((CPU_REG32 *)(0xE000ED20))) /* System Handlers 12 to 15 Prio. */
428 #define CPU_REG_NVIC_SHCSR (*((CPU_REG32 *)(0xE000ED24))) /* System Handler Ctrl & State Reg. */
429 #define CPU_REG_NVIC_CFSR (*((CPU_REG32 *)(0xE000ED28))) /* Configurable Fault Status Reg. */
430 #define CPU_REG_NVIC_HFSR (*((CPU_REG32 *)(0xE000ED2C))) /* Hard Fault Status Reg. */
431 #define CPU_REG_NVIC_DFSR (*((CPU_REG32 *)(0xE000ED30))) /* Debug Fault Status Reg. */
432 #define CPU_REG_NVIC_MMFAR (*((CPU_REG32 *)(0xE000ED34))) /* Mem Manage Addr Reg. */
433 #define CPU_REG_NVIC_BFAR (*((CPU_REG32 *)(0xE000ED38))) /* Bus Fault Addr Reg. */
434 #define CPU_REG_NVIC_AFSR (*((CPU_REG32 *)(0xE000ED3C))) /* Aux Fault Status Reg. */
435
436 #define CPU_REG_NVIC_PFR0 (*((CPU_REG32 *)(0xE000ED40))) /* Processor Feature Reg 0. */
437 #define CPU_REG_NVIC_PFR1 (*((CPU_REG32 *)(0xE000ED44))) /* Processor Feature Reg 1. */
438 #define CPU_REG_NVIC_DFR0 (*((CPU_REG32 *)(0xE000ED48))) /* Debug Feature Reg 0. */
439 #define CPU_REG_NVIC_AFR0 (*((CPU_REG32 *)(0xE000ED4C))) /* Aux Feature Reg 0. */
440 #define CPU_REG_NVIC_MMFR0 (*((CPU_REG32 *)(0xE000ED50))) /* Memory Model Feature Reg 0. */
441 #define CPU_REG_NVIC_MMFR1 (*((CPU_REG32 *)(0xE000ED54))) /* Memory Model Feature Reg 1. */
442 #define CPU_REG_NVIC_MMFR2 (*((CPU_REG32 *)(0xE000ED58))) /* Memory Model Feature Reg 2. */
443 #define CPU_REG_NVIC_MMFR3 (*((CPU_REG32 *)(0xE000ED5C))) /* Memory Model Feature Reg 3. */
444 #define CPU_REG_NVIC_ISAFR0 (*((CPU_REG32 *)(0xE000ED60))) /* ISA Feature Reg 0. */
445 #define CPU_REG_NVIC_ISAFR1 (*((CPU_REG32 *)(0xE000ED64))) /* ISA Feature Reg 1. */
446 #define CPU_REG_NVIC_ISAFR2 (*((CPU_REG32 *)(0xE000ED68))) /* ISA Feature Reg 2. */
447 #define CPU_REG_NVIC_ISAFR3 (*((CPU_REG32 *)(0xE000ED6C))) /* ISA Feature Reg 3. */
448 #define CPU_REG_NVIC_ISAFR4 (*((CPU_REG32 *)(0xE000ED70))) /* ISA Feature Reg 4. */
449 #define CPU_REG_NVIC_SW_TRIG (*((CPU_REG32 *)(0xE000EF00))) /* Software Trigger Int Reg. */
450
451 #define CPU_REG_MPU_TYPE (*((CPU_REG32 *)(0xE000ED90))) /* MPU Type Reg. */
452 #define CPU_REG_MPU_CTRL (*((CPU_REG32 *)(0xE000ED94))) /* MPU Ctrl Reg. */
453 #define CPU_REG_MPU_REG_NBR (*((CPU_REG32 *)(0xE000ED98))) /* MPU Region Nbr Reg. */
454 #define CPU_REG_MPU_REG_BASE (*((CPU_REG32 *)(0xE000ED9C))) /* MPU Region Base Addr Reg. */
455 #define CPU_REG_MPU_REG_ATTR (*((CPU_REG32 *)(0xE000EDA0))) /* MPU Region Attrib & Size Reg. */
456
457 #define CPU_REG_DBG_CTRL (*((CPU_REG32 *)(0xE000EDF0))) /* Debug Halting Ctrl & Status Reg. */
458 #define CPU_REG_DBG_SELECT (*((CPU_REG32 *)(0xE000EDF4))) /* Debug Core Reg Selector Reg. */
459 #define CPU_REG_DBG_DATA (*((CPU_REG32 *)(0xE000EDF8))) /* Debug Core Reg Data Reg. */
460 #define CPU_REG_DBG_INT (*((CPU_REG32 *)(0xE000EDFC))) /* Debug Except & Monitor Ctrl Reg. */
461
462
463 /*$PAGE*/
464 /*
465 *********************************************************************************************************
466 * CPU REGISTER BITS
467 *********************************************************************************************************
468 */
469
470 /* ---------- SYSTICK CTRL & STATUS REG BITS ---------- */
471 #define CPU_REG_NVIC_ST_CTRL_COUNTFLAG 0x00010000
472 #define CPU_REG_NVIC_ST_CTRL_CLKSOURCE 0x00000004
473 #define CPU_REG_NVIC_ST_CTRL_TICKINT 0x00000002
474 #define CPU_REG_NVIC_ST_CTRL_ENABLE 0x00000001
475
476
477 /* -------- SYSTICK CALIBRATION VALUE REG BITS -------- */
478 #define CPU_REG_NVIC_ST_CAL_NOREF 0x80000000
479 #define CPU_REG_NVIC_ST_CAL_SKEW 0x40000000
480
481 /* -------------- INT CTRL STATE REG BITS ------------- */
482 #define CPU_REG_NVIC_ICSR_NMIPENDSET 0x80000000
483 #define CPU_REG_NVIC_ICSR_PENDSVSET 0x10000000
484 #define CPU_REG_NVIC_ICSR_PENDSVCLR 0x08000000
485 #define CPU_REG_NVIC_ICSR_PENDSTSET 0x04000000
486 #define CPU_REG_NVIC_ICSR_PENDSTCLR 0x02000000
487 #define CPU_REG_NVIC_ICSR_ISRPREEMPT 0x00800000
488 #define CPU_REG_NVIC_ICSR_ISRPENDING 0x00400000
489 #define CPU_REG_NVIC_ICSR_RETTOBASE 0x00000800
490
491 /* ------------- VECT TBL OFFSET REG BITS ------------- */
492 #define CPU_REG_NVIC_VTOR_TBLBASE 0x20000000
493
494 /* ------------ APP INT/RESET CTRL REG BITS ----------- */
495 #define CPU_REG_NVIC_AIRCR_ENDIANNESS 0x00008000
496 #define CPU_REG_NVIC_AIRCR_SYSRESETREQ 0x00000004
497 #define CPU_REG_NVIC_AIRCR_VECTCLRACTIVE 0x00000002
498 #define CPU_REG_NVIC_AIRCR_VECTRESET 0x00000001
499
500 /* --------------- SYSTEM CTRL REG BITS --------------- */
501 #define CPU_REG_NVIC_SCR_SEVONPEND 0x00000010
502 #define CPU_REG_NVIC_SCR_SLEEPDEEP 0x00000004
503 #define CPU_REG_NVIC_SCR_SLEEPONEXIT 0x00000002
504
505 /* ----------------- CFG CTRL REG BITS ---------------- */
506 #define CPU_REG_NVIC_CCR_STKALIGN 0x00000200
507 #define CPU_REG_NVIC_CCR_BFHFNMIGN 0x00000100
508 #define CPU_REG_NVIC_CCR_DIV_0_TRP 0x00000010
509 #define CPU_REG_NVIC_CCR_UNALIGN_TRP 0x00000008
510 #define CPU_REG_NVIC_CCR_USERSETMPEND 0x00000002
511 #define CPU_REG_NVIC_CCR_NONBASETHRDENA 0x00000001
512
513 /* ------- SYSTEM HANDLER CTRL & STATE REG BITS ------- */
514 #define CPU_REG_NVIC_SHCSR_USGFAULTENA 0x00040000
515 #define CPU_REG_NVIC_SHCSR_BUSFAULTENA 0x00020000
516 #define CPU_REG_NVIC_SHCSR_MEMFAULTENA 0x00010000
517 #define CPU_REG_NVIC_SHCSR_SVCALLPENDED 0x00008000
518 #define CPU_REG_NVIC_SHCSR_BUSFAULTPENDED 0x00004000
519 #define CPU_REG_NVIC_SHCSR_MEMFAULTPENDED 0x00002000
520 #define CPU_REG_NVIC_SHCSR_USGFAULTPENDED 0x00001000
521 #define CPU_REG_NVIC_SHCSR_SYSTICKACT 0x00000800
522 #define CPU_REG_NVIC_SHCSR_PENDSVACT 0x00000400
523 #define CPU_REG_NVIC_SHCSR_MONITORACT 0x00000100
524 #define CPU_REG_NVIC_SHCSR_SVCALLACT 0x00000080
525 #define CPU_REG_NVIC_SHCSR_USGFAULTACT 0x00000008
526 #define CPU_REG_NVIC_SHCSR_BUSFAULTACT 0x00000002
527 #define CPU_REG_NVIC_SHCSR_MEMFAULTACT 0x00000001
528
529 /* -------- CONFIGURABLE FAULT STATUS REG BITS -------- */
530 #define CPU_REG_NVIC_CFSR_DIVBYZERO 0x02000000
531 #define CPU_REG_NVIC_CFSR_UNALIGNED 0x01000000
532 #define CPU_REG_NVIC_CFSR_NOCP 0x00080000
533 #define CPU_REG_NVIC_CFSR_INVPC 0x00040000
534 #define CPU_REG_NVIC_CFSR_INVSTATE 0x00020000
535 #define CPU_REG_NVIC_CFSR_UNDEFINSTR 0x00010000
536 #define CPU_REG_NVIC_CFSR_BFARVALID 0x00008000
537 #define CPU_REG_NVIC_CFSR_STKERR 0x00001000
538 #define CPU_REG_NVIC_CFSR_UNSTKERR 0x00000800
539 #define CPU_REG_NVIC_CFSR_IMPRECISERR 0x00000400
540 #define CPU_REG_NVIC_CFSR_PRECISERR 0x00000200
541 #define CPU_REG_NVIC_CFSR_IBUSERR 0x00000100
542 #define CPU_REG_NVIC_CFSR_MMARVALID 0x00000080
543 #define CPU_REG_NVIC_CFSR_MSTKERR 0x00000010
544 #define CPU_REG_NVIC_CFSR_MUNSTKERR 0x00000008
545 #define CPU_REG_NVIC_CFSR_DACCVIOL 0x00000002
546 #define CPU_REG_NVIC_CFSR_IACCVIOL 0x00000001
547
548 /* ------------ HARD FAULT STATUS REG BITS ------------ */
549 #define CPU_REG_NVIC_HFSR_DEBUGEVT 0x80000000
550 #define CPU_REG_NVIC_HFSR_FORCED 0x40000000
551 #define CPU_REG_NVIC_HFSR_VECTTBL 0x00000002
552
553 /* ------------ DEBUG FAULT STATUS REG BITS ----------- */
554 #define CPU_REG_NVIC_DFSR_EXTERNAL 0x00000010
555 #define CPU_REG_NVIC_DFSR_VCATCH 0x00000008
556 #define CPU_REG_NVIC_DFSR_DWTTRAP 0x00000004
557 #define CPU_REG_NVIC_DFSR_BKPT 0x00000002
558 #define CPU_REG_NVIC_DFSR_HALTED 0x00000001
559
560
561 /*
562 *********************************************************************************************************
563 * CPU REGISTER MASK
564 *********************************************************************************************************
565 */
566
567 #define CPU_MSK_NVIC_ICSR_VECT_ACTIVE 0x000001FF
568
569
570 /*$PAGE*/
571 /*
572 *********************************************************************************************************
573 * CONFIGURATION ERRORS
574 *********************************************************************************************************
575 */
576
577 #ifndef CPU_CFG_ADDR_SIZE
578 #error "CPU_CFG_ADDR_SIZE not #define'd in 'cpu.h' "
579 #error " [MUST be CPU_WORD_SIZE_08 8-bit alignment]"
580 #error " [ || CPU_WORD_SIZE_16 16-bit alignment]"
581 #error " [ || CPU_WORD_SIZE_32 32-bit alignment]"
582
583 #elif ((CPU_CFG_ADDR_SIZE != CPU_WORD_SIZE_08) && \
584 (CPU_CFG_ADDR_SIZE != CPU_WORD_SIZE_16) && \
585 (CPU_CFG_ADDR_SIZE != CPU_WORD_SIZE_32))
586 #error "CPU_CFG_ADDR_SIZE illegally #define'd in 'cpu.h' "
587 #error " [MUST be CPU_WORD_SIZE_08 8-bit alignment]"
588 #error " [ || CPU_WORD_SIZE_16 16-bit alignment]"
589 #error " [ || CPU_WORD_SIZE_32 32-bit alignment]"
590 #endif
591
592
593 #ifndef CPU_CFG_DATA_SIZE
594 #error "CPU_CFG_DATA_SIZE not #define'd in 'cpu.h' "
595 #error " [MUST be CPU_WORD_SIZE_08 8-bit alignment]"
596 #error " [ || CPU_WORD_SIZE_16 16-bit alignment]"
597 #error " [ || CPU_WORD_SIZE_32 32-bit alignment]"
598
599 #elif ((CPU_CFG_DATA_SIZE != CPU_WORD_SIZE_08) && \
600 (CPU_CFG_DATA_SIZE != CPU_WORD_SIZE_16) && \
601 (CPU_CFG_DATA_SIZE != CPU_WORD_SIZE_32))
602 #error "CPU_CFG_DATA_SIZE illegally #define'd in 'cpu.h' "
603 #error " [MUST be CPU_WORD_SIZE_08 8-bit alignment]"
604 #error " [ || CPU_WORD_SIZE_16 16-bit alignment]"
605 #error " [ || CPU_WORD_SIZE_32 32-bit alignment]"
606 #endif
607
608
609
610
611 #ifndef CPU_CFG_ENDIAN_TYPE
612 #error "CPU_CFG_ENDIAN_TYPE not #define'd in 'cpu.h' "
613 #error " [MUST be CPU_ENDIAN_TYPE_BIG ]"
614 #error " [ || CPU_ENDIAN_TYPE_LITTLE]"
615
616 #elif ((CPU_CFG_ENDIAN_TYPE != CPU_ENDIAN_TYPE_BIG ) && \
617 (CPU_CFG_ENDIAN_TYPE != CPU_ENDIAN_TYPE_LITTLE))
618 #error "CPU_CFG_ENDIAN_TYPE illegally #define'd in 'cpu.h' "
619 #error " [MUST be CPU_ENDIAN_TYPE_BIG ]"
620 #error " [ || CPU_ENDIAN_TYPE_LITTLE]"
621 #endif
622
623
624
625
626 #ifndef CPU_CFG_STK_GROWTH
627 #error "CPU_CFG_STK_GROWTH not #define'd in 'cpu.h' "
628 #error " [MUST be CPU_STK_GROWTH_LO_TO_HI]"
629 #error " [ || CPU_STK_GROWTH_HI_TO_LO]"
630
631 #elif ((CPU_CFG_STK_GROWTH != CPU_STK_GROWTH_LO_TO_HI) && \
632 (CPU_CFG_STK_GROWTH != CPU_STK_GROWTH_HI_TO_LO))
633 #error "CPU_CFG_STK_GROWTH illegally #define'd in 'cpu.h' "
634 #error " [MUST be CPU_STK_GROWTH_LO_TO_HI]"
635 #error " [ || CPU_STK_GROWTH_HI_TO_LO]"
636 #endif
637
638
639
640
641 #ifndef CPU_CFG_CRITICAL_METHOD
642 #error "CPU_CFG_CRITICAL_METHOD not #define'd in 'cpu.h' "
643 #error " [MUST be CPU_CRITICAL_METHOD_INT_DIS_EN ]"
644 #error " [ || CPU_CRITICAL_METHOD_STATUS_STK ]"
645 #error " [ || CPU_CRITICAL_METHOD_STATUS_LOCAL]"
646
647 #elif ((CPU_CFG_CRITICAL_METHOD != CPU_CRITICAL_METHOD_INT_DIS_EN ) && \
648 (CPU_CFG_CRITICAL_METHOD != CPU_CRITICAL_METHOD_STATUS_STK ) && \
649 (CPU_CFG_CRITICAL_METHOD != CPU_CRITICAL_METHOD_STATUS_LOCAL))
650 #error "CPU_CFG_CRITICAL_METHOD illegally #define'd in 'cpu.h' "
651 #error " [MUST be CPU_CRITICAL_METHOD_INT_DIS_EN ]"
652 #error " [ || CPU_CRITICAL_METHOD_STATUS_STK ]"
653 #error " [ || CPU_CRITICAL_METHOD_STATUS_LOCAL]"
654 #endif
655
656
657 /*$PAGE*/
658 /*
659 *********************************************************************************************************
660 * MODULE END
661 *********************************************************************************************************
662 */
663
664 #endif /* End of CPU module include. */
665