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spi_002.h
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1 /*
2 * @brief SPI registers and control functions
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __SPI_002_H_
33 #define __SPI_002_H_
34
35 #include "sys_config.h"
36 #include "cmsis.h"
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
50 typedef struct {
51 __IO uint32_t CFG;
52 __IO uint32_t DLY;
53 __IO uint32_t STAT;
54 __IO uint32_t INTENSET;
55 __O uint32_t INTENCLR;
56 __I uint32_t RXDAT;
57 __IO uint32_t TXDATCTL;
58 __IO uint32_t TXDAT;
59 __IO uint32_t TXCTRL;
60 __IO uint32_t DIV;
61 __I uint32_t INTSTAT;
62 } IP_SPI_002_T;
63
67 /* SPI CFG Register BitMask */
68 #define SPI_CFG_BITMASK ((uint32_t) 0x1BD)
69
70 #define SPI_CFG_SPI_EN ((uint32_t) (1 << 0))
71
72 #define SPI_CFG_SLAVE_EN ((uint32_t) 0)
73
74 #define SPI_CFG_MASTER_EN ((uint32_t) (1 << 2))
75
76 #define SPI_CFG_MSB_FIRST_EN ((uint32_t) 0) /*Data will be transmitted and received in standard order (MSB first).*/
77
78 #define SPI_CFG_LSB_FIRST_EN ((uint32_t) (1 << 3))/*Data will be transmitted and received in reverse order (LSB first).*/
79
80 #define SPI_CFG_CPHA_FIRST ((uint32_t) (0)) /*Capture data on the first edge, Change data on the following edge*/
81 #define SPI_CFG_CPHA_SECOND ((uint32_t) (1 << 4)) /*Change data on the first edge, Capture data on the following edge*/
82
83 #define SPI_CFG_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/
84 #define SPI_CFG_CPOL_HI ((uint32_t) (1 << 5)) /* The rest state of the clock (between frames) is high.*/
85
86 #define SPI_CFG_LBM_EN ((uint32_t) (1 << 7))
87
88 #define SPI_CFG_SPOL_LO ((uint32_t) (0)) /* SSEL is active Low */
89 #define SPI_CFG_SPOL_HI ((uint32_t) (1 << 8)) /* SSEL is active High */
90
95 #define SPI_DLY_BITMASK ((uint32_t) 0xFFFF)
96
97 #define SPI_DLY_PRE_DELAY(n) ((uint32_t) ((n) & 0x0F)) /* Time Unit: SPI clock time */
98
99 #define SPI_DLY_POST_DELAY(n) ((uint32_t) (((n) & 0x0F) << 4)) /* Time Unit: SPI clock time */
100
101 #define SPI_DLY_FRAME_DELAY(n) ((uint32_t) (((n) & 0x0F) << 8)) /* Time Unit: SPI clock time */
102
103 #define SPI_DLY_TRANSFER_DELAY(n) ((uint32_t) (((n) & 0x0F) << 12)) /* Time Unit: SPI clock time */
104
108 /* SPI STAT Register BitMask */
109 #define SPI_STAT_BITMASK ((uint32_t) 0x1FF)
110 /* Receiver Ready Flag */
111 #define SPI_STAT_RXRDY ((uint32_t) (1 << 0)) /* Data is ready for read */
112 /* Transmitter Ready Flag */
113 #define SPI_STAT_TXRDY ((uint32_t) (1 << 1)) /* Data may be written to transmit buffer */
114 /* Receiver Overrun interrupt flag */
115 #define SPI_STAT_RXOV ((uint32_t) (1 << 2)) /* Data comes while receiver buffer is in used */
116 /* Transmitter Underrun interrupt flag (In Slave Mode only) */
117 #define SPI_STAT_TXUR ((uint32_t) (1 << 3)) /* There is no data to be sent in the next input clock */
118 /* Slave Select Assert */
119 #define SPI_STAT_SSA ((uint32_t) (1 << 4)) /* There is SSEL transition from deasserted to asserted */
120 /* Slave Select Deassert */
121 #define SPI_STAT_SSD ((uint32_t) (1 << 5)) /* There is SSEL transition from asserted to deasserted */
122 /* Stalled status flag */
123 #define SPI_STAT_STALLED ((uint32_t) (1 << 6)) /* SPI is currently in a stall condition. */
124 /* End Transfer flag. */
125 #define SPI_STAT_EOT ((uint32_t) (1 << 7)) /* The current frame is the last frame of the current transfer. */
126 /* Idle status flag. */
127 #define SPI_STAT_LE ((uint32_t) (1 << 8)) /* SPI master function is fully idle. */
128
129 /* Clear RXOV Flag */
130 #define SPI_STAT_CLR_RXOV ((uint32_t) (1 << 2))
131 /* Clear TXUR Flag */
132 #define SPI_STAT_CLR_TXUR ((uint32_t) (1 << 3))
133 /* Clear SSA Flag */
134 #define SPI_STAT_CLR_SSA ((uint32_t) (1 << 4))
135 /* Clear SSD Flag */
136 #define SPI_STAT_CLR_SSD ((uint32_t) (1 << 5))
137 /*Force an end to the current transfer */
138 #define SPI_STAT_FORCE_EOT ((uint32_t) (1 << 7))
139
143 /* SPI INTENSET Register BitMask */
144 #define SPI_INTENSET_BITMASK ((uint32_t) 0x3F)
145
146 #define SPI_INTENSET_RXDYEN ((uint32_t) (1 << 0))
147
148 #define SPI_INTENSET_TXDYEN ((uint32_t) (1 << 1))
149
150 #define SPI_INTENSET_RXOVEN ((uint32_t) (1 << 2))
151
152 #define SPI_INTENSET_TXUREN ((uint32_t) (1 << 3))
153
154 #define SPI_INTENSET_SSAEN ((uint32_t) (1 << 2))
155
156 #define SPI_INTENSET_SSDEN ((uint32_t) (1 << 2))
157
161 /* SPI INTENCLR Register BitMask */
162 #define SPI_INTENCLR_BITMASK ((uint32_t) 0x3F)
163
164 #define SPI_INTENCLR_RXDYEN ((uint32_t) (1 << 0))
165
166 #define SPI_INTENCLR_TXDYEN ((uint32_t) (1 << 1))
167
168 #define SPI_INTENCLR_RXOVEN ((uint32_t) (1 << 2))
169
170 #define SPI_INTENCLR_TXUREN ((uint32_t) (1 << 3))
171
172 #define SPI_INTENCLR_SSAEN ((uint32_t) (1 << 2))
173
174 #define SPI_INTENCLR_SSDEN ((uint32_t) (1 << 2))
175
179 /* SPI RXDAT Register BitMask */
180 #define SPI_RXDAT_BITMASK ((uint32_t) 0x11FFFF)
181
182 #define SPI_RXDAT_DATA(n) ((uint32_t) ((n) & 0xFFFF))
183
184 #define SPI_RXDAT_RXSSELN_ACTIVE ((uint32_t) 0) /* SSEL is in active state */
185 #define SPI_RXDAT_RXSSELN_INACTIVE ((uint32_t) (1 << 16)) /* SSEL is in inactive state */
186
187 #define SPI_RXDAT_SOT ((uint32_t) (1 << 20)) /* This is the first frame received after SSEL is asserted */
188
192 /* SPI TXDATCTL Register BitMask */
193 #define SPI_TXDATCTL_BITMASK ((uint32_t) 0xF71FFFF)
194 /* SPI Transmit Data */
195 #define SPI_TXDATCTL_DATA(n) ((uint32_t) ((n) & 0xFFFF))
196 /*Assert/Deassert SSL pin*/
197 #define SPI_TXDATCTL_ASSERT_SSEL ((uint32_t) 0)
198 #define SPI_TXDATCTL_DEASSERT_SSEL ((uint32_t) (1 << 16))
199
200 #define SPI_TXDATCTL_EOT ((uint32_t) (1 << 20)) /* This is the last frame of the current transfer */
201
202 #define SPI_TXDATCTL_EOF ((uint32_t) (1 << 21)) /* This is the last part of the current frame */
203
204 #define SPI_TXDATCTL_RXIGNORE ((uint32_t) (1 << 22)) /* Received data is ignored */
205
206 #define SPI_TXDATCTL_FLEN(n) ((uint32_t) (((n) & 0x0F) << 24)) /* Frame Length -1 */
207
211 /* SPI Transmit Data */
212 #define SPI_TXDAT_DATA(n) ((uint32_t) ((n) & 0xFFFF))
213
217 /* SPI TXDATCTL Register BitMask */
218 #define SPI_TXCTL_BITMASK ((uint32_t) 0xF71FF00)
219 /*Assert/Deassert SSL pin*/
220 #define SPI_TXCTL_ASSERT_SSEL ((uint32_t) 0)
221 #define SPI_TXCTL_DEASSERT_SSEL ((uint32_t) (1 << 16))
222
223 #define SPI_TXCTL_EOT ((uint32_t) (1 << 20)) /* This is the last frame of the current transfer */
224
225 #define SPI_TXCTL_EOF ((uint32_t) (1 << 21)) /* This is the last part of the current frame */
226
227 #define SPI_TXCTL_RXIGNORE ((uint32_t) (1 << 22)) /* Received data is ignored */
228
229 #define SPI_TXCTL_FLEN(n) ((uint32_t) (((n) & 0x0F) << 24)) /* Frame Length -1 */
230
235 #define SPI_DIV_VAL(n) ((uint32_t) ((n) & 0xFFFF)) /* SPI_CLK = PCLK/(DIV_VAL+1)*/
236
240 /* SPI INTSTAT Register Bitmask */
241 #define SPI_INTSTAT_BITMASK ((uint32_t) 0x3F)
242 /* Receiver Ready Flag */
243 #define SPI_INTSTAT_RXRDY ((uint32_t) (1 << 0)) /* Data is ready for read */
244 /* Transmitter Ready Flag */
245 #define SPI_INTSTAT_TXRDY ((uint32_t) (1 << 1)) /* Data may be written to transmit buffer */
246 /* Receiver Overrun interrupt flag */
247 #define SPI_INTSTAT_RXOV ((uint32_t) (1 << 2)) /* Data comes while receiver buffer is in used */
248 /* Transmitter Underrun interrupt flag (In Slave Mode only) */
249 #define SPI_INTSTAT_TXUR ((uint32_t) (1 << 3)) /* There is no data to be sent in the next input clock */
250 /* Slave Select Assert */
251 #define SPI_INTSTAT_SSA ((uint32_t) (1 << 4)) /* There is SSEL transition from deasserted to asserted */
252 /* Slave Select Deassert */
253 #define SPI_INTSTAT_SSD ((uint32_t) (1 << 5)) /* There is SSEL transition from asserted to deasserted */
254
256 typedef enum IP_SPI_MODE {
257 SPI_MODE_MASTER = SPI_CFG_MASTER_EN, /* Master Mode */
258 SPI_MODE_SLAVE = SPI_CFG_SLAVE_EN, /* Slave Mode */
259 } IP_SPI_MODE_T;
260
262 typedef enum IP_SPI_CLOCK_MODE {
263 SPI_CLOCK_CPHA0_CPOL0 = SPI_CFG_CPOL_LO | SPI_CFG_CPHA_FIRST,
264 SPI_CLOCK_CPHA0_CPOL1 = SPI_CFG_CPOL_HI | SPI_CFG_CPHA_FIRST,
265 SPI_CLOCK_CPHA1_CPOL0 = SPI_CFG_CPOL_LO | SPI_CFG_CPHA_SECOND,
266 SPI_CLOCK_CPHA1_CPOL1 = SPI_CFG_CPOL_HI | SPI_CFG_CPHA_SECOND,
267 SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0,
268 SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0,
269 SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1,
270 SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1,
271 } IP_SPI_CLOCK_MODE_T;
272
274 typedef enum IP_SPI_DATA_ORDER {
275 SPI_DATA_MSB_FIRST = SPI_CFG_MSB_FIRST_EN, /* Standard Order */
276 SPI_DATA_LSB_FIRST = SPI_CFG_LSB_FIRST_EN, /* Reverse Order */
277 } IP_SPI_DATA_ORDER_T;
278
280 typedef enum IP_SPI_SSEL_POL {
281 SPI_SSEL_ACTIVE_LO = SPI_CFG_SPOL_LO, /* SSEL is active Low*/
282 SPI_SSEL_ACTIVE_HI = SPI_CFG_SPOL_HI, /* SSEL is active High */
283 } IP_SPI_SSEL_POL_T;
284
288 typedef struct {
289 IP_SPI_MODE_T Mode; /* Mode Select */
290 IP_SPI_CLOCK_MODE_T ClockMode; /* CPHA CPOL Select */
291 IP_SPI_DATA_ORDER_T DataOrder; /* MSB/LSB First */
292 IP_SPI_SSEL_POL_T SSELPol; /* SSEL Polarity Select */
293 uint16_t ClkDiv; /* SPI Clock Divider Value */
294 } IP_SPI_CONFIG_T;
295
299 typedef struct {
300 uint8_t PreDelay; /* Pre-delay value in SPI clock time */
301 uint8_t PostDelay; /* Post-delay value in SPI clock time */
302 uint8_t FrameDelay; /* Delay value between frames of a transfer in SPI clock time */
303 uint8_t TransferDelay; /* Delay value between transfers in SPI clock time */
304 } IP_SPI_DELAY_CONFIG_T;
305
311 STATIC INLINE void IP_SPI_Enable(IP_SPI_002_T *pSPI)
312 {
313 pSPI->CFG |= SPI_CFG_SPI_EN;
314 }
315
321 STATIC INLINE void IP_SPI_Disable(IP_SPI_002_T *pSPI)
322 {
323 pSPI->CFG &= (~SPI_CFG_SPI_EN) & SPI_CFG_BITMASK;
324 }
325
332 STATIC INLINE void IP_SPI_DeInit(IP_SPI_002_T *pSPI)
333 {
334 IP_SPI_Disable(pSPI);
335 }
336
344 STATIC INLINE void IP_SPI_EnableLoopBack(IP_SPI_002_T *pSPI)
345 {
346 pSPI->CFG |= SPI_CFG_LBM_EN;
347 }
348
356 STATIC INLINE void IP_SPI_DisableLoopBack(IP_SPI_002_T *pSPI)
357 {
358 pSPI->CFG &= (~SPI_CFG_LBM_EN) & SPI_CFG_BITMASK;
359 }
360
366 STATIC INLINE uint32_t IP_SPI_GetStatus(IP_SPI_002_T *pSPI)
367 {
368 return pSPI->STAT;
369 }
370
376 STATIC INLINE void IP_SPI_ForceEOT(IP_SPI_002_T *pSPI)
377 {
378 pSPI->STAT |= SPI_STAT_FORCE_EOT;
379 }
380
387 STATIC INLINE void IP_SPI_ClearStatus(IP_SPI_002_T *pSPI, uint32_t Flag)
388 {
389 pSPI->STAT |= Flag;
390 }
391
398 STATIC INLINE void IP_SPI_IntEnable(IP_SPI_002_T *pSPI, uint32_t IntEnMsk)
399 {
400 pSPI->INTENSET |= IntEnMsk;
401 }
402
409 STATIC INLINE void IP_SPI_IntDisable(IP_SPI_002_T *pSPI, uint32_t IntDisMsk)
410 {
411 pSPI->INTENCLR |= IntDisMsk;
412 }
413
420 STATIC INLINE uint32_t IP_SPI_GetIntStatus(IP_SPI_002_T *pSPI)
421 {
422 return pSPI->INTSTAT;
423 }
424
432 STATIC INLINE void IP_SPI_SendFrame(IP_SPI_002_T *pSPI, uint16_t data)
433 {
434 pSPI->TXDAT = SPI_TXDAT_DATA(data);
435 }
436
445 STATIC INLINE void IP_SPI_SetControlInfo(IP_SPI_002_T *pSPI, uint8_t Flen, uint32_t Flag)
446 {
447 pSPI->TXCTRL = Flag | SPI_TXDATCTL_FLEN(Flen - 1);
448 }
449
458 STATIC INLINE void IP_SPI_SendFrameAndControl(IP_SPI_002_T *pSPI, uint16_t TxData, uint8_t Flen, uint32_t Flag)
459 {
460 pSPI->TXDATCTL = Flag | SPI_TXDATCTL_FLEN(Flen - 1) | SPI_TXDATCTL_DATA(TxData);
461 }
462
468 STATIC INLINE uint16_t IP_SPI_ReceiveFrame(IP_SPI_002_T *pSPI)
469 {
470 return SPI_RXDAT_DATA(pSPI->RXDAT);
471 }
472
480 void IP_SPI_Init(IP_SPI_002_T *pSPI, IP_SPI_CONFIG_T *pConfig);
481
489 void IP_SPI_DelayConfig(IP_SPI_002_T *pSPI, IP_SPI_DELAY_CONFIG_T *pConfig);
490
495 #ifdef __cplusplus
496 }
497 #endif
498
499 #endif /* __SPI_002_H_ */