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sysinit_ea_devkit_17884088.c
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1 /*
2 * Copyright(C) NXP Semiconductors, 2012
3 * All rights reserved.
4 *
5 * Software that is described herein is for illustrative purposes only
6 * which provides customers with programming information regarding the
7 * LPC products. This software is supplied "AS IS" without any warranties of
8 * any kind, and NXP Semiconductors and its licensor disclaim any and
9 * all warranties, express or implied, including all implied warranties of
10 * merchantability, fitness for a particular purpose and non-infringement of
11 * intellectual property rights. NXP Semiconductors assumes no responsibility
12 * or liability for the use of the software, conveys no license or rights under any
13 * patent, copyright, mask work right, or any other intellectual property rights in
14 * or to any products. NXP Semiconductors reserves the right to make changes
15 * in the software without notification. NXP Semiconductors also makes no
16 * representation or warranty that such application will be suitable for the
17 * specified use without further testing or modification.
18 *
19 * Permission to use, copy, modify, and distribute this software and its
20 * documentation is hereby granted, under NXP Semiconductors' and its
21 * licensor's relevant copyrights in the software, without fee, provided that it
22 * is used in conjunction with NXP Semiconductors microcontrollers. This
23 * copyright, permission, and disclaimer notice must appear in all copies of
24 * this code.
25 */
26
27 #include "board.h"
28
52 /*****************************************************************************
53 * Private types/enumerations/variables
54 ****************************************************************************/
55
56 /* SCR pin definitions for pin muxing */
57 typedef struct {
58 uint8_t pingrp; /* Pin group */
59 uint8_t pinnum; /* Pin number */
60 uint32_t modefunc; /* Pin mode and function */
61 } PINMUX_GRP_T;
62
63 /* Pin muxing configuration */
64 STATIC const PINMUX_GRP_T pinmuxing[] = {
65 /* CAN RD1 and TD1 */
66 {0x0, 0, (IOCON_FUNC1 | IOCON_MODE_INACT)},
67 {0x0, 1, (IOCON_FUNC1 | IOCON_MODE_INACT)},
68 /* UART 0 debug port (via USB bridge) */
69 {0x0, 2, (IOCON_FUNC1 | IOCON_MODE_INACT)},
70 {0x0, 3, (IOCON_FUNC1 | IOCON_MODE_INACT)},
71 /* I2S */
72 {0x0, 4, (IOCON_FUNC1 | IOCON_MODE_INACT)}, /* I2S RX clock */
73 {0x0, 5, (IOCON_FUNC1 | IOCON_MODE_INACT)}, /* I2S RX WS */
74 {0x0, 6, (IOCON_FUNC1 | IOCON_MODE_INACT)}, /* I2S RX SDA */
75 {0x0, 7, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, /* I2S TX clock */
76 {0x0, 8, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, /* I2S TX WS */
77 {0x0, 9, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, /* I2S TX SDA */
78 /* SSP 0 */
79 {0x0, 15, (IOCON_FUNC1 | IOCON_MODE_INACT)}, /* SSP CLK */
80 {0x0, 16, (IOCON_FUNC1 | IOCON_MODE_INACT)},
81 {0x0, 17, (IOCON_FUNC1 | IOCON_MODE_INACT)},
82 {0x0, 18, (IOCON_FUNC1 | IOCON_MODE_INACT)},
83 /* ADC */
84 {0x0, 25, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_ADMODE_EN)},
85 /* DAC */
86 {0x0, 26, (IOCON_FUNC2 | IOCON_DAC_EN | IOCON_HYS_EN | IOCON_MODE_PULLUP)},
87 /* ENET */
88 {0x1, 0, (IOCON_FUNC1 | IOCON_MODE_INACT)},
89 {0x1, 1, (IOCON_FUNC1 | IOCON_MODE_INACT)},
90 {0x1, 4, (IOCON_FUNC1 | IOCON_MODE_INACT)},
91 {0x1, 8, (IOCON_FUNC1 | IOCON_MODE_INACT)},
92 {0x1, 9, (IOCON_FUNC1 | IOCON_MODE_INACT)},
93 {0x1, 10, (IOCON_FUNC1 | IOCON_MODE_INACT)},
94 #if defined(CHIP_LPC407X_8X)
95 {0x1, 14, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)},
96 #else
97 {0x1, 14, (IOCON_FUNC1 | IOCON_MODE_INACT)},
98 #endif
99 {0x1, 15, (IOCON_FUNC1 | IOCON_MODE_INACT)},
100 #if defined(CHIP_LPC407X_8X)
101 {0x1, 16, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)},
102 {0x1, 17, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)},
103 #else
104 {0x1, 16, (IOCON_FUNC1 | IOCON_MODE_INACT)},
105 {0x1, 17, (IOCON_FUNC1 | IOCON_MODE_INACT)},
106 #endif
107 /* FIXME NOT COMPLETE */
108
109 /* LEDs */
110 {0x2, 26, (IOCON_FUNC0 | IOCON_MODE_INACT)},
111 {0x2, 27, (IOCON_FUNC0 | IOCON_MODE_INACT)},
112 };
113
114 /*****************************************************************************
115 * Public types/enumerations/variables
116 ****************************************************************************/
117
118 /*****************************************************************************
119 * Private functions
120 ****************************************************************************/
121
122 /* Setup system clocking */
123 STATIC void SystemSetupClocking(void)
124 {
125 /* CPU clock source starts with IRC */
126 Chip_Clock_SetMainPllSource(SYSCTL_PLLCLKSRC_IRC);
127 Chip_Clock_SetCPUClockSource(SYSCTL_CCLKSRC_SYSCLK);
128
129 /* Enable PBOOST for CPU clock over 100MHz */
130 Chip_SYSCTL_EnableBoost();
131
132 /* Enable main oscillator used for PLLs */
133 LPC_SYSCTL->SCS = SYSCTL_OSCEC;
134 while ((LPC_SYSCTL->SCS & SYSCTL_OSCSTAT) == 0) {}
135
136 /* PLL0 clock source is 12MHz oscillator, PLL1 can only be the
137 main oscillator */
138 Chip_Clock_SetMainPllSource(SYSCTL_PLLCLKSRC_MAINOSC);
139
140 /* Setup PLL0 for a 120MHz clock
141 Input clock rate (FIN) is main oscillator = 12MHz
142 PLL output = 120MHz = FIN * MSEL = 120MHz, so MSEL = 10
143 FCCO must be between 156 MHz to 320 MHz, where FCCO = PLL output * 2 * P,
144 so P = 1 and FCCO = 120MHz * 2 * 1 = 240MHz */
145 Chip_Clock_SetupPLL(SYSCTL_MAIN_PLL, 9, 0); /* Multiply by 10, Divide by 1 */
146
147 /* Enable PLL0 */
148 Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
149
150 /* Setup USB PLL1 for a 240MHz clock
151 Input clock rate (FIN) is main oscillator = 12MHz
152 PLL output = 240MHz = FIN * MSEL = 120MHz, so MSEL = 20
153 FCCO must be between 156 MHz to 320 MHz, where FCCO = PLL output * 2 * P,
154 so P = 1 and FCCO = 240MHz * 2 * 1 = 240MHz */
155 Chip_Clock_SetupPLL(SYSCTL_USB_PLL, 19, 0); /* Multiply by 20, Divide by 1 */
156
157 /* Enable PLL0 */
158 Chip_Clock_EnablePLL(SYSCTL_USB_PLL, SYSCTL_PLL_ENABLE);
159
160 /* Since the USB PLL clock is 240MHz, we need to divide by 5 to get 48Mhz
161 as needed by the USB peripheral. Also set the USB divider source to
162 the USB PLL. USB clock rate = 240 / 5 = 48MHz */
163 Chip_Clock_SetUSBClockSource(SYSCTL_USBCLKSRC_USBPLL);
164 Chip_Clock_SetUSBClockDiv(5);
165
166 /* PLL1 is disabled until needed */
167 Chip_Clock_DisablePLL(SYSCTL_USB_PLL, SYSCTL_PLL_ENABLE);
168
169 /* Wait for main (CPU) PLL0 to lock */
170 while ((Chip_Clock_GetPLLStatus(SYSCTL_MAIN_PLL) & SYSCTL_PLLSTS_LOCKED) == 0) {}
171
172 /* The CPU is still sourced from the SYSCLK, so set the CPU divider to
173 1 and switch it to the PLL0 clock */
174 Chip_Clock_SetCPUClockDiv(1);
175 Chip_Clock_SetCPUClockSource(SYSCTL_CCLKSRC_MAINPLL);
176
177 /* Peripheral clocking will be derived from PLL0 with a divider of 2 (60MHz) */
178 Chip_Clock_SetPCLKDiv(2);
179
180 #if defined(CHIP_LPC407X_8X)
181 /* SPIFI clocking will be derived from Main PLL with a divider of 2 (60MHz) */
182 Chip_Clock_SetSPIFIClockDiv(2);
183 Chip_Clock_SetSPIFIClockSource(SYSCTL_SPIFICLKSRC_MAINPLL);
184 #endif
185
186 }
187
188 /* Sets up system pin muxing */
189 STATIC void SystemSetupMuxing(void)
190 {
191 int i, j;
192
193 Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_EMC);
194 Chip_SYSCTL_PeriphReset(SYSCTL_RESET_IOCON);
195
196 /* Setup data, address, and EMC control pins with high slew rate */
197 for (i = 3; i <= 4; i++) {
198 for (j = 0; j <= 31; j++) {
199 Chip_IOCON_PinMuxSet(LPC_IOCON, (uint8_t) i, (uint8_t) j, (IOCON_FUNC1 | IOCON_FASTSLEW_EN));
200 }
201 }
202 for (i = 16; i <= 31; i++) {
203 Chip_IOCON_PinMuxSet(LPC_IOCON, 2, (uint8_t) i, (IOCON_FUNC1 | IOCON_FASTSLEW_EN));
204 }
205
206 /* Setup system level pin muxing */
207 for (i = 0; i < (sizeof(pinmuxing) / sizeof(pinmuxing[0])); i++) {
208 Chip_IOCON_PinMuxSet(LPC_IOCON, pinmuxing[i].pingrp, pinmuxing[i].pinnum,
209 pinmuxing[i].modefunc);
210 }
211 }
212
213 /* EMC clock delay */
214 #define CLK0_DELAY 7
215
216 /* Keil SDRAM timing and chip Config */
217 STATIC const IP_EMC_DYN_CONFIG_T IS42S32800D_config = {
218 EMC_NANOSECOND(64000000 / 4096),
219 0x01, /* Command Delayed */
220 3, /* tRP */
221 7, /* tRAS */
222 EMC_NANOSECOND(70), /* tSREX */
223 EMC_CLOCK(0x01), /* tAPR */
224 EMC_CLOCK(0x05), /* tDAL */
225 EMC_NANOSECOND(12), /* tWR */
226 EMC_NANOSECOND(60), /* tRC */
227 EMC_NANOSECOND(60), /* tRFC */
228 EMC_NANOSECOND(70), /* tXSR */
229 EMC_NANOSECOND(12), /* tRRD */
230 EMC_CLOCK(0x02), /* tMRD */
231 {
232 {
233 EMC_ADDRESS_DYCS0, /* EA Board uses DYCS0 for SDRAM */
234 2, /* RAS */
235
236 EMC_DYN_MODE_WBMODE_PROGRAMMED |
237 EMC_DYN_MODE_OPMODE_STANDARD |
238 EMC_DYN_MODE_CAS_2 |
239 EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL |
240 EMC_DYN_MODE_BURST_LEN_4,
241
242 EMC_DYN_CONFIG_DATA_BUS_32 |
243 EMC_DYN_CONFIG_LPSDRAM |
244 EMC_DYN_CONFIG_8Mx16_4BANKS_12ROWS_9COLS |
245 EMC_DYN_CONFIG_MD_SDRAM
246 },
247 {0, 0, 0, 0},
248 {0, 0, 0, 0},
249 {0, 0, 0, 0}
250 }
251 };
252
253 /* NorFlash timing and chip Config */
254 STATIC const IP_EMC_STATIC_CONFIG_T SST39VF320_config = {
255 0,
256 EMC_STATIC_CONFIG_MEM_WIDTH_16 |
257 EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW |
258 EMC_STATIC_CONFIG_BLS_HIGH /* |
259 EMC_CONFIG_BUFFER_ENABLE*/,
260
261 EMC_NANOSECOND(0),
262 EMC_NANOSECOND(35),
263 EMC_NANOSECOND(70),
264 EMC_NANOSECOND(70),
265 EMC_NANOSECOND(40),
266 EMC_CLOCK(4)
267 };
268
269 /* NandFlash timing and chip Config */
270 STATIC const IP_EMC_STATIC_CONFIG_T K9F1G_config = {
271 1,
272 EMC_STATIC_CONFIG_MEM_WIDTH_8 |
273 EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW |
274 EMC_STATIC_CONFIG_BLS_HIGH /* |
275 EMC_CONFIG_BUFFER_ENABLE*/,
276
277 EMC_NANOSECOND(0),
278 EMC_NANOSECOND(35),
279 EMC_NANOSECOND(70),
280 EMC_NANOSECOND(70),
281 EMC_NANOSECOND(40),
282 EMC_CLOCK(4)
283 };
284
285 /* Setup external memories */
286 STATIC void SystemSetupMemory(void)
287 {
288 /* Setup EMC Delays */
289 /* Move all clock delays together */
290 LPC_SYSCTL->EMCDLYCTL = (CLK0_DELAY) | (CLK0_DELAY << 8) | (CLK0_DELAY << 16 | (CLK0_DELAY << 24));
291
292 /* Setup EMC Clock Divider for divide by 2 */
293 /* Setup EMC clock for a divider of 2 from CPU clock. Enable EMC clock for
294 external memory setup of DRAM. */
295 Chip_Clock_SetEMCClockDiv(SYSCTL_EMC_DIV2);
296 Chip_SYSCTL_PeriphReset(SYSCTL_RESET_EMC);
297
298 /* Init EMC Controller -Enable-LE mode- clock ratio 1:1 */
299 Chip_EMC_Init(1, 0, 0);
300
301 /* Init EMC Dynamic Controller */
302 Chip_EMC_Dynamic_Init((IP_EMC_DYN_CONFIG_T *) &IS42S32800D_config);
303
304 /* Init EMC Static Controller CS0 */
305 Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_T *) &SST39VF320_config);
306
307
308 /* Init EMC Static Controller CS1 */
309 Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_T *) &K9F1G_config);
310
311 /* EMC Shift Control */
312 LPC_SYSCTL->SCS |= 1;
313 }
314
315 /*****************************************************************************
316 * Public functions
317 ****************************************************************************/
318
326 void SystemInit(void)
327 {
328 #if defined(CORE_M3) || defined(CORE_M4)
329 unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
330
331 #if defined(__IAR_SYSTEMS_ICC__)
332 extern void *__vector_table;
333
334 *pSCB_VTOR = (unsigned int) &__vector_table;
335 #elif defined(__CODE_RED)
336 extern void *g_pfnVectors;
337
338 *pSCB_VTOR = (unsigned int) &g_pfnVectors;
339 #elif defined(__ARMCC_VERSION)
340 extern void *__Vectors;
341
342 *pSCB_VTOR = (unsigned int) &__Vectors;
343 #endif
344
345 #if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
346 fpuInit();
347 #endif
348
349 /* Setup system clocking and memory. This is done early to allow the
350 application and tools to clear memory and use scatter loading to
351 external memory. */
352 SystemSetupClocking();
353 SystemSetupMuxing();
354 SystemSetupMemory();
355 #endif
356 }
357