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can_001.h
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1 /*
2 * @brief CAN registers and control functions
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __CAN_001_H_
33 #define __CAN_001_H_
34
35 #include "sys_config.h"
36 #include "cmsis.h"
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
49 #define CANAF_RAM_ENTRY_NUM 512
50
54 typedef enum IP_CAN_AF_RAM_SECTION {
55 CANAF_RAM_FULLCAN_SEC,
56 CANAF_RAM_SFF_SEC,
57 CANAF_RAM_SFF_GRP_SEC,
58 CANAF_RAM_EFF_SEC,
59 CANAF_RAM_EFF_GRP_SEC,
60 CANAF_RAM_SECTION_NUM,
61 } IP_CAN_AF_RAM_SECTION_T;
62
66 typedef struct
67 {
68 __IO uint32_t MASK[CANAF_RAM_ENTRY_NUM];
69 } IP_CAN_001_AF_RAM_T;
70
74 typedef struct
75 {
76 __IO uint32_t AFMR;
77 __IO uint32_t ENDADDR[CANAF_RAM_SECTION_NUM];
78 __I uint32_t LUTERRAD;
79 __I uint32_t LUTERR;
80 __IO uint32_t FCANIE;
81 __IO uint32_t FCANIC[2];
82 } IP_CAN_001_AF_T;
83
87 typedef struct
88 {
89 __I uint32_t TXSR;
90 __I uint32_t RXSR;
91 __I uint32_t MSR;
92 } IP_CAN_001_CR_T;
93
97 typedef struct
98 {
99 __IO uint32_t TFI;
100 __IO uint32_t TID;
101 __IO uint32_t TD[2];
102 } IP_CAN_001_TX_T;
103
107 typedef struct
108 {
109 __IO uint32_t RFS;
116 __IO uint32_t RID;
117 __IO uint32_t RD[2];
118 } IP_CAN_001_RX_T;
119
123 typedef struct
124 {
125 __IO uint32_t MOD;
126 __O uint32_t CMR;
127 __IO uint32_t GSR;
128 __I uint32_t ICR;
129 __IO uint32_t IER;
130 __IO uint32_t BTR;
131 __IO uint32_t EWL;
132 __I uint32_t SR;
133 __IO IP_CAN_001_RX_T RX;
134 __IO IP_CAN_001_TX_T TX[3];
135 } IP_CAN_001_T;
136
141 #define CAN_MOD_BITMASK (0xBF)
142
144 #define CAN_MOD_OPERATION ((uint32_t) 0)
145
147 #define CAN_MOD_RM ((uint32_t) (1 << 0))
148
150 #define CAN_MOD_LOM ((uint32_t) (1 << 1))
151
153 #define CAN_MOD_STM ((uint32_t) (1 << 2))
154
156 #define CAN_MOD_TPM ((uint32_t) (1 << 3))
157
159 #define CAN_MOD_SM ((uint32_t) (1 << 4))
160
162 #define CAN_MOD_RPM ((uint32_t) (1 << 5))
163
165 #define CAN_MOD_TM ((uint32_t) (1 << 7))
166
171 #define CAN_CMR_BITMASK (0xFF)
172
174 #define CAN_CMR_TR ((uint32_t) (1))
175
177 #define CAN_CMR_AT ((uint32_t) (1 << 1))
178
180 #define CAN_CMR_RRB ((uint32_t) (1 << 2))
181
183 #define CAN_CMR_CDO ((uint32_t) (1 << 3))
184
186 #define CAN_CMR_SRR ((uint32_t) (1 << 4))
187
189 #define CAN_CMR_STB(n) ((uint32_t) (1 << (n + 5)))
190
195 #define CAN_GSR_BITMASK (0xFFFF00FF)
196
198 #define CAN_GSR_RBS ((uint32_t) (1))
199
201 #define CAN_GSR_DOS ((uint32_t) (1 << 1))
202
204 #define CAN_GSR_TBS ((uint32_t) (1 << 2))
205
207 #define CAN_GSR_TCS ((uint32_t) (1 << 3))
208
210 #define CAN_GSR_RS ((uint32_t) (1 << 4))
211
213 #define CAN_GSR_TS ((uint32_t) (1 << 5))
214
216 #define CAN_GSR_ES ((uint32_t) (1 << 6))
217
219 #define CAN_GSR_BS ((uint32_t) (1 << 7))
220
222 #define CAN_GSR_RXERR(n) ((uint32_t) ((n >> 16) & 0xFF)
223
225 #define CAN_GSR_TXERR(n) ((uint32_t) ((n >> 24) & 0xFF)
226
231 #define CAN_ICR_BITMASK (0xFFFF07FF)
232
234 #define CAN_ICR_RI ((uint32_t) (1))
235
237 #define CAN_ICR_TI1 ((uint32_t) (1 << 1))
238
240 #define CAN_ICR_EI ((uint32_t) (1 << 2))
241
243 #define CAN_ICR_DOI ((uint32_t) (1 << 3))
244
246 #define CAN_ICR_WUI ((uint32_t) (1 << 4))
247
249 #define CAN_ICR_EPI ((uint32_t) (1 << 5))
250
252 #define CAN_ICR_ALI ((uint32_t) (1 << 6))
253
255 #define CAN_ICR_BEI ((uint32_t) (1 << 7))
256
258 #define CAN_ICR_IDI ((uint32_t) (1 << 8))
259
261 #define CAN_ICR_TI2 ((uint32_t) (1 << 9))
262
264 #define CAN_ICR_TI3 ((uint32_t) (1 << 10))
265
267 #define CAN_ICR_ERRBIT_VAL(n) ((uint32_t) (((n) >> 16) & 0x1F))
268
269 #define CAN_ICR_ERR_SOF (3)
270
271 #define CAN_ICR_ERR_ID28_ID21 (2)
272
273 #define CAN_ICR_ERR_ID20_ID18 (6)
274
275 #define CAN_ICR_ERR_SRTR (4)
276
277 #define CAN_ICR_ERR_IDE (5)
278
279 #define CAN_ICR_ERR_ID17_ID13 (7)
280
281 #define CAN_ICR_ERR_ID12_ID5 (0x0F)
282
283 #define CAN_ICR_ERR_ID4_ID0 (0x0E)
284
285 #define CAN_ICR_ERR_RTR (0x0C)
286
287 #define CAN_ICR_ERR_ReservedBit_1 (0x0D)
288
289 #define CAN_ICR_ERR_ReservedBit_0 (0x09)
290
291 #define CAN_ICR_ERR_DLC (0x0B)
292
293 #define CAN_ICR_ERR_DATA_FIELD (0x0A)
294
295 #define CAN_ICR_ERR_CRC_SEQ (0x08)
296
297 #define CAN_ICR_ERR_CRC_DELIMITER (0x18)
298
299 #define CAN_ICR_ERR_ACK (0x19)
300
301 #define CAN_ICR_ERR_ACK_DELIMITER (0x1B)
302
303 #define CAN_ICR_ERR_EOF (0x1A)
304
305 #define CAN_ICR_ERR_INTERMISSION (0x12)
306
308 #define CAN_ICR_ERRDIR_RECEIVE ((uint32_t) (1 << 21))
309
311 #define CAN_ICR_ERRC_VAL(n) ((uint32_t) (((n) >> 22) & 0x3))
312 #define CAN_ICR_BIT_ERROR (0)
313 #define CAN_ICR_FORM_ERROR (1)
314 #define CAN_ICR_STUFF_ERROR (2)
315 #define CAN_ICR_OTHER_ERROR (3)
316
318 #define CAN_ICR_ALCBIT_VAL(n) ((uint32_t) (((n) >> 24) & 0xFF))
319
324 #define CAN_IER_BITMASK (0x7FF)
325
327 #define CAN_IER_RIE ((uint32_t) (1))
328
330 #define CAN_IER_TIE1 ((uint32_t) (1 << 1))
331
333 #define CAN_IER_EIE ((uint32_t) (1 << 2))
334
336 #define CAN_IER_DOIE ((uint32_t) (1 << 3))
337
339 #define CAN_IER_WUIE ((uint32_t) (1 << 4))
340
342 #define CAN_IER_EPIE ((uint32_t) (1 << 5))
343
345 #define CAN_IER_ALIE ((uint32_t) (1 << 6))
346
348 #define CAN_IER_BEIE ((uint32_t) (1 << 7))
349
351 #define CAN_IER_IDIE ((uint32_t) (1 << 8))
352
354 #define CAN_IER_TIE2 ((uint32_t) (1 << 9))
355
357 #define CAN_IER_TIE3 ((uint32_t) (1 << 10))
358
363 #define CAN_BTR_BITMASK (0xFFC3FF)
364
366 #define CAN_BTR_BRP(n) ((uint32_t) ((n) & 0x3FF))
367
369 #define CAN_BTR_SJW(n) ((uint32_t) (((n) & 0x3) << 14))
370
372 #define CAN_BTR_TESG1(n) ((uint32_t) (((n) & 0xF) << 16))
373
375 #define CAN_BTR_TESG2(n) ((uint32_t) (((n) & 0xF) << 20))
376
378 #define CAN_BTR_SAM ((uint32_t) (1 << 23))
379
384 #define CAN_EWL_BITMASK (0xFF)
385
387 #define CAN_EWL_VAL(n) ((uint32_t) ((n) & 0xFF))
388
393 #define CAN_SR_BITMASK (0xFFFFFF)
394
396 #define CAN_SR_RBS(n) ((uint32_t) (1 << ((n) * 8)))
397
399 #define CAN_SR_DOS(n) ((uint32_t) (1 << (1 + (n) * 8)))
400
402 #define CAN_SR_TBS(n) ((uint32_t) (1 << (2 + (n) * 8)))
403
405 #define CAN_SR_TCS(n) ((uint32_t) (1 << (3 + (n) * 8)))
406
408 #define CAN_SR_RS(n) ((uint32_t) (1 << (4 + (n) * 8)))
409
411 #define CAN_SR_TS(n) ((uint32_t) (1 << (5 + (n) * 8)))
412
414 #define CAN_SR_ES(n) ((uint32_t) (1 << (6 + (n) * 8)))
415
417 #define CAN_SR_BS(n) ((uint32_t) (1 << (7 + (n) * 8)))
418
423 #define CAN_RFS_BITMASK (0xC00F07FF)
424
426 #define CAN_RFS_ID_INDEX(n) ((uint32_t) ((n) & 0x3FF))
427
429 #define CAN_RFS_BP ((uint32_t) (1 << 10))
430
432 #define CAN_RFS_DLC(n) ((uint32_t) ((n >> 16) & 0x0F))
433
435 #define CAN_RFS_RTR ((uint32_t) (1 << 30))
436
438 #define CAN_RFS_FF ((uint32_t) ((uint32_t) 1 << 31))
439
444 #define CAN_RID_ID_11(n) ((uint32_t) ((n) & 0x7FF))
445
447 #define CAN_RID_ID_29(n) ((uint32_t) ((n) & 0x1FFFFFFF))
448
453 #define CAN_TFI_BITMASK (0xC00F00FF)
454
456 #define CAN_TFI_PRIO(n) ((uint32_t) ((n) & 0xFF))
457
459 #define CAN_TFI_DLC(n) ((uint32_t) (((n) & 0xF) << 16))
460
462 #define CAN_TFI_RTR ((uint32_t) (1 << 30))
463
465 #define CAN_TFI_FF ((uint32_t) ((uint32_t) 1 << 31))
466
471 #define CAN_TID_ID11(n) ((uint32_t) ((n) & 0x7FF))
472
474 #define CAN_TID_ID29(n) ((uint32_t) ((n) & 0x1FFFFFFF))
475
480 #define CAN_TSR_BITMASK (0x30303)
481
483 #define CAN_TSR_TS(n) ((uint32_t) (1 << (n + 0)))
484
486 #define CAN_TSR_TBS(n) ((uint32_t) (1 << (n + 8)))
487
489 #define CAN_TSR_TCS(n) ((uint32_t) (1 << (n + 16)))
490
495 #define CAN_RSR_BITMASK (0x30303)
496
498 #define CAN_RSR_RS(n) ((uint32_t) (1 << (n + 0)))
499
501 #define CAN_RSR_RBS(n) ((uint32_t) (1 << (n + 8)))
502
505 #define CAN_RSR_DOS(n) ((uint32_t) (1 << (n + 16)))
506
511 #define CAN_MSR_BITMASK (0x303)
512
514 #define CAN_MSR_E(n) ((uint32_t) (1 << (n + 0)))
515
517 #define CAN_MSR_BS(n) ((uint32_t) (1 << (n + 8)))
518
523 #define CANAF_AFMR_OPERATION ((uint32_t) (0))
524
526 #define CANAF_AFMR_ACCOFF ((uint32_t) (1))
527
529 #define CANAF_AFMR_ACCBP ((uint32_t) (1 << 1))
530
532 #define CANAF_AFMR_EFCAN ((uint32_t) (1 << 2))
533
538 #define CANAF_ENDADDR(n) ((uint32_t) (((n) & 0x3FF) << 2))
539 #define CANAF_ENDADDR_VAL(n) ((uint32_t) ((n >> 2) & 0x3FF))
540
545 #define CANAF_LUTERRAD(n) ((uint32_t) (((n) & 0x1FF) << 2))
546
551 #define CANAF_LUTERR ((uint32_t) (1))
552
557 #define CANAF_FCANIE_BITMASK (0x01)
558
560 #define CANAF_FCANIE ((uint32_t) (1))
561
567 #define CANAF_FULLCAN_MSG_FF_POS (31)
568
569 #define CANAF_FULLCAN_MSG_RTR_POS (30)
570
571 #define CANAF_FULLCAN_MSG_LOST_POS (26)
572
573 #define CANAF_FULLCAN_MSG_SEM_POS (24)
574
575 #define CANAF_FULLCAN_MSG_SEM_BITMASK (0x03)
576
577 #define CANAF_FULLCAN_MSG_DLC_POS (16)
578
579 #define CANAF_FULLCAN_MSG_DLC_BITMASK (0x0F)
580
581 #define CANAF_FULLCAN_MSG_SCC_POS (13)
582
583 #define CANAF_FULLCAN_MSG_SCC_BITMASK (0x07)
584
585 #define CANAF_FULLCAN_MSG_ID11_POS (0)
586
587 #define CANAF_FULLCAN_MSG_ID11_BITMASK (0x7FF)
588
593 #define CANAF_FULCAN_MSG_AF_UPDATING (0x01)
594
595 #define CANAF_FULCAN_MSG_AF_FINISHED (0x03)
596
597 #define CANAF_FULCAN_MSG_CPU_READING (0x0)
598
603 #define CANAF_FCAN_IC_INTPND(n) ((n >= 32) ? ((uint32_t) (1 << (n - 32))) : ((uint32_t) (1 << n)))
604
609 #define CAN_STD_ENTRY_CTRL_NO_POS (13 )
610
611 #define CAN_STD_ENTRY_CTRL_NO_MASK (0x07)
612
613 #define CAN_STD_ENTRY_DISABLE_POS (12 )
614
615 #define CAN_STD_ENTRY_DISABLE_MASK (0x01)
616
617 #define CAN_STD_ENTRY_IE_POS (11 )
618
619 #define CAN_STD_ENTRY_IE_MASK (0x01)
620
621 #define CAN_STD_ENTRY_ID_POS (0 )
622
623 #define CAN_STD_ENTRY_ID_MASK (0x7FF)
624
629 #define CAN_EXT_ENTRY_CTRL_NO_POS (29 )
630
631 #define CAN_EXT_ENTRY_CTRL_NO_MASK (0x07)
632
633 #define CAN_EXT_ENTRY_ID_POS (0 )
634
635 #define CAN_EXT_ENTRY_ID_MASK (0x1FFFFFFF)
636
642 #define CAN_REMOTE_MSG ((uint32_t) (1 << 0))
643
645 #define CAN_EXTEND_ID_USAGE ((uint32_t) (1 << 30))
646
648 #define CAN_MSG_MAX_DATA_LEN (8)
649
653 typedef enum IP_CAN_BUFFER_ID {
654 CAN_BUFFER_1 = 0,
655 CAN_BUFFER_2,
656 CAN_BUFFER_3,
657 CAN_BUFFER_LAST,
658 } IP_CAN_BUFFER_ID_T;
659
663 typedef struct
664 {
665 uint32_t ID;
666 uint32_t Type;
667 uint32_t DLC;
668 uint8_t Data[CAN_MSG_MAX_DATA_LEN];
669 } IP_CAN_MSG_T;
670
674 typedef struct
675 {
676 uint16_t BRP;
677 uint8_t SJW;
678 uint8_t TESG1;
679 uint8_t TESG2;
680 uint8_t SAM;
681 } IP_CAN_BUS_TIMING_T;
682
686 typedef struct {
687 uint8_t CtrlNo;
688 uint8_t Disable;
689 uint16_t ID_11;
690 } IP_CAN_STD_ID_Entry_T;
691
695 typedef struct {
696 IP_CAN_STD_ID_Entry_T LowerID;
697 IP_CAN_STD_ID_Entry_T UpperID;
698 } IP_CAN_STD_ID_RANGE_Entry_T;
699
703 typedef struct {
704 uint8_t CtrlNo;
705 uint32_t ID_29;
706 } IP_CAN_EXT_ID_Entry_T;
707
711 typedef struct {
712 IP_CAN_EXT_ID_Entry_T LowerID;
713 IP_CAN_EXT_ID_Entry_T UpperID;
714 } IP_CAN_EXT_ID_RANGE_Entry_T;
715
719 typedef struct {
720 IP_CAN_STD_ID_Entry_T *FullCANSec;
721 uint16_t FullCANEntryNum;
722 IP_CAN_STD_ID_Entry_T *SffSec;
723 uint16_t SffEntryNum;
724 IP_CAN_STD_ID_RANGE_Entry_T *SffGrpSec;
725 uint16_t SffGrpEntryNum;
726 IP_CAN_EXT_ID_Entry_T *EffSec;
727 uint16_t EffEntryNum;
728 IP_CAN_EXT_ID_RANGE_Entry_T *EffGrpSec;
729 uint16_t EffGrpEntryNum;
730 } IP_CAN_AF_LUT_T;
731
737 STATIC INLINE void IP_CAN_DeInit(IP_CAN_001_T *pCAN)
738 {}
739
745 STATIC INLINE uint32_t IP_CAN_GetMode(IP_CAN_001_T *pCAN)
746 {
747 return pCAN->MOD & CAN_MOD_BITMASK;
748 }
749
756 STATIC INLINE void IP_CAN_SetCmd(IP_CAN_001_T *pCAN, uint32_t command)
757 {
758 pCAN->CMR = command;
759 }
760
767 STATIC INLINE void IP_CAN_SetEWL(IP_CAN_001_T *pCAN, uint32_t ewl)
768 {
769 pCAN->EWL = ewl & CAN_EWL_BITMASK;
770 }
771
777 STATIC INLINE uint8_t IP_CAN_GetEWL(IP_CAN_001_T *pCAN)
778 {
779 return CAN_EWL_VAL(pCAN->EWL);
780 }
781
787 STATIC INLINE uint32_t IP_CAN_GetGlobalStatus(IP_CAN_001_T *pCAN)
788 {
789 return pCAN->GSR;
790 }
791
797 STATIC INLINE uint32_t IP_CAN_GetStatus(IP_CAN_001_T *pCAN)
798 {
799 return pCAN->SR;
800 }
801
808 STATIC INLINE void IP_CAN_IntEnable(IP_CAN_001_T *pCAN, uint32_t IntMask) {
809 pCAN->IER |= IntMask;
810 }
811
818 STATIC INLINE void IP_CAN_IntDisable(IP_CAN_001_T *pCAN, uint32_t IntMask) {
819 pCAN->IER &= (~IntMask) & CAN_IER_BITMASK;
820 }
821
827 STATIC INLINE uint32_t IP_CAN_GetIntStatus(IP_CAN_001_T *pCAN)
828 {
829 return pCAN->ICR;
830 }
831
838 STATIC INLINE void IP_CAN_AF_SetMode(IP_CAN_001_AF_T *pCanAF, uint32_t AFMode)
839 {
840 pCanAF->AFMR = AFMode;
841 }
842
848 STATIC INLINE uint32_t IP_CAN_AF_GetMode(IP_CAN_001_AF_T *pCanAF)
849 {
850 return pCanAF->AFMR;
851 }
852
858 void IP_CAN_Init(IP_CAN_001_T *pCAN);
859
867 void IP_CAN_SetMode(IP_CAN_001_T *pCAN, uint32_t Mode, FunctionalState NewState);
868
875 void IP_CAN_SetBusTiming(IP_CAN_001_T *pCAN, IP_CAN_BUS_TIMING_T *pBusTiming);
876
883 Status IP_CAN_Receive(IP_CAN_001_T *pCAN, IP_CAN_MSG_T *pMsg);
884
892 Status IP_CAN_Send(IP_CAN_001_T *pCAN, IP_CAN_BUFFER_ID_T TxBufID, IP_CAN_MSG_T *pMsg);
893
900 void IP_CAN_AF_Init(IP_CAN_001_AF_T *pCanAF, IP_CAN_001_AF_RAM_T *pCanAFRam);
901
908 void IP_CAN_FullCANIntConfig(IP_CAN_001_AF_T *pCanAF, FunctionalState NewState);
909
916 uint32_t IP_CAN_GetFullCANIntStatus(IP_CAN_001_AF_T *pCanAF, uint8_t ObjID);
917
927 Status IP_CAN_FullCANReceive(IP_CAN_001_AF_T *pCanAF, IP_CAN_001_AF_RAM_T *pCanAFRam,
928 uint8_t ObjID, IP_CAN_MSG_T *pMsg, uint8_t *pSCC);
929
936 void IP_CAN_ClearAFLUT(IP_CAN_001_AF_T *pCanAF, IP_CAN_001_AF_RAM_T *pCanAFRam);
937
945 Status IP_CAN_SetAFLUT(IP_CAN_001_AF_T *pCanAF, IP_CAN_001_AF_RAM_T *pCanAFRam, IP_CAN_AF_LUT_T *pAFSections);
946
954 Status IP_CAN_InsertFullCANEntry(IP_CAN_001_AF_T *pCanAF,
955 IP_CAN_001_AF_RAM_T *pCanAFRam,
956 IP_CAN_STD_ID_Entry_T *pEntry);
957
965 Status IP_CAN_InsertIndividualSTDEntry(IP_CAN_001_AF_T *pCanAF,
966 IP_CAN_001_AF_RAM_T *pCanAFRam,
967 IP_CAN_STD_ID_Entry_T *pEntry);
968
976 Status IP_CAN_InsertGroupSTDEntry(IP_CAN_001_AF_T *pCanAF,
977 IP_CAN_001_AF_RAM_T *pCanAFRam,
978 IP_CAN_STD_ID_RANGE_Entry_T *pEntry);
979
987 Status IP_CAN_InsertIndividualEXTEntry(IP_CAN_001_AF_T *pCanAF,
988 IP_CAN_001_AF_RAM_T *pCanAFRam,
989 IP_CAN_EXT_ID_Entry_T *pEntry);
990
998 Status IP_CAN_InsertGroupEXTEntry(IP_CAN_001_AF_T *pCanAF,
999 IP_CAN_001_AF_RAM_T *pCanAFRam,
1000 IP_CAN_EXT_ID_RANGE_Entry_T *pEntry);
1001
1009 Status IP_CAN_RemoveFullCANEntry(IP_CAN_001_AF_T *pCanAF,
1010 IP_CAN_001_AF_RAM_T *pCanAFRam,
1011 int16_t Position);
1012
1020 Status IP_CAN_RemoveIndividualSTDEntry(IP_CAN_001_AF_T *pCanAF,
1021 IP_CAN_001_AF_RAM_T *pCanAFRam,
1022 int16_t Position);
1023
1031 Status IP_CAN_RemoveGroupSTDEntry(IP_CAN_001_AF_T *pCanAF,
1032 IP_CAN_001_AF_RAM_T *pCanAFRam,
1033 int16_t Position);
1034
1042 Status IP_CAN_RemoveIndividualEXTEntry(IP_CAN_001_AF_T *pCanAF,
1043 IP_CAN_001_AF_RAM_T *pCanAFRam,
1044 int16_t Position);
1045
1053 Status IP_CAN_RemoveGroupEXTEntry(IP_CAN_001_AF_T *pCanAF,
1054 IP_CAN_001_AF_RAM_T *pCanAFRam,
1055 int16_t Position);
1056
1064 uint16_t IP_CAN_GetEntriesNum(IP_CAN_001_AF_T *pCanAF,
1065 IP_CAN_001_AF_RAM_T *pCanAFRam,
1066 IP_CAN_AF_RAM_SECTION_T SectionID);
1067
1076 Status IP_CAN_ReadFullCANEntry(IP_CAN_001_AF_T *pCanAF,
1077 IP_CAN_001_AF_RAM_T *pCanAFRam,
1078 uint16_t Position,
1079 IP_CAN_STD_ID_Entry_T *pEntry);
1080
1089 Status IP_CAN_ReadIndividualSTDEntry(IP_CAN_001_AF_T *pCanAF,
1090 IP_CAN_001_AF_RAM_T *pCanAFRam,
1091 uint16_t Position,
1092 IP_CAN_STD_ID_Entry_T *pEntry);
1093
1102 Status IP_CAN_ReadGroupSTDEntry(IP_CAN_001_AF_T *pCanAF,
1103 IP_CAN_001_AF_RAM_T *pCanAFRam,
1104 uint16_t Position,
1105 IP_CAN_STD_ID_RANGE_Entry_T *pEntry);
1106
1115 Status IP_CAN_ReadIndividualEXTEntry(IP_CAN_001_AF_T *pCanAF,
1116 IP_CAN_001_AF_RAM_T *pCanAFRam,
1117 uint16_t Position,
1118 IP_CAN_EXT_ID_Entry_T *pEntry);
1119
1128 Status IP_CAN_ReadGroupEXTEntry(IP_CAN_001_AF_T *pCanAF,
1129 IP_CAN_001_AF_RAM_T *pCanAFRam,
1130 uint16_t Position,
1131 IP_CAN_EXT_ID_RANGE_Entry_T *pEntry);
1132
1137 #ifdef __cplusplus
1138 }
1139 #endif
1140
1141 #endif /* __CAN_001_H_ */