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cmsis.h
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1 /*
2 * @brief Basic CMSIS include file
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __CMSIS_H_
33 #define __CMSIS_H_
34
35 #include "lpc_types.h"
36 #include "sys_config.h"
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
47 #if defined(__ARMCC_VERSION)
48 // Kill warning "#pragma push with no matching #pragma pop"
49 #pragma diag_suppress 2525
50 #pragma push
51 #pragma anon_unions
52 #elif defined(__CWCC__)
53 #pragma push
54 #pragma cpp_extensions on
55 #elif defined(__GNUC__)
56 /* anonymous unions are enabled by default */
57 #elif defined(__IAR_SYSTEMS_ICC__)
58 // #pragma push // FIXME not usable for IAR
59 #pragma language=extended
60 #else
61 #error Not supported compiler type
62 #endif
63
64 /*
65 * ==========================================================================
66 * ---------- Interrupt Number Definition -----------------------------------
67 * ==========================================================================
68 */
69 #if defined(CHIP_LPC1343)
70
75 typedef enum IRQn {
76 Reset_IRQn = -15,
77 NonMaskableInt_IRQn = -14,
78 MemoryManagement_IRQn = -12,
79 BusFault_IRQn = -11,
80 UsageFault_IRQn = -10,
81 SVCall_IRQn = -5,
82 DebugMonitor_IRQn = -4,
83 PendSV_IRQn = -2,
84 SysTick_IRQn = -1,
86 /****** LPC13xx Specific Interrupt Numbers *******************************************************/
87 WAKEUP0_IRQn = 0,
88 WAKEUP1_IRQn = 1,
89 WAKEUP2_IRQn = 2,
90 WAKEUP3_IRQn = 3,
91 WAKEUP4_IRQn = 4,
92 WAKEUP5_IRQn = 5,
93 WAKEUP6_IRQn = 6,
94 WAKEUP7_IRQn = 7,
95 WAKEUP8_IRQn = 8,
96 WAKEUP9_IRQn = 9,
97 WAKEUP10_IRQn = 10,
98 WAKEUP11_IRQn = 11,
99 WAKEUP12_IRQn = 12,
100 WAKEUP13_IRQn = 13,
101 WAKEUP14_IRQn = 14,
102 WAKEUP15_IRQn = 15,
103 WAKEUP16_IRQn = 16,
104 WAKEUP17_IRQn = 17,
105 WAKEUP18_IRQn = 18,
106 WAKEUP19_IRQn = 19,
107 WAKEUP20_IRQn = 20,
108 WAKEUP21_IRQn = 21,
109 WAKEUP22_IRQn = 22,
110 WAKEUP23_IRQn = 23,
111 WAKEUP24_IRQn = 24,
112 WAKEUP25_IRQn = 25,
113 WAKEUP26_IRQn = 26,
114 WAKEUP27_IRQn = 27,
115 WAKEUP28_IRQn = 28,
116 WAKEUP29_IRQn = 29,
117 WAKEUP30_IRQn = 30,
118 WAKEUP31_IRQn = 31,
119 WAKEUP32_IRQn = 32,
120 WAKEUP33_IRQn = 33,
121 WAKEUP34_IRQn = 34,
122 WAKEUP35_IRQn = 35,
123 WAKEUP36_IRQn = 36,
124 WAKEUP37_IRQn = 37,
125 WAKEUP38_IRQn = 38,
126 WAKEUP39_IRQn = 39,
127 I2C0_IRQn = 40,
128 TIMER_16_0_IRQn = 41,
129 TIMER_16_1_IRQn = 42,
130 TIMER_32_0_IRQn = 43,
131 TIMER_32_1_IRQn = 44,
132 SSP0_IRQn = 45,
133 UART0_IRQn = 46,
134 USB0_IRQn = 47,
135 USB0_FIQ_IRQn = 48,
136 ADC_IRQn = 49,
137 WDT_IRQn = 50,
138 BOD_IRQn = 51,
139 EINT3_IRQn = 53,
140 EINT2_IRQn = 54,
141 EINT1_IRQn = 55,
142 EINT0_IRQn = 56,
143 SSP1_IRQn = 57,
144 } IRQn_Type;
145
150 #elif defined(CHIP_LPC1347)
151
156 typedef enum IRQn {
157 Reset_IRQn = -15,
158 NonMaskableInt_IRQn = -14,
159 HardFault_IRQn = -13,
160 MemoryManagement_IRQn = -12,
161 BusFault_IRQn = -11,
162 UsageFault_IRQn = -10,
163 SVCall_IRQn = -5,
164 DebugMonitor_IRQn = -4,
165 PendSV_IRQn = -2,
166 SysTick_IRQn = -1,
168 /****** LPC1347 Specific Interrupt Numbers *******************************************************/
169 PIN_INT0_IRQn = 0,
170 PIN_INT1_IRQn = 1,
171 PIN_INT2_IRQn = 2,
172 PIN_INT3_IRQn = 3,
173 PIN_INT4_IRQn = 4,
174 PIN_INT5_IRQn = 5,
175 PIN_INT6_IRQn = 6,
176 PIN_INT7_IRQn = 7,
177 GINT0_IRQn = 8,
178 GINT1_IRQn = 9,
179 Reserved0_IRQn = 10,
180 Reserved1_IRQn = 11,
181 RIT_IRQn = 12,
182 Reserved2_IRQn = 13,
183 SSP1_IRQn = 14,
184 I2C0_IRQn = 15,
185 TIMER_16_0_IRQn = 16,
186 TIMER_16_1_IRQn = 17,
187 TIMER_32_0_IRQn = 18,
188 TIMER_32_1_IRQn = 19,
189 SSP0_IRQn = 20,
190 UART0_IRQn = 21,
191 USB0_IRQn = 22,
192 USB0_FIQ_IRQn = 23,
193 ADC_IRQn = 24,
194 WDT_IRQn = 25,
195 BOD_IRQn = 26,
196 FMC_IRQn = 27,
197 Reserved3_IRQn = 28,
198 Reserved4_IRQn = 29,
199 USB_WAKEUP_IRQn = 30,
200 Reserved5_IRQn = 31,
201 } IRQn_Type;
202
207 #else
208 #error Incorrect or missing device variant (CHIP_1343 or CHIP_1347)
209 #endif
210
211 /*
212 * ==========================================================================
213 * ----------- Processor and Core Peripheral Section ------------------------
214 * ==========================================================================
215 */
216
217 #if defined(CHIP_LPC1343)
218
222 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
223 #define __MPU_PRESENT 0
224 #define __NVIC_PRIO_BITS 3
225 #define __Vendor_SysTickConfig 0
231 #elif defined(CHIP_LPC1347)
232
236 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
237 #define __CM3_REV 0x0201
238 #define __MPU_PRESENT 0
239 #define __NVIC_PRIO_BITS 3
240 #define __Vendor_SysTickConfig 0
246 #endif
247
248 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
249
254 #ifdef __cplusplus
255 }
256 #endif
257
258 #endif /* __CMSIS_H_ */