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i2s_001.h
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1 /*
2 * @brief I2S Registers and control functions
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __I2S_001_H_
33 #define __I2S_001_H_
34
35 #include "sys_config.h"
36 #include "cmsis.h"
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
50 typedef struct {
51 __IO uint32_t DAO;
52 __IO uint32_t DAI;
53 __O uint32_t TXFIFO;
54 __I uint32_t RXFIFO;
55 __I uint32_t STATE;
56 __IO uint32_t DMA1;
57 __IO uint32_t DMA2;
58 __IO uint32_t IRQ;
59 __IO uint32_t TXRATE;
60 __IO uint32_t RXRATE;
61 __IO uint32_t TXBITRATE;
62 __IO uint32_t RXBITRATE;
63 __IO uint32_t TXMODE;
64 __IO uint32_t RXMODE;
65 } IP_I2S_001_T;
66
71 #define I2S_WORDWIDTH_8 (0UL << 0)
72 #define I2S_WORDWIDTH_16 (1UL << 0)
73 #define I2S_WORDWIDTH_32 (3UL << 0)
76 #define I2S_STEREO (0UL << 2)
77 #define I2S_MONO (1UL << 2)
80 #define I2S_MASTER_MODE (0UL << 5)
81 #define I2S_SLAVE_MODE (1UL << 5)
84 #define I2S_STOP_ENABLE (0UL << 3)
85 #define I2S_STOP_DISABLE (1UL << 3)
88 #define I2S_RESET_ENABLE (1UL << 4)
89 #define I2S_RESET_DISABLE (0UL << 4)
92 #define I2S_MUTE_ENABLE (1UL << 15)
93 #define I2S_MUTE_DISABLE (0UL << 15)
99 #define I2S_DAO_WORDWIDTH_8 ((uint32_t) (0))
100 #define I2S_DAO_WORDWIDTH_16 ((uint32_t) (1))
101 #define I2S_DAO_WORDWIDTH_32 ((uint32_t) (3))
102 #define I2S_DAO_WORDWIDTH_MASK ((uint32_t) (3))
103
105 #define I2S_DAO_MONO ((uint32_t) (1 << 2))
108 #define I2S_DAO_STOP ((uint32_t) (1 << 3))
111 #define I2S_DAO_RESET ((uint32_t) (1 << 4))
114 #define I2S_DAO_SLAVE ((uint32_t) (1 << 5))
117 #define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t) ((n & 0x1FF) << 6))
118 #define I2S_DAO_WS_HALFPERIOD_MASK ((uint32_t) ((0x1FF) << 6))
121 #define I2S_DAO_MUTE ((uint32_t) (1 << 15))
127 #define I2S_DAI_WORDWIDTH_8 ((uint32_t) (0))
128 #define I2S_DAI_WORDWIDTH_16 ((uint32_t) (1))
129 #define I2S_DAI_WORDWIDTH_32 ((uint32_t) (3))
130 #define I2S_DAI_WORDWIDTH_MASK ((uint32_t) (3))
133 #define I2S_DAI_MONO ((uint32_t) (1 << 2))
136 #define I2S_DAI_STOP ((uint32_t) (1 << 3))
139 #define I2S_DAI_RESET ((uint32_t) (1 << 4))
142 #define I2S_DAI_SLAVE ((uint32_t) (1 << 5))
145 #define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t) ((n & 0x1FF) << 6))
146 #define I2S_DAI_WS_HALFPERIOD_MASK ((uint32_t) ((0x1FF) << 6))
151 #define I2S_STATE_IRQ ((uint32_t) (1))
152 #define I2S_STATE_DMA1 ((uint32_t) (1 << 1))
153 #define I2S_STATE_DMA2 ((uint32_t) (1 << 2))
154 #define I2S_STATE_RX_LEVEL(n) ((uint32_t) ((n & 1F) << 8))
155 #define I2S_STATE_TX_LEVEL(n) ((uint32_t) ((n & 1F) << 16))
160 #define I2S_DMA1_RX_ENABLE ((uint32_t) (1))
161 #define I2S_DMA1_TX_ENABLE ((uint32_t) (1 << 1))
162 #define I2S_DMA1_RX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 8))
163 #define I2S_DMA1_TX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 16))
168 #define I2S_DMA2_RX_ENABLE ((uint32_t) (1))
169 #define I2S_DMA2_TX_ENABLE ((uint32_t) (1 << 1))
170 #define I2S_DMA2_RX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 8))
171 #define I2S_DMA2_TX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 16))
177 #define I2S_IRQ_RX_ENABLE ((uint32_t) (1))
178 #define I2S_IRQ_TX_ENABLE ((uint32_t) (1 << 1))
179 #define I2S_IRQ_RX_DEPTH(n) ((uint32_t) ((n & 0x0F) << 8))
180 #define I2S_IRQ_RX_DEPTH_MASK ((uint32_t) ((0x0F) << 8))
181 #define I2S_IRQ_TX_DEPTH(n) ((uint32_t) ((n & 0x0F) << 16))
182 #define I2S_IRQ_TX_DEPTH_MASK ((uint32_t) ((0x0F) << 16))
183
187 #define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t) (n & 0xFF))
188 #define I2S_TXRATE_X_DIVIDER(n) ((uint32_t) ((n & 0xFF) << 8))
189 #define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t) (n & 0xFF))
190 #define I2S_RXRATE_X_DIVIDER(n) ((uint32_t) ((n & 0xFF) << 8))
195 #define I2S_TXBITRATE(n) ((uint32_t) (n & 0x3F))
196 #define I2S_RXBITRATE(n) ((uint32_t) (n & 0x3F))
197
201 #define I2S_TXMODE_CLKSEL(n) ((uint32_t) (n & 0x03))
202 #define I2S_TXMODE_4PIN_ENABLE ((uint32_t) (1 << 2))
203 #define I2S_TXMODE_MCENA ((uint32_t) (1 << 3))
204 #define I2S_RXMODE_CLKSEL(n) ((uint32_t) (n & 0x03))
205 #define I2S_RXMODE_4PIN_ENABLE ((uint32_t) (1 << 2))
206 #define I2S_RXMODE_MCENA ((uint32_t) (1 << 3))
211 typedef enum IP_I2S_TRxMode {
212 I2S_TX_MODE,
213 I2S_RX_MODE,
214 } IP_I2S_TRxMode_T;
215
219 typedef enum IP_I2S_DMARequestNumber {
220 IP_I2S_DMA_REQUEST_NUMBER_1,
221 IP_I2S_DMA_REQUEST_NUMBER_2,
222 } IP_I2S_DMARequestNumber_T;
223
224 /**********************************************************************************
225 * I2S Init/DeInit functions
226 *********************************************************************************/
227
233 void IP_I2S_Init(IP_I2S_001_T *pI2S);
234
241 void IP_I2S_DeInit(IP_I2S_001_T *pI2S);
242
243 /**********************************************************************************
244 * I2S configuration functions
245 *********************************************************************************/
246
257 void IP_I2S_SetWordWidth(IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t wordwidth);
258
268 void IP_I2S_SetMono(IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t mono);
269
279 void IP_I2S_SetMasterSlaveMode(IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t mode);
280
290 void IP_I2S_SetBitRate(IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t mclk_divider);
291
307 void IP_I2S_SetXYDivider(IP_I2S_001_T *pI2S, uint8_t TRMode, uint8_t x_divider, uint8_t y_devider);
308
318 void IP_I2S_SetWS_Halfperiod(IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t ws_halfperiod);
319
333 void IP_I2S_ModeConfig(IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t clksel, uint32_t fpin, uint32_t mcena);
334
341 uint8_t IP_I2S_GetLevel(IP_I2S_001_T *pI2S, uint8_t TRMode);
342
343 /**********************************************************************************
344 * I2S operate functions
345 *********************************************************************************/
346
354 void IP_I2S_Send(IP_I2S_001_T *pI2S, uint32_t data);
355
362 uint32_t IP_I2S_Receive(IP_I2S_001_T *pI2S);
363
370 void IP_I2S_Start(IP_I2S_001_T *pI2S, uint8_t TRMode);
371
378 void IP_I2S_Pause(IP_I2S_001_T *pI2S, uint8_t TRMode);
379
386 STATIC INLINE void IP_I2S_EnableMute(IP_I2S_001_T *pI2S)
387 {
388 pI2S->DAO |= I2S_DAO_MUTE;
389 }
390
395 STATIC INLINE void IP_I2S_DisableMute(IP_I2S_001_T *pI2S)
396 {
397 pI2S->DAO &= ~I2S_DAO_MUTE;
398 }
399
407 void IP_I2S_Stop(IP_I2S_001_T *pI2S, uint8_t TRMode);
408
409 /**********************************************************************************
410 * I2S DMA functions
411 *********************************************************************************/
412
424 void IP_I2S_SetFIFODepthDMA(IP_I2S_001_T *pI2S, uint8_t TRMode, IP_I2S_DMARequestNumber_T DMANum, uint32_t depth);
425
436 void IP_I2S_DMACmd(IP_I2S_001_T *pI2S, IP_I2S_DMARequestNumber_T DMANum, uint8_t TRMode, FunctionalState NewState);
437
438 /**********************************************************************************
439 * I2S IRQ functions
440 *********************************************************************************/
441
450 void IP_I2S_InterruptCmd(IP_I2S_001_T *pI2S, uint8_t TRMode, FunctionalState NewState);
451
459 void IP_I2S_SetFIFODepthIRQ(IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t depth);
460
467 Status IP_I2S_GetIntStatus(IP_I2S_001_T *pI2S, uint8_t TRMode);
468
473 #ifdef __cplusplus
474 }
475 #endif
476
477 #endif /* __I2S_001_H_ */