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cmsis.h
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1 /*
2 * @brief Basic CMSIS include file
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __CMSIS_H_
33 #define __CMSIS_H_
34
35 #include "lpc_types.h"
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
46 #if defined(__ARMCC_VERSION)
47 // Kill warning "#pragma push with no matching #pragma pop"
48 #pragma diag_suppress 2525
49 #pragma push
50 #pragma anon_unions
51 #elif defined(__CWCC__)
52 #pragma push
53 #pragma cpp_extensions on
54 #elif defined(__GNUC__)
55 /* anonymous unions are enabled by default */
56 #elif defined(__IAR_SYSTEMS_ICC__)
57 // #pragma push // FIXME not usable for IAR
58 #pragma language=extended
59 #else
60 #error Not supported compiler type
61 #endif
62
63 #if defined(CORE_M4)
64
68 #define __CM4_REV 0x0000
69 #define __MPU_PRESENT 1
70 #define __NVIC_PRIO_BITS 3
71 #define __Vendor_SysTickConfig 0
72 #ifdef CHIP_LPC43XX
73 #define __FPU_PRESENT 1
74 #else
75 #define __FPU_PRESENT 0
76 #endif
77
86 typedef enum {
87 /* ------------------------- Cortex-M4 Processor Exceptions Numbers ----------------------------- */
88 Reset_IRQn = -15,
89 NonMaskableInt_IRQn = -14,
90 HardFault_IRQn = -13,
91 MemoryManagement_IRQn = -12,
92 BusFault_IRQn = -11,
93 UsageFault_IRQn = -10,
94 SVCall_IRQn = -5,
95 DebugMonitor_IRQn = -4,
96 PendSV_IRQn = -2,
97 SysTick_IRQn = -1,
99 /* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */
100 DAC_IRQn = 0,
101 M0CORE_IRQn = 1,
102 DMA_IRQn = 2,
103 RESERVED1_IRQn = 3,
104 RESERVED2_IRQn = 4,
105 ETHERNET_IRQn = 5,
106 SDIO_IRQn = 6,
107 LCD_IRQn = 7,
108 USB0_IRQn = 8,
109 USB1_IRQn = 9,
110 SCT_IRQn = 10,
111 RITIMER_IRQn = 11,
112 TIMER0_IRQn = 12,
113 TIMER1_IRQn = 13,
114 TIMER2_IRQn = 14,
115 TIMER3_IRQn = 15,
116 MCPWM_IRQn = 16,
117 ADC0_IRQn = 17,
118 I2C0_IRQn = 18,
119 I2C1_IRQn = 19,
120 SPI_INT_IRQn = 20,
121 ADC1_IRQn = 21,
122 SSP0_IRQn = 22,
123 SSP1_IRQn = 23,
124 USART0_IRQn = 24,
125 UART1_IRQn = 25,
126 USART2_IRQn = 26,
127 USART3_IRQn = 27,
128 I2S0_IRQn = 28,
129 I2S1_IRQn = 29,
130 RESERVED4_IRQn = 30,
131 SGPIO_INT_IRQn = 31,
132 PIN_INT0_IRQn = 32,
133 PIN_INT1_IRQn = 33,
134 PIN_INT2_IRQn = 34,
135 PIN_INT3_IRQn = 35,
136 PIN_INT4_IRQn = 36,
137 PIN_INT5_IRQn = 37,
138 PIN_INT6_IRQn = 38,
139 PIN_INT7_IRQn = 39,
140 GINT0_IRQn = 40,
141 GINT1_IRQn = 41,
142 EVENTROUTER_IRQn = 42,
143 C_CAN1_IRQn = 43,
144 RESERVED6_IRQn = 44,
145 RESERVED7_IRQn = 45,
146 ATIMER_IRQn = 46,
147 RTC_IRQn = 47,
148 RESERVED8_IRQn = 48,
149 WWDT_IRQn = 49,
150 RESERVED9_IRQn = 50,
151 C_CAN0_IRQn = 51,
152 QEI_IRQn = 52,
153 } IRQn_Type;
154
159 #include "core_cm4.h"
161 #elif defined(CORE_M3)
162
166 #define __MPU_PRESENT 1
167 #define __NVIC_PRIO_BITS 3
168 #define __Vendor_SysTickConfig 0
169 #define __FPU_PRESENT 0
179 typedef enum {
180 /* ------------------------- Cortex-M3 Processor Exceptions Numbers ----------------------------- */
181 Reset_IRQn = -15,
182 NonMaskableInt_IRQn = -14,
183 HardFault_IRQn = -13,
184 MemoryManagement_IRQn = -12,
185 BusFault_IRQn = -11,
186 UsageFault_IRQn = -10,
187 SVCall_IRQn = -5,
188 DebugMonitor_IRQn = -4,
189 PendSV_IRQn = -2,
190 SysTick_IRQn = -1,
192 /* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */
193 DAC_IRQn = 0,
194 RESERVED0_IRQn = 1,
195 DMA_IRQn = 2,
196 RESERVED1_IRQn = 3,
197 RESERVED2_IRQn = 4,
198 ETHERNET_IRQn = 5,
199 SDIO_IRQn = 6,
200 LCD_IRQn = 7,
201 USB0_IRQn = 8,
202 USB1_IRQn = 9,
203 SCT_IRQn = 10,
204 RITIMER_IRQn = 11,
205 TIMER0_IRQn = 12,
206 TIMER1_IRQn = 13,
207 TIMER2_IRQn = 14,
208 TIMER3_IRQn = 15,
209 MCPWM_IRQn = 16,
210 ADC0_IRQn = 17,
211 I2C0_IRQn = 18,
212 I2C1_IRQn = 19,
213 RESERVED3_IRQn = 20,
214 ADC1_IRQn = 21,
215 SSP0_IRQn = 22,
216 SSP1_IRQn = 23,
217 USART0_IRQn = 24,
218 UART1_IRQn = 25,
219 USART2_IRQn = 26,
220 USART3_IRQn = 27,
221 I2S0_IRQn = 28,
222 I2S1_IRQn = 29,
223 RESERVED4_IRQn = 30,
224 RESERVED5_IRQn = 31,
225 PIN_INT0_IRQn = 32,
226 PIN_INT1_IRQn = 33,
227 PIN_INT2_IRQn = 34,
228 PIN_INT3_IRQn = 35,
229 PIN_INT4_IRQn = 36,
230 PIN_INT5_IRQn = 37,
231 PIN_INT6_IRQn = 38,
232 PIN_INT7_IRQn = 39,
233 GINT0_IRQn = 40,
234 GINT1_IRQn = 41,
235 EVENTROUTER_IRQn = 42,
236 C_CAN1_IRQn = 43,
237 RESERVED6_IRQn = 44,
238 RESERVED7_IRQn = 45,
239 ATIMER_IRQn = 46,
240 RTC_IRQn = 47,
241 RESERVED8_IRQn = 48,
242 WWDT_IRQn = 49,
243 RESERVED9_IRQn = 50,
244 C_CAN0_IRQn = 51,
245 QEI_IRQn = 52,
246 } IRQn_Type;
247
252 #include "core_cm3.h"
254 #elif defined(CORE_M0)
255
259 #define __MPU_PRESENT 0
260 #define __NVIC_PRIO_BITS 2
261 #define __Vendor_SysTickConfig 0
262 #define __FPU_PRESENT 0
272 typedef enum {
273 /* ------------------------- Cortex-M0 Processor Exceptions Numbers ----------------------------- */
274 Reset_IRQn = -15,
275 NonMaskableInt_IRQn = -14,
276 HardFault_IRQn = -13,
277 SVCall_IRQn = -5,
278 DebugMonitor_IRQn = -4,
279 PendSV_IRQn = -2,
280 SysTick_IRQn = -1,
282 /* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */
283 DAC_IRQn = 0,
284 M0_M4CORE_IRQn = 1,
285 DMA_IRQn = 2,
286 RESERVED1_IRQn = 3,
287 FLASHEEPROM_IRQn = 4,
288 ETHERNET_IRQn = 5,
289 SDIO_IRQn = 6,
290 LCD_IRQn = 7,
291 USB0_IRQn = 8,
292 USB1_IRQn = 9,
293 SCT_IRQn = 10,
294 RITIMER_IRQn = 11,
295 TIMER0_IRQn = 12,
296 GINT1_IRQn = 13,
297 PIN_INT4_IRQn = 14,
298 TIMER3_IRQn = 15,
299 MCPWM_IRQn = 16,
300 ADC0_IRQn = 17,
301 I2C0_IRQn = 18,
302 SGPIO_INT_IRQn = 19,
303 SPI_INT_IRQn = 20,
304 ADC1_IRQn = 21,
305 SSP0_IRQn = 22,
306 EVENTROUTER_IRQn = 23,
307 USART0_IRQn = 24,
308 UART1_IRQn = 25,
309 USART2_IRQn = 26,
310 USART3_IRQn = 27,
311 I2S0_IRQn = 28,
312 C_CAN0_IRQn = 29,
313 I2S1_IRQn = 29,
314 RESERVED2_IRQn = 30,
315 RESERVED3_IRQn = 31,
316 } IRQn_Type;
317
322 #include "core_cm0.h"
323 #else
324 #error Please #define CORE_M0, CORE_M3, or CORE_M4
325 #endif
326
331 #ifdef __cplusplus
332 }
333 #endif
334
335 #endif /* __CMSIS_H_ */