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scu_18xx_43xx.h
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1 /*
2 * Copyright(C) NXP Semiconductors, 2012
3 * All rights reserved.
4 *
5 * Software that is described herein is for illustrative purposes only
6 * which provides customers with programming information regarding the
7 * LPC products. This software is supplied "AS IS" without any warranties of
8 * any kind, and NXP Semiconductors and its licensor disclaim any and
9 * all warranties, express or implied, including all implied warranties of
10 * merchantability, fitness for a particular purpose and non-infringement of
11 * intellectual property rights. NXP Semiconductors assumes no responsibility
12 * or liability for the use of the software, conveys no license or rights under any
13 * patent, copyright, mask work right, or any other intellectual property rights in
14 * or to any products. NXP Semiconductors reserves the right to make changes
15 * in the software without notification. NXP Semiconductors also makes no
16 * representation or warranty that such application will be suitable for the
17 * specified use without further testing or modification.
18 *
19 * Permission to use, copy, modify, and distribute this software and its
20 * documentation is hereby granted, under NXP Semiconductors' and its
21 * licensor's relevant copyrights in the software, without fee, provided that it
22 * is used in conjunction with NXP Semiconductors microcontrollers. This
23 * copyright, permission, and disclaimer notice must appear in all copies of
24 * this code.
25 */
26
27 #ifndef __SCU_18XX_43XX_H_
28 #define __SCU_18XX_43XX_H_
29
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33
42 typedef struct {
43 __IO uint32_t SFSP[16][32];
44 __I uint32_t RESERVED0[256];
45 __IO uint32_t SFSCLK[4];
46 __I uint32_t RESERVED16[28];
47 __IO uint32_t SFSUSB;
48 __IO uint32_t SFSI2C0;
49 __IO uint32_t ENAIO[3];
50 __I uint32_t RESERVED17[27];
51 __IO uint32_t EMCDELAYCLK;
52 __I uint32_t RESERVED18[63];
53 __IO uint32_t PINTSEL0;
54 __IO uint32_t PINTSEL1;
55 } LPC_SCU_T;
56
62 #define SCU_MODE_MODE_INACT (0x0 << 3)
63 #define SCU_MODE_MODE_PULLDOWN (0x1 << 3)
64 #define SCU_MODE_MODE_PULLUP (0x2 << 3)
65 #define SCU_MODE_MODE_REPEATER (0x3 << 3)
66 #define SCU_MODE_HIGHSPEEDSLEW_EN (0x1 << 5)
67 #define SCU_MODE_INBUFF_EN (0x1 << 6)
68 #define SCU_MODE_ZIF_DIS (0x1 << 7)
69 #define SCU_MODE_4MA_DRIVESTR (0x0 << 8)
70 #define SCU_MODE_8MA_DRIVESTR (0x1 << 8)
71 #define SCU_MODE_14MA_DRIVESTR (0x2 << 8)
72 #define SCU_MODE_20MA_DRIVESTR (0x3 << 8)
73 #define SCU_MODE_FUNC0 0x0
74 #define SCU_MODE_FUNC1 0x1
75 #define SCU_MODE_FUNC2 0x2
76 #define SCU_MODE_FUNC3 0x3
77 #define SCU_MODE_FUNC4 0x4
78 #define SCU_MODE_FUNC5 0x5
79 #define SCU_MODE_FUNC6 0x6
80 #define SCU_MODE_FUNC7 0x7
81 #define SCU_PINIO_FAST (SCU_MODE_MODE_PULLUP | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS)
82
87 #define MD_PUP (0x0 << 3)
88 #define MD_BUK (0x1 << 3)
89 #define MD_PLN (0x2 << 3)
90 #define MD_PDN (0x3 << 3)
91 #define MD_EHS (0x1 << 5)
92 #define MD_EZI (0x1 << 6)
93 #define MD_ZI (0x1 << 7)
94 #define MD_EHD0 (0x1 << 8)
95 #define MD_EHD1 (0x1 << 8)
96 #define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
97 #define I2C0_STANDARD_FAST_MODE (1 << 3 | 1 << 11)
98 #define I2C0_FAST_MODE_PLUS (2 << 1 | 1 << 3 | 1 << 7 | 1 << 10 | 1 << 11)
99 #define FUNC0 0x0
100 #define FUNC1 0x1
101 #define FUNC2 0x2
102 #define FUNC3 0x3
103 #define FUNC4 0x4
104 #define FUNC5 0x5
105 #define FUNC6 0x6
106 #define FUNC7 0x7
108 #define PORT_OFFSET 0x80
109 #define PIN_OFFSET 0x04
112 #define LPC_SCU_PIN(LPC_SCU_BASE, po, pi) (*(volatile int *) ((LPC_SCU_BASE) + ((po) * 0x80) + ((pi) * 0x4))
113
115 #define LPC_SCU_CLK(LPC_SCU_BASE, c) (*(volatile int *) ((LPC_SCU_BASE) +0xC00 + ((c) * 0x4)))
116
126 STATIC INLINE void Chip_SCU_PinMuxSet(uint8_t port, uint8_t pin, uint16_t modefunc)
127 {
128 LPC_SCU->SFSP[port][pin] = modefunc;
129 }
130
141 STATIC INLINE void Chip_SCU_PinMux(uint8_t port, uint8_t pin, uint16_t mode, uint8_t func)
142 {
143 Chip_SCU_PinMuxSet(port, pin, (mode | (uint16_t) func));
144 }
145
152 STATIC INLINE void Chip_SCU_ClockPinMuxSet(uint8_t clknum, uint16_t modefunc)
153 {
154 LPC_SCU->SFSCLK[clknum] = (uint32_t) modefunc;
155 }
156
164 STATIC INLINE void Chip_SCU_ClockPinMux(uint8_t clknum, uint16_t mode, uint8_t func)
165 {
166 LPC_SCU->SFSCLK[clknum] = ((uint32_t) mode | (uint32_t) func);
167 }
168
176 void Chip_SCU_GPIOIntPinSel(uint8_t PortSel, uint8_t PortNum, uint8_t PinNum);
177
185 STATIC INLINE void Chip_SCU_I2C0PinConfig(uint32_t I2C0Mode)
186 {
187 LPC_SCU->SFSI2C0 = I2C0Mode;
188 }
189
196 STATIC INLINE void Chip_SCU_ADC_Channel_Config(uint32_t ADC_ID, uint8_t channel)
197 {
198 LPC_SCU->ENAIO[ADC_ID] |= 1UL << channel;
199 }
200
205 STATIC INLINE void Chip_SCU_DAC_Analog_Config(void)
206 {
207 /*Enable analog function DAC on pin P4_4*/
208 LPC_SCU->ENAIO[2] |= 1;
209 }
210
215 #ifdef __cplusplus
216 }
217 #endif
218
219 #endif /* __SCU_18XX_43XX_H_ */