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clock_11xx.h
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1 /*
2 * @brief LPC11XX Clock control functions
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __CLOCK_11XX_H_
33 #define __CLOCK_11XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
62 #define SYSCTL_IRC_FREQ (12000000)
63
71 STATIC INLINE void Chip_Clock_SetupSystemPLL(uint8_t msel, uint8_t psel)
72 {
73 LPC_SYSCTL->SYSPLLCTRL = (msel & 0x1F) | ((psel & 0x3) << 5);
74 }
75
80 STATIC INLINE bool Chip_Clock_IsSystemPLLLocked(void)
81 {
82 return (bool) ((LPC_SYSCTL->SYSPLLSTAT & 1) != 0);
83 }
84
88 typedef enum CHIP_SYSCTL_PLLCLKSRC {
89 SYSCTL_PLLCLKSRC_IRC = 0,
90 SYSCTL_PLLCLKSRC_MAINOSC,
91 #if defined(CHIP_LPC11AXX)
92 SYSCTL_PLLCLKSRC_EXT_CLKIN,
93 #else
94 SYSCTL_PLLCLKSRC_RESERVED1,
95 #endif
96 SYSCTL_PLLCLKSRC_RESERVED2,
97 } CHIP_SYSCTL_PLLCLKSRC_T;
98
106 void Chip_Clock_SetSystemPllSource(CHIP_SYSCTL_PLLCLKSRC_T src);
107
108 #if defined(CHIP_LPC11UXX)
109
116 STATIC INLINE void Chip_Clock_SetupUSBPLL(uint8_t msel, uint8_t psel)
117 {
118 LPC_SYSCTL->USBPLLCTRL = (msel & 0x1F) | ((psel & 0x3) << 5);
119 }
120
125 STATIC INLINE bool Chip_Clock_IsUSBPLLLocked(void)
126 {
127 return (bool) ((LPC_SYSCTL->USBPLLSTAT & 1) != 0);
128 }
129
137 void Chip_Clock_SetUSBPllSource(CHIP_SYSCTL_PLLCLKSRC_T src);
138
139 #endif /*defined(CHIP_LPC11UXX)*/
140
150 void Chip_Clock_SetPLLBypass(bool bypass, bool highfr);
151
155 typedef enum CHIP_WDTLFO_OSC {
156 WDTLFO_OSC_ILLEGAL,
157 WDTLFO_OSC_0_60,
158 WDTLFO_OSC_1_05,
159 WDTLFO_OSC_1_40,
160 WDTLFO_OSC_1_75,
161 WDTLFO_OSC_2_10,
162 WDTLFO_OSC_2_40,
163 WDTLFO_OSC_2_70,
164 WDTLFO_OSC_3_00,
165 WDTLFO_OSC_3_25,
166 WDTLFO_OSC_3_50,
167 WDTLFO_OSC_3_75,
168 WDTLFO_OSC_4_00,
169 WDTLFO_OSC_4_20,
170 WDTLFO_OSC_4_40,
171 WDTLFO_OSC_4_60
172 } CHIP_WDTLFO_OSC_T;
173
181 STATIC INLINE void Chip_Clock_SetWDTOSC(CHIP_WDTLFO_OSC_T wdtclk, uint8_t div)
182 {
183 LPC_SYSCTL->WDTOSCCTRL = (((uint32_t) wdtclk) << 5) | ((div >> 1) - 1);
184 }
185
186 #if defined(CHIP_LPC11AXX)
187
194 STATIC INLINE void Chip_Clock_SetLFOSC(CHIP_WDTLFO_OSC_T lfoclk, uint8_t div)
195 {
196 LPC_SYSCTL->LFOSCCTRL = (((uint32_t) lfoclk) << 5) | ((div >> 1) - 1);
197 }
198
199 #endif /*CHIP_LPC11AXX*/
200
204 typedef enum CHIP_SYSCTL_MAINCLKSRC {
205 SYSCTL_MAINCLKSRC_IRC = 0,
206 SYSCTL_MAINCLKSRC_PLLIN,
207 SYSCTL_MAINCLKSRC_LFOSC,
208 SYSCTL_MAINCLKSRC_WDTOSC = SYSCTL_MAINCLKSRC_LFOSC,
209 SYSCTL_MAINCLKSRC_PLLOUT,
210 } CHIP_SYSCTL_MAINCLKSRC_T;
211
219 void Chip_Clock_SetMainClockSource(CHIP_SYSCTL_MAINCLKSRC_T src);
220
225 STATIC INLINE CHIP_SYSCTL_MAINCLKSRC_T Chip_Clock_GetMainClockSource(void)
226 {
227 return (CHIP_SYSCTL_MAINCLKSRC_T) (LPC_SYSCTL->MAINCLKSEL);
228 }
229
237 STATIC INLINE void Chip_Clock_SetSysClockDiv(uint32_t div)
238 {
239 LPC_SYSCTL->SYSAHBCLKDIV = div;
240 }
241
245 typedef enum CHIP_SYSCTL_CLOCK {
246 SYSCTL_CLOCK_SYS = 0,
247 SYSCTL_CLOCK_ROM,
248 SYSCTL_CLOCK_RAM,
249 SYSCTL_CLOCK_FLASHREG,
250 SYSCTL_CLOCK_FLASHARRAY,
251 #if defined(CHIP_LPC110X)
252 SYSCTL_CLOCK_RESERVED5,
253 #else
254 SYSCTL_CLOCK_I2C,
255 #endif
256 SYSCTL_CLOCK_GPIO,
257 SYSCTL_CLOCK_CT16B0,
258 SYSCTL_CLOCK_CT16B1,
259 SYSCTL_CLOCK_CT32B0,
260 SYSCTL_CLOCK_CT32B1,
261 SYSCTL_CLOCK_SSP0,
262 SYSCTL_CLOCK_UART0,
263 SYSCTL_CLOCK_ADC,
264 #if defined(CHIP_LPC11UXX)
265 SYSCTL_CLOCK_USB,
266 #else
267 SYSCTL_CLOCK_RESERVED14,
268 #endif
269 SYSCTL_CLOCK_WDT,
270 SYSCTL_CLOCK_IOCON,
271 #if defined(CHIP_LPC11CXX)
272 SYSCTL_CLOCK_CAN,
273 #else
274 SYSCTL_CLOCK_RESERVED17,
275 #endif
276 #if !(defined(CHIP_LPC110X) || defined(CHIP_LPC11XXLV))
277 SYSCTL_CLOCK_SSP1,
278 #if !defined(CHIP_LPC11CXX)
279 SYSCTL_CLOCK_PINT,
280 #if defined(CHIP_LPC11AXX)
281 SYSCTL_CLOCK_ACOMP,
282 SYSCTL_CLOCK_DAC,
283 #else
284 SYSCTL_CLOCK_RESERVED20,
285 SYSCTL_CLOCK_RESERVED21,
286 #endif
287 SYSCTL_CLOCK_RESERVED22,
288 SYSCTL_CLOCK_P0INT,
289 SYSCTL_CLOCK_GROUP0INT = SYSCTL_CLOCK_P0INT,
290 SYSCTL_CLOCK_P1INT,
291 SYSCTL_CLOCK_GROUP1INT = SYSCTL_CLOCK_P1INT,
292 SYSCTL_CLOCK_RESERVED25,
293 #if defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
294 SYSCTL_CLOCK_RAM1,
295 #else
296 SYSCTL_CLOCK_RESERVED26,
297 #endif
298 #if defined(CHIP_LPC11UXX)
299 SYSCTL_CLOCK_USBRAM,
300 #else
301 SYSCTL_CLOCK_RESERVED27,
302 #endif
303 #endif /* !defined(CHIP_LPC11CXX) */
304 #endif /* !(defined(CHIP_LPC110X) || defined(CHIP_LPC11XXLV)) */
305 } CHIP_SYSCTL_CLOCK_T;
306
312 STATIC INLINE void Chip_Clock_EnablePeriphClock(CHIP_SYSCTL_CLOCK_T clk)
313 {
314 LPC_SYSCTL->SYSAHBCLKCTRL |= (1 << clk);
315 }
316
322 STATIC INLINE void Chip_Clock_DisablePeriphClock(CHIP_SYSCTL_CLOCK_T clk)
323 {
324 LPC_SYSCTL->SYSAHBCLKCTRL &= ~(1 << clk);
325 }
326
334 STATIC INLINE void Chip_Clock_SetSSP0ClockDiv(uint32_t div)
335 {
336 LPC_SYSCTL->SSP0CLKDIV = div;
337 }
338
344 STATIC INLINE uint32_t Chip_Clock_GetSSP0ClockDiv(void)
345 {
346 return LPC_SYSCTL->SSP0CLKDIV;
347 }
348
356 STATIC INLINE void Chip_Clock_SetUARTClockDiv(uint32_t div)
357 {
358 LPC_SYSCTL->USARTCLKDIV = div;
359 }
360
366 STATIC INLINE uint32_t Chip_Clock_GetUARTClockDiv(void)
367 {
368 return LPC_SYSCTL->USARTCLKDIV;
369 }
370
371 #if defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11AXX) || defined(CHIP_LPC11UXX)
372
379 STATIC INLINE void Chip_Clock_SetSSP1ClockDiv(uint32_t div)
380 {
381 LPC_SYSCTL->SSP1CLKDIV = div;
382 }
383
389 STATIC INLINE uint32_t Chip_Clock_GetSSP1ClockDiv(void)
390 {
391 return LPC_SYSCTL->SSP1CLKDIV;
392 }
393
394 #endif /*defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11AXX) || defined(CHIP_LPC11UXX)*/
395
396 #if defined(CHIP_LPC11UXX)
397
400 typedef enum CHIP_SYSCTL_USBCLKSRC{
401 SYSCTL_USBCLKSRC_PLLOUT = 0,
402 SYSCTL_USBCLKSRC_MAINSYSCLK,
403 } CHIP_SYSCTL_USBCLKSRC_T;
404
415 void Chip_Clock_SetUSBClockSource(CHIP_SYSCTL_USBCLKSRC_T src, uint32_t div);
416
417 #endif /*CHIP_LPC11UXX*/
418
419 #if defined(CHIP_LPC110X) || defined(CHIP_LPC11XXLV) || defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX)
420
423 typedef enum CHIP_SYSCTL_WDTCLKSRC{
424 SYSCTL_WDTCLKSRC_IRC = 0,
425 SYSCTL_WDTCLKSRC_MAINSYSCLK,
426 SYSCTL_WDTCLKSRC_WDTOSC,
427 } CHIP_SYSCTL_WDTCLKSRC_T;
428
439 void Chip_Clock_SetWDTClockSource(CHIP_SYSCTL_WDTCLKSRC_T src, uint32_t div);
440
441 #endif
442
443 #if !defined(CHIP_LPC110X)
444
447 typedef enum CHIP_SYSCTL_CLKOUTSRC{
448 SYSCTL_CLKOUTSRC_IRC = 0,
449 SYSCTL_CLKOUTSRC_MAINOSC,
450 SYSCTL_CLKOUTSRC_WDTOSC,
451 SYSCTL_CLKOUTSRC_LFOSC = SYSCTL_CLKOUTSRC_WDTOSC,
452 SYSCTL_CLKOUTSRC_MAINSYSCLK,
453 } CHIP_SYSCTL_CLKOUTSRC_T;
454
465 void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div);
466
467 #endif
468
473 STATIC INLINE uint32_t Chip_Clock_GetMainOscRate(void)
474 {
475 return CRYSTAL_MAIN_FREQ_IN;
476 }
477
482 STATIC INLINE uint32_t Chip_Clock_GetIntOscRate(void)
483 {
484 return SYSCTL_IRC_FREQ;
485 }
486
487 #if defined(CHIP_LPC11AXX)
488
493 STATIC INLINE uint32_t Chip_Clock_GetExtClockInRate(void)
494 {
495 return EXTCLKIN_FREQ_IN;
496 }
497
498 #endif
499
505 uint32_t Chip_Clock_GetWDTOSCRate(void);
506
507 #if defined(CHIP_LPC11AXX)
508
513 uint32_t Chip_Clock_GetLFOOSCRate(void);
514
515 #endif
516
521 uint32_t Chip_Clock_GetSystemPllInClockRate(void);
522
527 uint32_t Chip_Clock_GetSystemPllOutClockRate(void);
528
529 #if defined(CHIP_LPC11UXX)
530
534 uint32_t Chip_Clock_GetUSBPllInClockRate(void);
535
540 uint32_t Chip_Clock_GetUSBPllOutClockRate(void);
541
542 #endif
543
548 uint32_t Chip_Clock_GetMainClockRate(void);
549
554 uint32_t Chip_Clock_GetSystemClockRate(void);
555
560 #ifdef __cplusplus
561 }
562 #endif
563
564 #endif /* __CLOCK_11XX_H_ */