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ssp_001.h
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1 /*
2 * @brief SSP Registers and control functions
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __SSP_001_H_
33 #define __SSP_001_H_
34
35 #include "sys_config.h"
36 #include "cmsis.h"
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
50 typedef struct {
51 __IO uint32_t CR0;
52 __IO uint32_t CR1;
53 __IO uint32_t DR;
54 __I uint32_t SR;
55 __IO uint32_t CPSR;
56 __IO uint32_t IMSC;
57 __I uint32_t RIS;
58 __I uint32_t MIS;
59 __O uint32_t ICR;
60 #if !defined(CHIP_LPC110X) && !defined(CHIP_LPC11XXLV) && !defined(CHIP_LPC11AXX) && \
61 !defined(CHIP_LPC11CXX) && !defined(CHIP_LPC11EXX) && !defined(CHIP_LPC11UXX)
62 __IO uint32_t DMACR;
63 #endif
64 } IP_SSP_001_T;
65
71 #define SSP_CR0_DSS(n) ((uint32_t) ((n) & 0xF))
72
73 #define SSP_CR0_FRF_SPI ((uint32_t) (0 << 4))
74
75 #define SSP_CR0_FRF_TI ((uint32_t) (1 << 4))
76
77 #define SSP_CR0_FRF_MICROWIRE ((uint32_t) (2 << 4))
78
80 #define SSP_CR0_CPOL_LO ((uint32_t) (0))
81 #define SSP_CR0_CPOL_HI ((uint32_t) (1 << 6))
82
84 #define SSP_CR0_CPHA_FIRST ((uint32_t) (0))
85 #define SSP_CR0_CPHA_SECOND ((uint32_t) (1 << 7))
86
88 #define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8))
89
90 #define SSP_CR0_BITMASK ((uint32_t) (0xFFFF))
91
92 #define SSP_CR0_BITMASK ((uint32_t) (0xFFFF))
93
95 #define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8))
96
102 #define SSP_CR1_LBM_EN ((uint32_t) (1 << 0))
103
104 #define SSP_CR1_SSP_EN ((uint32_t) (1 << 1))
105
106 #define SSP_CR1_SLAVE_EN ((uint32_t) (1 << 2))
107 #define SSP_CR1_MASTER_EN ((uint32_t) (0))
108
110 #define SSP_CR1_SO_DISABLE ((uint32_t) (1 << 3))
111
112 #define SSP_CR1_BITMASK ((uint32_t) (0x0F))
113
115 #define SSP_CPSR_BITMASK ((uint32_t) (0xFF))
116
121 #define SSP_DR_BITMASK(n) ((n) & 0xFFFF)
122
128 #define SSP_SR_BITMASK ((uint32_t) (0x1F))
129
131 #define SSP_ICR_BITMASK ((uint32_t) (0x03))
132
136 typedef enum IP_SSP_STATUS {
137 SSP_STAT_TFE = ((uint32_t)(1 << 0)),
138 SSP_STAT_TNF = ((uint32_t)(1 << 1)),
139 SSP_STAT_RNE = ((uint32_t)(1 << 2)),
140 SSP_STAT_RFF = ((uint32_t)(1 << 3)),
141 SSP_STAT_BSY = ((uint32_t)(1 << 4)),
142 } IP_SSP_STATUS_T;
143
147 typedef enum IP_SSP_INTMASK {
148 SSP_RORIM = ((uint32_t)(1 << 0)),
149 SSP_RTIM = ((uint32_t)(1 << 1)),
150 SSP_RXIM = ((uint32_t)(1 << 2)),
151 SSP_TXIM = ((uint32_t)(1 << 3)),
152 SSP_INT_MASK_BITMASK = ((uint32_t)(0xF)),
153 } IP_SSP_INTMASK_T;
154
158 typedef enum IP_SSP_MASKINTSTATUS {
159 SSP_RORMIS = ((uint32_t)(1 << 0)),
160 SSP_RTMIS = ((uint32_t)(1 << 1)),
161 SSP_RXMIS = ((uint32_t)(1 << 2)),
162 SSP_TXMIS = ((uint32_t)(1 << 3)),
163 SSP_MASK_INT_STAT_BITMASK = ((uint32_t)(0xF)),
164 } IP_SSP_MASKINTSTATUS_T;
165
169 typedef enum IP_SSP_RAWINTSTATUS {
170 SSP_RORRIS = ((uint32_t)(1 << 0)),
171 SSP_RTRIS = ((uint32_t)(1 << 1)),
172 SSP_RXRIS = ((uint32_t)(1 << 2)),
173 SSP_TXRIS = ((uint32_t)(1 << 3)),
174 SSP_RAW_INT_STAT_BITMASK = ((uint32_t)(0xF)),
175 } IP_SSP_RAWINTSTATUS_T;
176
177 typedef enum IP_SSP_INTCLEAR {
178 SSP_RORIC = 0x0,
179 SSP_RTIC = 0x1,
180 SSP_INT_CLEAR_BITMASK = 0x3,
181 } IP_SSP_INTCLEAR_T;
182
183 typedef enum IP_SSP_DMA {
184 SSP_DMA_RX = (1u),
185 SSP_DMA_TX = (1u << 1),
186 SSP_DMA_BITMASK = ((uint32_t)(0x3)),
187 } IP_SSP_DMA_T;
188
195 STATIC INLINE void IP_SSP_DeInit(IP_SSP_001_T *pSSP)
196 {
197 pSSP->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;
198 }
199
205 STATIC INLINE void IP_SSP_Enable(IP_SSP_001_T *pSSP)
206 {
207 pSSP->CR1 |= SSP_CR1_SSP_EN;
208 }
209
215 STATIC INLINE void IP_SSP_Disable(IP_SSP_001_T *pSSP)
216 {
217 pSSP->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;
218 }
219
227 STATIC INLINE void IP_SSP_EnableLoopBack(IP_SSP_001_T *pSSP)
228 {
229 pSSP->CR1 |= SSP_CR1_LBM_EN;
230 }
231
239 STATIC INLINE void IP_SSP_DisableLoopBack(IP_SSP_001_T *pSSP)
240 {
241 pSSP->CR1 &= (~SSP_CR1_LBM_EN) & SSP_CR1_BITMASK;
242 }
243
255 STATIC INLINE FlagStatus IP_SSP_GetStatus(IP_SSP_001_T *pSSP, IP_SSP_STATUS_T Stat)
256 {
257 return (pSSP->SR & Stat) ? SET : RESET;
258 }
259
266 STATIC INLINE uint32_t IP_SSP_GetIntStatus(IP_SSP_001_T *pSSP)
267 {
268 return pSSP->MIS;
269 }
270
282 STATIC INLINE IntStatus IP_SSP_GetRawIntStatus(IP_SSP_001_T *pSSP, IP_SSP_RAWINTSTATUS_T RawInt)
283 {
284 return (pSSP->RIS & RawInt) ? SET : RESET;
285 }
286
293 STATIC INLINE uint8_t IP_SSP_GetDataSize(IP_SSP_001_T *pSSP)
294 {
295 return SSP_CR0_DSS(pSSP->CR0);
296 }
297
307 STATIC INLINE void IP_SSP_ClearIntPending(IP_SSP_001_T *pSSP, IP_SSP_INTCLEAR_T IntClear)
308 {
309 pSSP->ICR = IntClear;
310 }
311
322 STATIC INLINE void IP_SSP_Int_Enable(IP_SSP_001_T *pSSP, IP_SSP_INTMASK_T IntType)
323 {
324 pSSP->IMSC |= IntType;
325 }
326
337 STATIC INLINE void IP_SSP_Int_Disable(IP_SSP_001_T *pSSP, IP_SSP_INTMASK_T IntType)
338 {
339 pSSP->IMSC &= (~IntType);
340 }
341
347 STATIC INLINE uint16_t IP_SSP_ReceiveFrame(IP_SSP_001_T *pSSP)
348 {
349 return (uint16_t) (SSP_DR_BITMASK(pSSP->DR));
350 }
351
358 STATIC INLINE void IP_SSP_SendFrame(IP_SSP_001_T *pSSP, uint16_t tx_data)
359 {
360 pSSP->DR = SSP_DR_BITMASK(tx_data);
361 }
362
371 void IP_SSP_Set_ClockRate(IP_SSP_001_T *pSSP, uint32_t clk_rate, uint32_t prescale);
372
389 STATIC INLINE void IP_SSP_SetFormat(IP_SSP_001_T *pSSP, uint32_t bits, uint32_t frameFormat, uint32_t clockMode)
390 {
391 pSSP->CR0 = (pSSP->CR0 & ~0xFF) | bits | frameFormat | clockMode;
392 }
393
402 STATIC INLINE void IP_SSP_Set_Mode(IP_SSP_001_T *pSSP, uint32_t mode)
403 {
404 pSSP->CR1 = (pSSP->CR1 & ~(1 << 2)) | mode;
405 }
406
407 #if !defined(CHIP_LPC110X) && !defined(CHIP_LPC11XXLV) && !defined(CHIP_LPC11AXX) && \
408 !defined(CHIP_LPC11CXX) && !defined(CHIP_LPC11EXX) && !defined(CHIP_LPC11UXX)
409
417 STATIC INLINE void IP_SSP_DMA_Enable(IP_SSP_001_T *pSSP, IP_SSP_DMA_T flag)
418 {
419 pSSP->DMACR |= flag;
420 }
421
430 STATIC INLINE void IP_SSP_DMA_Disable(IP_SSP_001_T *pSSP, IP_SSP_DMA_T flag)
431 {
432 pSSP->DMACR &= ~flag;
433 }
434
435 #endif
436
441 #ifdef __cplusplus
442 }
443 #endif
444
445 #endif /* __SSP_001_H_ */