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sdc_001.h
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1 /*
2 * @brief SD Card Interface Registers and control functions
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __SDC_001_H_
33 #define __SDC_001_H_
34
35 #include "sys_config.h"
36 #include "cmsis.h"
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
51 typedef struct {
52 __IO uint32_t POWER;
53 __IO uint32_t CLOCK;
54 __IO uint32_t ARGUMENT;
55 __IO uint32_t COMMAND;
56 __I uint32_t RESPCMD;
57 __I uint32_t RESPONSE[4];
58 __IO uint32_t DATATIMER;
59 __IO uint32_t DATALENGTH;
60 __IO uint32_t DATACTRL;
61 __I uint32_t DATACNT;
62 __I uint32_t STATUS;
63 __O uint32_t CLEAR;
64 __IO uint32_t MASK0;
65 uint32_t RESERVED0[2];
66 __I uint32_t FIFOCNT;
67 uint32_t RESERVED1[13];
68 __IO uint32_t FIFO[16];
69 } IP_SDC_001_T;
70
75 #define SDC_PWR_BITMASK ((uint32_t) 0xC3)
76
77 #define SDC_PWR_CTRL_BITMASK (((uint32_t) 0x03) << 0)
78
79 #define SDC_PWR_CTRL(n) (((uint32_t) (n & 0x03)) << 0)
80
81 #define SDC_PWR_OPENDRAIN (((uint32_t) 1) << 6)
82
83 #define SDC_PWR_ROD (((uint32_t) 1) << 7)
84
89 #define SDC_CLOCK_BITMASK ((uint32_t) 0xFFF)
90
91 #define SDC_CLOCK_CLKDIV_BITMASK (((uint32_t) 0xFF ) << 0)
92
93 #define SDC_CLOCK_CLKDIV(n) (((uint32_t) (n & 0x0FF)) << 0)
94
99 #define SDC_COMMAND_BITMASK ((uint32_t) 0x7FF)
100
101 #define SDC_COMMAND_INDEX_BITMASK ((uint32_t) 0x3F)
102
103 #define SDC_COMMAND_INDEX(n) ((uint32_t) n & 0x3F)
104
105 #define SDC_COMMAND_NO_RSP (((uint32_t) 0 ) << 6)
106
107 #define SDC_COMMAND_SHORT_RSP (((uint32_t) 1 ) << 6)
108
109 #define SDC_COMMAND_LONG_RSP (((uint32_t) 3 ) << 6)
110
111 #define SDC_COMMAND_RSP_BITMASK (((uint32_t) 3 ) << 6)
112
113 #define SDC_COMMAND_INTERRUPT (((uint32_t) 1 ) << 8)
114
115 #define SDC_COMMAND_PENDING (((uint32_t) 1 ) << 9)
116
117 #define SDC_COMMAND_ENABLE (((uint32_t) 1 ) << 10)
118
123 #define SDC_RESPCOMMAND_VAL(n) ((uint32_t) n & 0x3F)
124
129 #define SDC_DATALENGTH_LEN(n) ((uint32_t) n & 0xFFFF)
130
135 #define SDC_DATACTRL_BITMASK ((uint32_t) 0xFF)
136
137 #define SDC_DATACTRL_ENABLE (((uint32_t) 1 ) << 0)
138
139 #define SDC_DATACTRL_DIR_FROMCARD (((uint32_t) 1 ) << 1)
140
141 #define SDC_DATACTRL_DIR_TOCARD ((uint32_t) 0)
142
143 #define SDC_DATACTRL_XFER_MODE_STREAM (((uint32_t) 1 ) << 2)
144
145 #define SDC_DATACTRL_XFER_MODE_BLOCK ((uint32_t) 0)
146
147 #define SDC_DATACTRL_DMA_ENABLE (((uint32_t) 1 ) << 3)
148
149 #define SDC_DATACTRL_BLOCKSIZE(n) (((uint32_t) (n & 0x0F) ) << 4)
150
151 #define SDC_DATACTRL_BLOCKSIZE_VAL(n) (((uint32_t) 1) << n)
152
156 #define SDC_DATACNT_VAL(n) ((uint32_t) n & 0xFFFF)
157
162 #define SDC_STATUS_CMDCRCFAIL (((uint32_t) 1 ) << 0)
163
164 #define SDC_STATUS_DATACRCFAIL (((uint32_t) 1 ) << 1)
165
166 #define SDC_STATUS_CMDTIMEOUT (((uint32_t) 1 ) << 2)
167
168 #define SDC_STATUS_DATATIMEOUT (((uint32_t) 1 ) << 3)
169
170 #define SDC_STATUS_TXUNDERRUN (((uint32_t) 1 ) << 4)
171
172 #define SDC_STATUS_RXOVERRUN (((uint32_t) 1 ) << 5)
173
174 #define SDC_STATUS_CMDRESPEND (((uint32_t) 1 ) << 6)
175
176 #define SDC_STATUS_CMDSENT (((uint32_t) 1 ) << 7)
177
178 #define SDC_STATUS_DATAEND (((uint32_t) 1 ) << 8)
179
180 #define SDC_STATUS_STARTBITERR (((uint32_t) 1 ) << 9)
181
182 #define SDC_STATUS_DATABLOCKEND (((uint32_t) 1 ) << 10)
183
184 #define SDC_STATUS_CMDACTIVE (((uint32_t) 1 ) << 11)
185
186 #define SDC_STATUS_TXACTIVE (((uint32_t) 1 ) << 12)
187
188 #define SDC_STATUS_RXACTIVE (((uint32_t) 1 ) << 13)
189
190 #define SDC_STATUS_TXFIFOHALFEMPTY (((uint32_t) 1 ) << 14)
191
192 #define SDC_STATUS_RXFIFOHALFFULL (((uint32_t) 1 ) << 15)
193
194 #define SDC_STATUS_TXFIFOFULL (((uint32_t) 1 ) << 16)
195
196 #define SDC_STATUS_RXFIFOFULL (((uint32_t) 1 ) << 17)
197
198 #define SDC_STATUS_TXFIFOEMPTY (((uint32_t) 1 ) << 18)
199
200 #define SDC_STATUS_RXFIFOEMPTY (((uint32_t) 1 ) << 19)
201
202 #define SDC_STATUS_TXDATAAVLBL (((uint32_t) 1 ) << 20)
203
204 #define SDC_STATUS_RXDATAAVLBL (((uint32_t) 1 ) << 21)
205
206 #define SDC_STATUS_CMDERR (SDC_STATUS_CMDCRCFAIL | SDC_STATUS_CMDTIMEOUT | SDC_STATUS_STARTBITERR)
207
208 #define SDC_STATUS_DATAERR (SDC_STATUS_DATACRCFAIL | SDC_STATUS_DATATIMEOUT | SDC_STATUS_TXUNDERRUN \
209 | SDC_STATUS_RXOVERRUN | SDC_STATUS_STARTBITERR)
210
211 #define SDC_STATUS_FIFO (SDC_STATUS_TXFIFOHALFEMPTY | SDC_STATUS_RXFIFOHALFFULL \
212 | SDC_STATUS_TXFIFOFULL | SDC_STATUS_RXFIFOFULL \
213 | SDC_STATUS_TXFIFOEMPTY | SDC_STATUS_RXFIFOEMPTY \
214 | SDC_STATUS_DATABLOCKEND)
215
217 #define SDC_STATUS_DATA (SDC_STATUS_DATAEND )
218
223 #define SDC_CLEAR_ALL ((uint32_t) 0x7FF)
224
225 #define SDC_CLEAR_CMDCRCFAIL (((uint32_t) 1 ) << 0)
226
227 #define SDC_CLEAR_DATACRCFAIL (((uint32_t) 1 ) << 1)
228
229 #define SDC_CLEAR_CMDTIMEOUT (((uint32_t) 1 ) << 2)
230
231 #define SDC_CLEAR_DATATIMEOUT (((uint32_t) 1 ) << 3)
232
233 #define SDC_CLEAR_TXUNDERRUN (((uint32_t) 1 ) << 4)
234
235 #define SDC_CLEAR_RXOVERRUN (((uint32_t) 1 ) << 5)
236
237 #define SDC_CLEAR_CMDRESPEND (((uint32_t) 1 ) << 6)
238
239 #define SDC_CLEAR_CMDSENT (((uint32_t) 1 ) << 7)
240
241 #define SDC_CLEAR_DATAEND (((uint32_t) 1 ) << 8)
242
243 #define SDC_CLEAR_STARTBITERR (((uint32_t) 1 ) << 9)
244
245 #define SDC_CLEAR_DATABLOCKEND (((uint32_t) 1 ) << 10)
246
251 #define SDC_MASK0_CMDCRCFAIL (((uint32_t) 1 ) << 0)
252
253 #define SDC_MASK0_DATACRCFAIL (((uint32_t) 1 ) << 1)
254
255 #define SDC_MASK0_CMDTIMEOUT (((uint32_t) 1 ) << 2)
256
257 #define SDC_MASK0_DATATIMEOUT (((uint32_t) 1 ) << 3)
258
259 #define SDC_MASK0_TXUNDERRUN (((uint32_t) 1 ) << 4)
260
261 #define SDC_MASK0_RXOVERRUN (((uint32_t) 1 ) << 5)
262
263 #define SDC_MASK0_CMDRESPEND (((uint32_t) 1 ) << 6)
264
265 #define SDC_MASK0_CMDSENT (((uint32_t) 1 ) << 7)
266
267 #define SDC_MASK0_DATAEND (((uint32_t) 1 ) << 8)
268
269 #define SDC_MASK0_STARTBITERR (((uint32_t) 1 ) << 9)
270
271 #define SDC_MASK0_DATABLOCKEND (((uint32_t) 1 ) << 10)
272
273 #define SDC_MASK0_CMDACTIVE (((uint32_t) 1 ) << 11)
274
275 #define SDC_MASK0_TXACTIVE (((uint32_t) 1 ) << 12)
276
277 #define SDC_MASK0_RXACTIVE (((uint32_t) 1 ) << 13)
278
279 #define SDC_MASK0_TXFIFOHALFEMPTY (((uint32_t) 1 ) << 14)
280
281 #define SDC_MASK0_RXFIFOHALFFULL (((uint32_t) 1 ) << 15)
282
283 #define SDC_MASK0_TXFIFOFULL (((uint32_t) 1 ) << 16)
284
285 #define SDC_MASK0_RXFIFOFULL (((uint32_t) 1 ) << 17)
286
287 #define SDC_MASK0_TXFIFOEMPTY (((uint32_t) 1 ) << 18)
288
289 #define SDC_MASK0_RXFIFOEMPTY (((uint32_t) 1 ) << 19)
290
291 #define SDC_MASK0_TXDATAAVLBL (((uint32_t) 1 ) << 20)
292
293 #define SDC_MASK0_RXDATAAVLBL (((uint32_t) 1 ) << 21)
294
295 #define SDC_MASK0_CMDERR (SDC_MASK0_CMDCRCFAIL | SDC_MASK0_CMDTIMEOUT | SDC_MASK0_STARTBITERR)
296
297 #define SDC_MASK0_TXDATAERR (SDC_MASK0_DATACRCFAIL | SDC_MASK0_DATATIMEOUT | SDC_MASK0_TXUNDERRUN | \
298 SDC_MASK0_STARTBITERR)
299
301 #define SDC_MASK0_RXDATAERR (SDC_MASK0_DATACRCFAIL | SDC_MASK0_DATATIMEOUT | SDC_MASK0_RXOVERRUN | \
302 SDC_MASK0_STARTBITERR)
303
304 #define SDC_MASK0_TXFIFO (SDC_MASK0_TXFIFOHALFEMPTY | SDC_MASK0_DATABLOCKEND )
305
306 #define SDC_MASK0_RXFIFO (SDC_MASK0_RXFIFOHALFFULL | SDC_MASK0_DATABLOCKEND )
307
309 #define SDC_MASK0_DATA (SDC_MASK0_DATAEND | SDC_MASK0_DATABLOCKEND )
310
314 #define SDC_FIFOCNT_VAL(n) ((uint32_t) n & 0x7FFF)
315
316 /* The number of bytes used to store card status*/
317 #define SDC_CARDSTATUS_BYTENUM ((uint32_t) 4)
318
322 typedef enum IP_SDC_001_PWR_CTRL {
323 SDC_POWER_OFF = 0,
324 SDC_POWER_UP = 2,
325 SDC_POWER_ON = 3,
326 } IP_SDC_001_PWR_CTRL_T;
327
331 typedef enum IP_SDC_001_CLOCK_CTRL {
332 SDC_CLOCK_ENABLE = 8,
333 SDC_CLOCK_POWER_SAVE = 9,
334 SDC_CLOCK_DIVIDER_BYPASS = 10,
335 SDC_CLOCK_WIDEBUS_MODE = 11,
336 } IP_SDC_001_CLOCK_CTRL_T;
337
341 typedef enum IP_SDC_001_RESPONSE {
342 SDC_NO_RESPONSE = SDC_COMMAND_NO_RSP,
343 SDC_SHORT_RESPONSE = SDC_COMMAND_SHORT_RSP,
344 SDC_LONG_RESPONSE = SDC_COMMAND_LONG_RSP,
345 } IP_SDC_001_RESPONSE_T;
346
350 typedef enum IP_SDC_001_TRANSFER_DIR {
351 SDC_TRANSFER_DIR_FROMCARD = SDC_DATACTRL_DIR_FROMCARD,
352 SDC_TRANSFER_DIR_TOCARD = SDC_DATACTRL_DIR_TOCARD,
353 } IP_SDC_001_TRANSFER_DIR_T;
354
358 typedef enum IP_SDC_001_TRANSFER_MODE {
359 SDC_TRANSFER_MODE_STREAM = SDC_DATACTRL_XFER_MODE_STREAM,
360 SDC_TRANSFER_MODE_BLOCK = SDC_DATACTRL_XFER_MODE_BLOCK,
361 } IP_SDC_001_TRANSFER_MODE_T;
362
366 typedef enum IP_SDC_001_BLOCK_SIZE {
367 SDC_BLOCK_SIZE_1 = 0,
368 SDC_BLOCK_SIZE_2,
369 SDC_BLOCK_SIZE_4,
370 SDC_BLOCK_SIZE_8,
371 SDC_BLOCK_SIZE_16,
372 SDC_BLOCK_SIZE_32,
373 SDC_BLOCK_SIZE_64,
374 SDC_BLOCK_SIZE_128,
375 SDC_BLOCK_SIZE_256,
376 SDC_BLOCK_SIZE_512,
377 SDC_BLOCK_SIZE_1024,
378 SDC_BLOCK_SIZE_2048,
379 } IP_SDC_001_BLOCK_SIZE_T;
380
384 typedef struct {
385 uint8_t CmdIndex;
386 uint32_t Data[SDC_CARDSTATUS_BYTENUM]; /* Card Status which can be stored in 1 or 4 bytes */
387 } IP_SDC_001_RESP_T;
388
392 typedef struct {
393 uint16_t BlockNum;
394 IP_SDC_001_BLOCK_SIZE_T BlockSize;
395 IP_SDC_001_TRANSFER_DIR_T Dir;
396 IP_SDC_001_TRANSFER_MODE_T Mode;
397 bool DMAUsed;
398 uint32_t Timeout;
399 } IP_SDC_001_DATA_TRANSFER_T;
400
413 void IP_SDC_PowerControl(IP_SDC_001_T *pSDC, IP_SDC_001_PWR_CTRL_T pwrMode, uint32_t flag);
414
425 void IP_SDC_SetClockDiv(IP_SDC_001_T *pSDC, uint8_t div);
426
434 void IP_SDC_ClockControl(IP_SDC_001_T *pSDC, IP_SDC_001_CLOCK_CTRL_T ctrlType,
435 FunctionalState NewState);
436
444 void IP_SDC_SetCommand(IP_SDC_001_T *pSDC, uint32_t Cmd, uint32_t Arg);
445
451 void IP_SDC_ResetCommand(IP_SDC_001_T *pSDC);
452
459 void IP_SDC_GetResp(IP_SDC_001_T *pSDC, IP_SDC_001_RESP_T *pResp);
460
467 STATIC INLINE void IP_SDC_SetDataTimer(IP_SDC_001_T *pSDC, uint32_t timeout)
468 {
469 pSDC->DATATIMER = timeout;
470 }
471
478 void IP_SDC_SetDataTransfer(IP_SDC_001_T *pSDC, IP_SDC_001_DATA_TRANSFER_T *pTransfer);
479
487 void IP_SDC_WriteFIFO(IP_SDC_001_T *pSDC, uint32_t *pSrc, bool bFirstHalf);
488
496 void IP_SDC_ReadFIFO(IP_SDC_001_T *pSDC, uint32_t *pDst, bool bFirstHalf);
497
503 STATIC INLINE uint32_t IP_SDC_GetStatus(IP_SDC_001_T *pSDC)
504 {
505 return pSDC->STATUS;
506 }
507
514 STATIC INLINE void IP_SDC_ClearStatus(IP_SDC_001_T *pSDC, uint32_t flag)
515 {
516 pSDC->CLEAR = flag;
517 }
518
525 STATIC INLINE void IP_SDC_SetIntMask(IP_SDC_001_T *pSDC, uint32_t mask)
526 {
527 pSDC->MASK0 = mask;
528 }
529
535 void IP_SDC_Init(IP_SDC_001_T *pSDC);
536
542 STATIC INLINE void IP_SDC_DeInit(IP_SDC_001_T *pSDC)
543 {
544 IP_SDC_PowerControl(pSDC, SDC_POWER_OFF, 0);
545 }
546
551 #ifdef __cplusplus
552 }
553 #endif
554
555 #endif /* __SDC_001_H_ */