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sysctl_17xx_40xx.h
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1 /*
2 * @brief LPC17xx/40xx System and Control driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef _SYSCTL_17XX_40XX_H_
33 #define _SYSCTL_17XX_40XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
47 typedef struct {
48 __IO uint32_t PLLCON;
49 __IO uint32_t PLLCFG;
50 __I uint32_t PLLSTAT;
51 __O uint32_t PLLFEED;
52 uint32_t RESERVED1[4];
53 } SYSCTL_PLL_REGS_T;
54
58 typedef enum {
59 SYSCTL_MAIN_PLL,
60 SYSCTL_USB_PLL,
61 } CHIP_SYSCTL_PLL_T;
62
66 typedef struct {
67 __IO uint32_t FLASHCFG;
68 uint32_t RESERVED0[15];
69 __IO uint32_t MEMMAP;
70 uint32_t RESERVED1[15];
71 SYSCTL_PLL_REGS_T PLL[SYSCTL_USB_PLL + 1];
72 __IO uint32_t PCON;
73 __IO uint32_t PCONP;
74 #if defined(CHIP_LPC175X_6X)
75 uint32_t RESERVED2[15];
76 #elif defined(CHIP_LPC177X_8X)
77 uint32_t RESERVED2[14];
78 __IO uint32_t EMCCLKSEL;
79 #else
80 __IO uint32_t PCONP1;
81 uint32_t RESERVED2[13];
82 __IO uint32_t EMCCLKSEL;
83 #endif
84 __IO uint32_t CCLKSEL;
85 __IO uint32_t USBCLKSEL;
86 __IO uint32_t CLKSRCSEL;
87 __IO uint32_t CANSLEEPCLR;
88 __IO uint32_t CANWAKEFLAGS;
89 uint32_t RESERVED3[10];
90 __IO uint32_t EXTINT;
91 uint32_t RESERVED4;
92 __IO uint32_t EXTMODE;
93 __IO uint32_t EXTPOLAR;
94 uint32_t RESERVED5[12];
95 __IO uint32_t RSID;
96 #if defined(CHIP_LPC175X_6X) || defined(CHIP_LPC407X_8X)
97 uint32_t RESERVED6[7];
98 #elif defined(CHIP_LPC177X_8X)
99 uint32_t RESERVED6;
100 uint32_t MATRIXARB;
101 uint32_t RESERVED6A[5];
102 #endif
103 __IO uint32_t SCS;
104 __IO uint32_t RESERVED7;
105 #if defined(CHIP_LPC175X_6X)
106 __IO uint32_t PCLKSEL[2];
107 uint32_t RESERVED8[4];
108 #else
109 __IO uint32_t PCLKSEL;
110 uint32_t RESERVED9;
111 __IO uint32_t PBOOST;
112 __IO uint32_t SPIFICLKSEL;
113 __IO uint32_t LCD_CFG;
114 uint32_t RESERVED10;
115 #endif
116 __IO uint32_t USBIntSt;
117 __IO uint32_t DMAREQSEL;
118 __IO uint32_t CLKOUTCFG;
119 #if defined(CHIP_LPC175X_6X)
120 uint32_t RESERVED11[6];
121 #else
122 __IO uint32_t RSTCON[2];
123 uint32_t RESERVED11[2];
124 __IO uint32_t EMCDLYCTL;
125 __IO uint32_t EMCCAL;
126 #endif
127 } LPC_SYSCTL_T;
128
132 typedef enum CHIP_SYSCTL_BOOT_MODE_REMAP {
133 REMAP_BOOT_LOADER_MODE,
134 REMAP_USER_FLASH_MODE
135 } CHIP_SYSCTL_BOOT_MODE_REMAP_T;
136
142 STATIC INLINE void Chip_SYSCTL_Map(CHIP_SYSCTL_BOOT_MODE_REMAP_T remap)
143 {
144 LPC_SYSCTL->MEMMAP = (uint32_t) remap;
145 }
146
150 #define SYSCTL_RST_POR (1 << 0)
151 #define SYSCTL_RST_EXTRST (1 << 1)
152 #define SYSCTL_RST_WDT (1 << 2)
153 #define SYSCTL_RST_BOD (1 << 3)
154 #if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC407X_8X)
155 #define SYSCTL_RST_SYSRST (1 << 4)
156 #define SYSCTL_RST_LOCKUP (1 << 5)
157 #endif
158
164 STATIC INLINE uint32_t Chip_SYSCTL_GetSystemRSTStatus(void)
165 {
166 return LPC_SYSCTL->RSID;
167 }
168
174 STATIC INLINE void Chip_SYSCTL_ClearSystemRSTStatus(uint32_t reset)
175 {
176 LPC_SYSCTL->RSID = reset;
177 }
178
183 STATIC INLINE void Chip_SYSCTL_EnableBOD(void)
184 {
185 LPC_SYSCTL->PCON |= (1 << 3);
186 }
187
192 STATIC INLINE void Chip_SYSCTL_DisableBOD(void)
193 {
194 LPC_SYSCTL->PCON &= ~(1 << 3);
195 }
196
201 STATIC INLINE void Chip_SYSCTL_EnableBODReset(void)
202 {
203 LPC_SYSCTL->PCON |= (1 << 4);
204 }
205
210 STATIC INLINE void Chip_SYSCTL_DisableBODReset(void)
211 {
212 LPC_SYSCTL->PCON &= ~(1 << 4);
213 }
214
219 STATIC INLINE void Chip_SYSCTL_EnableBODRPM(void)
220 {
221 LPC_SYSCTL->PCON |= (1 << 5);
222 }
223
228 STATIC INLINE void Chip_SYSCTL_DisableBODRPM(void)
229 {
230 LPC_SYSCTL->PCON &= ~(1 << 5);
231 }
232
233 #define SYSCTL_PD_SMFLAG (1 << 8)
234 #define SYSCTL_PD_DSFLAG (1 << 9)
235 #define SYSCTL_PD_PDFLAG (1 << 10)
236 #define SYSCTL_PD_DPDFLAG (1 << 11)
245 uint32_t Chip_SYSCTL_GetClrSleepFlags(uint32_t flags);
246
247 #if !defined(CHIP_LPC175X_6X)
248
252 STATIC INLINE void Chip_SYSCTL_EnableBoost(void)
253 {
254 LPC_SYSCTL->PBOOST = 0x3;
255 }
256
261 STATIC INLINE void Chip_SYSCTL_DisableBoost(void)
262 {
263 LPC_SYSCTL->PBOOST = 0x0;
264 }
265
266 #endif
267
268 #if !defined(CHIP_LPC175X_6X)
269
273 typedef enum {
274 SYSCTL_RESET_LCD,
275 SYSCTL_RESET_TIMER0,
276 SYSCTL_RESET_TIMER1,
277 SYSCTL_RESET_UART0,
278 SYSCTL_RESET_UART1,
279 SYSCTL_RESET_PWM0,
280 SYSCTL_RESET_PWM1,
281 SYSCTL_RESET_I2C0,
282 SYSCTL_RESET_UART4,
283 SYSCTL_RESET_RTC,
284 SYSCTL_RESET_SSP1,
285 SYSCTL_RESET_EMC,
286 SYSCTL_RESET_ADC,
287 SYSCTL_RESET_CAN1,
288 SYSCTL_RESET_CAN2,
289 SYSCTL_RESET_GPIO,
290 SYSCTL_RESET_SPIFI,
291 SYSCTL_RESET_MCPWM,
292 SYSCTL_RESET_QEI,
293 SYSCTL_RESET_I2C1,
294 SYSCTL_RESET_SSP2,
295 SYSCTL_RESET_SSP0,
296 SYSCTL_RESET_TIMER2,
297 SYSCTL_RESET_TIMER3,
298 SYSCTL_RESET_UART2,
299 SYSCTL_RESET_UART3,
300 SYSCTL_RESET_I2C2,
301 SYSCTL_RESET_I2S,
302 SYSCTL_RESET_PCSDC,
303 SYSCTL_RESET_GPDMA,
304 SYSCTL_RESET_ENET,
305 SYSCTL_RESET_USB,
306 SYSCTL_RESET_IOCON,
307 SYSCTL_RESET_DAC,
308 SYSCTL_RESET_CANACC,
309 } CHIP_SYSCTL_RESET_T;
310
316 void Chip_SYSCTL_PeriphReset(CHIP_SYSCTL_RESET_T periph);
317
318 #endif
319
324 #ifdef __cplusplus
325 }
326 #endif
327
328 #endif /* _SYSCTL_17XX_40XX_H_ */