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clock_8xx.h
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1 /*
2 * @brief LPC8xx clock driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licenser disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __CLOCK_8XX_H_
33 #define __CLOCK_8XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
61 /* Internal oscillator frequency */
62 #define SYSCTL_IRC_FREQ (12000000)
63
67 typedef enum CHIP_SYSCTL_PLLCLKSRC {
68 SYSCTL_PLLCLKSRC_IRC = 0,
69 SYSCTL_PLLCLKSRC_SYSOSC,
70 SYSCTL_PLLCLKSRC_RESERVED,
71 SYSCTL_PLLCLKSRC_EXT_CLKIN,
72 } CHIP_SYSCTL_PLLCLKSRC_T;
73
78 typedef enum CHIP_WDTLFO_OSC {
79 WDTLFO_OSC_ILLEGAL,
80 WDTLFO_OSC_0_60,
81 WDTLFO_OSC_1_05,
82 WDTLFO_OSC_1_40,
83 WDTLFO_OSC_1_75,
84 WDTLFO_OSC_2_10,
85 WDTLFO_OSC_2_40,
86 WDTLFO_OSC_2_70,
87 WDTLFO_OSC_3_00,
88 WDTLFO_OSC_3_25,
89 WDTLFO_OSC_3_50,
90 WDTLFO_OSC_3_75,
91 WDTLFO_OSC_4_00,
92 WDTLFO_OSC_4_20,
93 WDTLFO_OSC_4_40,
94 WDTLFO_OSC_4_60
95 } CHIP_WDTLFO_OSC_T;
96
100 typedef enum CHIP_SYSCTL_MAINCLKSRC{
101 SYSCTL_MAINCLKSRC_IRC = 0,
102 SYSCTL_MAINCLKSRC_PLLIN,
103 SYSCTL_MAINCLKSRC_WDTOSC,
104 SYSCTL_MAINCLKSRC_PLLOUT,
105 } CHIP_SYSCTL_MAINCLKSRC_T;
106
110 typedef enum CHIP_SYSCTL_CLOCK{
111 SYSCTL_CLOCK_SYS = 0,
112 SYSCTL_CLOCK_ROM,
113 SYSCTL_CLOCK_RAM,
114 SYSCTL_CLOCK_FLASHREG,
115 SYSCTL_CLOCK_FLASH,
116 SYSCTL_CLOCK_I2C,
117 SYSCTL_CLOCK_GPIO,
118 SYSCTL_CLOCK_SWM,
119 SYSCTL_CLOCK_SCT,
120 SYSCTL_CLOCK_WKT,
121 SYSCTL_CLOCK_MRT,
122 SYSCTL_CLOCK_SPI0,
123 SYSCTL_CLOCK_SPI1,
124 SYSCTL_CLOCK_CRC,
125 SYSCTL_CLOCK_UART0,
126 SYSCTL_CLOCK_UART1,
127 SYSCTL_CLOCK_UART2,
128 SYSCTL_CLOCK_WWDT,
129 SYSCTL_CLOCK_IOCON,
130 SYSCTL_CLOCK_ACOMP
131 } CHIP_SYSCTL_CLOCK_T;
132
136 typedef enum CHIP_SYSCTL_CLKOUTSRC{
137 SYSCTL_CLKOUTSRC_IRC = 0,
138 SYSCTL_CLKOUTSRC_SYSOSC,
139 SYSCTL_CLKOUTSRC_WDTOSC,
140 SYSCTL_CLKOUTSRC_MAINSYSCLK,
141 } CHIP_SYSCTL_CLKOUTSRC_T;
142
150 STATIC INLINE void Chip_Clock_SetupSystemPLL(uint8_t msel, uint8_t psel)
151 {
152 LPC_SYSCTL->SYSPLLCTRL = (msel & 0x1F) | ((psel & 0x3) << 5);
153 }
154
159 STATIC INLINE bool Chip_Clock_IsSystemPLLLocked(void)
160 {
161 return (bool) ((LPC_SYSCTL->SYSPLLSTAT & 1) != 0);
162 }
163
171 STATIC INLINE void Chip_Clock_SetWDTOSC(CHIP_WDTLFO_OSC_T wdtclk, uint8_t div)
172 {
173 LPC_SYSCTL->WDTOSCCTRL = (((uint32_t) wdtclk) << 5) | ((div >> 1) - 1);
174 }
175
180 STATIC INLINE CHIP_SYSCTL_MAINCLKSRC_T Chip_Clock_GetMainClockSource(void)
181 {
182 return (CHIP_SYSCTL_MAINCLKSRC_T) (LPC_SYSCTL->MAINCLKSEL);
183 }
184
192 STATIC INLINE void Chip_Clock_SetSysClockDiv(uint32_t div)
193 {
194 LPC_SYSCTL->SYSAHBCLKDIV = div;
195 }
196
202 STATIC INLINE void Chip_Clock_EnablePeriphClock(CHIP_SYSCTL_CLOCK_T clk)
203 {
204 LPC_SYSCTL->SYSAHBCLKCTRL |= (1 << clk);
205 }
206
212 STATIC INLINE void Chip_Clock_DisablePeriphClock(CHIP_SYSCTL_CLOCK_T clk)
213 {
214 LPC_SYSCTL->SYSAHBCLKCTRL &= ~(1 << clk);
215 }
216
224 STATIC INLINE void Chip_Clock_SetUARTClockDiv(uint32_t div)
225 {
226 LPC_SYSCTL->UARTCLKDIV = div;
227 }
228
234 STATIC INLINE uint32_t Chip_Clock_GetUARTClockDiv(void)
235 {
236 return LPC_SYSCTL->UARTCLKDIV;
237 }
238
243 STATIC INLINE uint32_t Chip_Clock_GetMainOscRate(void)
244 {
245 return CRYSTAL_MAIN_FREQ_IN;
246 }
247
252 STATIC INLINE uint32_t Chip_Clock_GetIntOscRate(void)
253 {
254 return SYSCTL_IRC_FREQ;
255 }
256
261 STATIC INLINE uint32_t Chip_Clock_GetExtClockInRate(void)
262 {
263 return EXTCLKIN_FREQ_IN;
264 }
265
273 void Chip_Clock_SetSystemPllSource(CHIP_SYSCTL_PLLCLKSRC_T src);
274
284 void Chip_Clock_SetPLLBypass(bool bypass, bool highfr);
285
293 void Chip_Clock_SetMainClockSource(CHIP_SYSCTL_MAINCLKSRC_T src);
294
305 void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div);
306
312 uint32_t Chip_Clock_GetWDTOSCRate(void);
313
318 uint32_t Chip_Clock_GetSystemPllInClockRate(void);
319
324 uint32_t Chip_Clock_GetSystemPllOutClockRate(void);
325
330 uint32_t Chip_Clock_GetMainClockRate(void);
331
336 uint32_t Chip_Clock_GetSystemClockRate(void);
337
342 #ifdef __cplusplus
343 }
344 #endif
345
346 #endif /* __CLOCK_8XX_H_ */