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Data Structures | Macros | Enumerations | Functions
IP: SPI register block and driver (002)
IP drivers: Common drivers used on multiple NXP devices

## Detailed Description

## Data Structures
struct | IP_SPI_002_T
| SPI register block structure. More...
struct | IP_SPI_CONFIG_T
| SPI Configure Struct. More...
struct | IP_SPI_DELAY_CONFIG_T
| SPI Delay Configure Struct. More...

## Macros
#define | SPI_CFG_BITMASK ((uint32_t) 0x1BD)
#define | SPI_CFG_SPI_EN ((uint32_t) (1 << 0))
#define | SPI_CFG_SLAVE_EN ((uint32_t) 0)
#define | SPI_CFG_MASTER_EN ((uint32_t) (1 << 2))
#define | SPI_CFG_MSB_FIRST_EN ((uint32_t) 0) /*Data will be transmitted and received in standard order (MSB first).*/
#define | SPI_CFG_LSB_FIRST_EN ((uint32_t) (1 << 3))/*Data will be transmitted and received in reverse order (LSB first).*/
#define | SPI_CFG_CPHA_FIRST ((uint32_t) (0)) /*Capture data on the first edge, Change data on the following edge*/
#define | SPI_CFG_CPHA_SECOND ((uint32_t) (1 << 4)) /*Change data on the first edge, Capture data on the following edge*/
#define | SPI_CFG_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/
#define | SPI_CFG_CPOL_HI ((uint32_t) (1 << 5)) /* The rest state of the clock (between frames) is high.*/
#define | SPI_CFG_LBM_EN ((uint32_t) (1 << 7))
#define | SPI_CFG_SPOL_LO ((uint32_t) (0)) /* SSEL is active Low */
#define | SPI_CFG_SPOL_HI ((uint32_t) (1 << 8)) /* SSEL is active High */
#define | SPI_DLY_BITMASK ((uint32_t) 0xFFFF)
#define | SPI_DLY_PRE_DELAY(n) ((uint32_t) ((n) & 0x0F)) /* Time Unit: SPI clock time */
#define | SPI_DLY_POST_DELAY(n) ((uint32_t) (((n) & 0x0F) << 4)) /* Time Unit: SPI clock time */
#define | SPI_DLY_FRAME_DELAY(n) ((uint32_t) (((n) & 0x0F) << 8)) /* Time Unit: SPI clock time */
#define | SPI_DLY_TRANSFER_DELAY(n) ((uint32_t) (((n) & 0x0F) << 12)) /* Time Unit: SPI clock time */
#define | SPI_STAT_BITMASK ((uint32_t) 0x1FF)
#define | SPI_STAT_RXRDY ((uint32_t) (1 << 0)) /* Data is ready for read */
#define | SPI_STAT_TXRDY ((uint32_t) (1 << 1)) /* Data may be written to transmit buffer */
#define | SPI_STAT_RXOV ((uint32_t) (1 << 2)) /* Data comes while receiver buffer is in used */
#define | SPI_STAT_TXUR ((uint32_t) (1 << 3)) /* There is no data to be sent in the next input clock */
#define | SPI_STAT_SSA ((uint32_t) (1 << 4)) /* There is SSEL transition from deasserted to asserted */
#define | SPI_STAT_SSD ((uint32_t) (1 << 5)) /* There is SSEL transition from asserted to deasserted */
#define | SPI_STAT_STALLED ((uint32_t) (1 << 6)) /* SPI is currently in a stall condition. */
#define | SPI_STAT_EOT ((uint32_t) (1 << 7)) /* The current frame is the last frame of the current transfer. */
#define | SPI_STAT_LE ((uint32_t) (1 << 8)) /* SPI master function is fully idle. */
#define | SPI_STAT_CLR_RXOV ((uint32_t) (1 << 2))
#define | SPI_STAT_CLR_TXUR ((uint32_t) (1 << 3))
#define | SPI_STAT_CLR_SSA ((uint32_t) (1 << 4))
#define | SPI_STAT_CLR_SSD ((uint32_t) (1 << 5))
#define | SPI_STAT_FORCE_EOT ((uint32_t) (1 << 7))
#define | SPI_INTENSET_BITMASK ((uint32_t) 0x3F)
#define | SPI_INTENSET_RXDYEN ((uint32_t) (1 << 0))
#define | SPI_INTENSET_TXDYEN ((uint32_t) (1 << 1))
#define | SPI_INTENSET_RXOVEN ((uint32_t) (1 << 2))
#define | SPI_INTENSET_TXUREN ((uint32_t) (1 << 3))
#define | SPI_INTENSET_SSAEN ((uint32_t) (1 << 2))
#define | SPI_INTENSET_SSDEN ((uint32_t) (1 << 2))
#define | SPI_INTENCLR_BITMASK ((uint32_t) 0x3F)
#define | SPI_INTENCLR_RXDYEN ((uint32_t) (1 << 0))
#define | SPI_INTENCLR_TXDYEN ((uint32_t) (1 << 1))
#define | SPI_INTENCLR_RXOVEN ((uint32_t) (1 << 2))
#define | SPI_INTENCLR_TXUREN ((uint32_t) (1 << 3))
#define | SPI_INTENCLR_SSAEN ((uint32_t) (1 << 2))
#define | SPI_INTENCLR_SSDEN ((uint32_t) (1 << 2))
#define | SPI_RXDAT_BITMASK ((uint32_t) 0x11FFFF)
#define | SPI_RXDAT_DATA(n) ((uint32_t) ((n) & 0xFFFF))
#define | SPI_RXDAT_RXSSELN_ACTIVE ((uint32_t) 0) /* SSEL is in active state */
#define | SPI_RXDAT_RXSSELN_INACTIVE ((uint32_t) (1 << 16)) /* SSEL is in inactive state */
#define | SPI_RXDAT_SOT ((uint32_t) (1 << 20)) /* This is the first frame received after SSEL is asserted */
#define | SPI_TXDATCTL_BITMASK ((uint32_t) 0xF71FFFF)
#define | SPI_TXDATCTL_DATA(n) ((uint32_t) ((n) & 0xFFFF))
#define | SPI_TXDATCTL_ASSERT_SSEL ((uint32_t) 0)
#define | SPI_TXDATCTL_DEASSERT_SSEL ((uint32_t) (1 << 16))
#define | SPI_TXDATCTL_EOT ((uint32_t) (1 << 20)) /* This is the last frame of the current transfer */
#define | SPI_TXDATCTL_EOF ((uint32_t) (1 << 21)) /* This is the last part of the current frame */
#define | SPI_TXDATCTL_RXIGNORE ((uint32_t) (1 << 22)) /* Received data is ignored */
#define | SPI_TXDATCTL_FLEN(n) ((uint32_t) (((n) & 0x0F) << 24)) /* Frame Length -1 */
#define | SPI_TXDAT_DATA(n) ((uint32_t) ((n) & 0xFFFF))
#define | SPI_TXCTL_BITMASK ((uint32_t) 0xF71FF00)
#define | SPI_TXCTL_ASSERT_SSEL ((uint32_t) 0)
#define | SPI_TXCTL_DEASSERT_SSEL ((uint32_t) (1 << 16))
#define | SPI_TXCTL_EOT ((uint32_t) (1 << 20)) /* This is the last frame of the current transfer */
#define | SPI_TXCTL_EOF ((uint32_t) (1 << 21)) /* This is the last part of the current frame */
#define | SPI_TXCTL_RXIGNORE ((uint32_t) (1 << 22)) /* Received data is ignored */
#define | SPI_TXCTL_FLEN(n) ((uint32_t) (((n) & 0x0F) << 24)) /* Frame Length -1 */
#define | SPI_DIV_VAL(n) ((uint32_t) ((n) & 0xFFFF)) /* SPI_CLK = PCLK/(DIV_VAL+1)*/
#define | SPI_INTSTAT_BITMASK ((uint32_t) 0x3F)
#define | SPI_INTSTAT_RXRDY ((uint32_t) (1 << 0)) /* Data is ready for read */
#define | SPI_INTSTAT_TXRDY ((uint32_t) (1 << 1)) /* Data may be written to transmit buffer */
#define | SPI_INTSTAT_RXOV ((uint32_t) (1 << 2)) /* Data comes while receiver buffer is in used */
#define | SPI_INTSTAT_TXUR ((uint32_t) (1 << 3)) /* There is no data to be sent in the next input clock */
#define | SPI_INTSTAT_SSA ((uint32_t) (1 << 4)) /* There is SSEL transition from deasserted to asserted */
#define | SPI_INTSTAT_SSD ((uint32_t) (1 << 5)) /* There is SSEL transition from asserted to deasserted */

## Enumerations
enum | IP_SPI_MODE_T { SPI_MODE_MASTER = SPI_CR_MASTER_EN, SPI_MODE_SLAVE = SPI_CR_SLAVE_EN, SPI_MODE_MASTER = SPI_CFG_MASTER_EN, SPI_MODE_SLAVE = SPI_CFG_SLAVE_EN }
| SPI Mode. More...
enum | IP_SPI_CLOCK_MODE_T { SPI_CLOCK_CPHA0_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_FIRST, SPI_CLOCK_CPHA0_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_FIRST, SPI_CLOCK_CPHA1_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_SECOND, SPI_CLOCK_CPHA1_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_SECOND, SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0, SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0, SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1, SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1, SPI_CLOCK_CPHA0_CPOL0 = SPI_CFG_CPOL_LO | SPI_CFG_CPHA_FIRST, SPI_CLOCK_CPHA0_CPOL1 = SPI_CFG_CPOL_HI | SPI_CFG_CPHA_FIRST, SPI_CLOCK_CPHA1_CPOL0 = SPI_CFG_CPOL_LO | SPI_CFG_CPHA_SECOND, SPI_CLOCK_CPHA1_CPOL1 = SPI_CFG_CPOL_HI | SPI_CFG_CPHA_SECOND, SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0, SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0, SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1, SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1 }
| SPI Clock Mode. More...
enum | IP_SPI_DATA_ORDER_T { SPI_DATA_MSB_FIRST = SPI_CR_MSB_FIRST_EN, SPI_DATA_LSB_FIRST = SPI_CR_LSB_FIRST_EN, SPI_DATA_MSB_FIRST = SPI_CFG_MSB_FIRST_EN, SPI_DATA_LSB_FIRST = SPI_CFG_LSB_FIRST_EN }
| SPI Data Order Mode. More...
enum | IP_SPI_SSEL_POL_T { SPI_SSEL_ACTIVE_LO = SPI_CFG_SPOL_LO, SPI_SSEL_ACTIVE_HI = SPI_CFG_SPOL_HI }
| SPI SSEL Polarity definition. More...

## Functions
STATIC INLINE void | IP_SPI_Enable (IP_SPI_002_T *pSPI)
| Enable SPI peripheral.
STATIC INLINE void | IP_SPI_Disable (IP_SPI_002_T *pSPI)
| Disable SPI peripheral.
STATIC INLINE void | IP_SPI_DeInit (IP_SPI_002_T *pSPI)
| Deinitialise the SPI.
STATIC INLINE void | IP_SPI_EnableLoopBack (IP_SPI_002_T *pSPI)
| Enable loopback mode.
STATIC INLINE void | IP_SPI_DisableLoopBack (IP_SPI_002_T *pSPI)
| Disable loopback mode.
STATIC INLINE uint32_t | IP_SPI_GetStatus (IP_SPI_002_T *pSPI)
| Get the current status of SPI controller.
STATIC INLINE void | IP_SPI_ForceEOT (IP_SPI_002_T *pSPI)
| Force to end of transfer.
STATIC INLINE void | IP_SPI_ClearStatus (IP_SPI_002_T *pSPI, uint32_t Flag)
| Clear SPI status.
STATIC INLINE void | IP_SPI_IntEnable (IP_SPI_002_T *pSPI, uint32_t IntEnMsk)
| Enable the interrupt(s) for the SPI.
STATIC INLINE void | IP_SPI_IntDisable (IP_SPI_002_T *pSPI, uint32_t IntDisMsk)
| Disable the interrupt(s) for the SPI.
STATIC INLINE uint32_t | IP_SPI_GetIntStatus (IP_SPI_002_T *pSPI)
| Get the masked interrupt status.
STATIC INLINE void | IP_SPI_SendFrame (IP_SPI_002_T *pSPI, uint16_t data)
| Send SPI 16-bit data.
STATIC INLINE void | IP_SPI_SetControlInfo (IP_SPI_002_T *pSPI, uint8_t Flen, uint32_t Flag)
| Set control information including SSEL, EOT, EOF RXIGNORE and FLEN.
STATIC INLINE void | IP_SPI_SendFrameAndControl (IP_SPI_002_T *pSPI, uint16_t TxData, uint8_t Flen, uint32_t Flag)
| Send SPI 16-bit data and control information simutaneously.
STATIC INLINE uint16_t | IP_SPI_ReceiveFrame (IP_SPI_002_T *pSPI)
| Get received SPI data.
void | IP_SPI_Init (IP_SPI_002_T *pSPI, IP_SPI_CONFIG_T *pConfig)
| Initialise the SPI.
void | IP_SPI_DelayConfig (IP_SPI_002_T *pSPI, IP_SPI_DELAY_CONFIG_T *pConfig)
| Configure the SPI Delay parameters.

## Macro Definition Documentation

#define SPI_CFG_BITMASK ((uint32_t) 0x1BD)

Macro defines for SPI Configuration register

Definition at line 68 of file spi_002.h.

#define SPI_CFG_CPHA_FIRST ((uint32_t) (0)) /*Capture data on the first edge, Change data on the following edge*/

SPI Clock Phase Select

Definition at line 80 of file spi_002.h.

#define SPI_CFG_CPHA_SECOND ((uint32_t) (1 << 4)) /*Change data on the first edge, Capture data on the following edge*/

Definition at line 81 of file spi_002.h.

#define SPI_CFG_CPOL_HI ((uint32_t) (1 << 5)) /* The rest state of the clock (between frames) is high.*/

Definition at line 84 of file spi_002.h.

#define SPI_CFG_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/

SPI Clock Polarity Select

Definition at line 83 of file spi_002.h.

#define SPI_CFG_LBM_EN ((uint32_t) (1 << 7))

SPI control 1 loopback mode enable

Definition at line 86 of file spi_002.h.

#define SPI_CFG_LSB_FIRST_EN ((uint32_t) (1 << 3))/*Data will be transmitted and received in reverse order (LSB first).*/

SPI LSB First mode enable

Definition at line 78 of file spi_002.h.

#define SPI_CFG_MASTER_EN ((uint32_t) (1 << 2))

SPI Master Mode Select

Definition at line 74 of file spi_002.h.

#define SPI_CFG_MSB_FIRST_EN ((uint32_t) 0) /*Data will be transmitted and received in standard order (MSB first).*/

SPI MSB First mode enable

Definition at line 76 of file spi_002.h.

#define SPI_CFG_SLAVE_EN ((uint32_t) 0)

SPI Slave Mode Select

Definition at line 72 of file spi_002.h.

#define SPI_CFG_SPI_EN ((uint32_t) (1 << 0))

SPI enable

Definition at line 70 of file spi_002.h.

#define SPI_CFG_SPOL_HI ((uint32_t) (1 << 8)) /* SSEL is active High */

Definition at line 89 of file spi_002.h.

#define SPI_CFG_SPOL_LO ((uint32_t) (0)) /* SSEL is active Low */

SPI SSEL Polarity Select

Definition at line 88 of file spi_002.h.

#define SPI_DIV_VAL | ( |  | n | ) | ((uint32_t) ((n) & 0xFFFF)) /* SPI_CLK = PCLK/(DIV_VAL+1)*/

Macro defines for SPI Divider registerRate divider value (In Master Mode only)

Definition at line 235 of file spi_002.h.

#define SPI_DLY_BITMASK ((uint32_t) 0xFFFF)

Macro defines for SPI Delay registerSPI DLY Register Mask

Definition at line 95 of file spi_002.h.

#define SPI_DLY_FRAME_DELAY | ( |  | n | ) | ((uint32_t) (((n) & 0x0F) << 8)) /* Time Unit: SPI clock time */

Controls the minimum amount of time between adjacent data frames.

Definition at line 101 of file spi_002.h.

#define SPI_DLY_POST_DELAY | ( |  | n | ) | ((uint32_t) (((n) & 0x0F) << 4)) /* Time Unit: SPI clock time */

Controls the amount of time between the end of a data frame and SSEL deassertion.

Definition at line 99 of file spi_002.h.

#define SPI_DLY_PRE_DELAY | ( |  | n | ) | ((uint32_t) ((n) & 0x0F)) /* Time Unit: SPI clock time */

Controls the amount of time between SSEL assertion and the beginning of a data frame.

Definition at line 97 of file spi_002.h.

#define SPI_DLY_TRANSFER_DELAY | ( |  | n | ) | ((uint32_t) (((n) & 0x0F) << 12)) /* Time Unit: SPI clock time */

Controls the minimum amount of time that the SSEL is deasserted between transfers.

Definition at line 103 of file spi_002.h.

#define SPI_INTENCLR_BITMASK ((uint32_t) 0x3F)

Macro defines for SPI Interrupt Enable Clear register

Definition at line 162 of file spi_002.h.

#define SPI_INTENCLR_RXDYEN ((uint32_t) (1 << 0))

Disable Interrupt when receiver data is available

Definition at line 164 of file spi_002.h.

#define SPI_INTENCLR_RXOVEN ((uint32_t) (1 << 2))

Disable Interrupt when a receiver overrun occurs

Definition at line 168 of file spi_002.h.

#define SPI_INTENCLR_SSAEN ((uint32_t) (1 << 2))

Disable Interrupt when the Slave Select is asserted.

Definition at line 172 of file spi_002.h.

#define SPI_INTENCLR_SSDEN ((uint32_t) (1 << 2))

Disable Interrupt when the Slave Select is deasserted..

Definition at line 174 of file spi_002.h.

#define SPI_INTENCLR_TXDYEN ((uint32_t) (1 << 1))

Disable Interrupt when the transmitter holding register is available.

Definition at line 166 of file spi_002.h.

#define SPI_INTENCLR_TXUREN ((uint32_t) (1 << 3))

Disable Interrupt when a transmitter underrun occurs (In Slave Mode Only)

Definition at line 170 of file spi_002.h.

#define SPI_INTENSET_BITMASK ((uint32_t) 0x3F)

Macro defines for SPI Interrupt Enable read and Set register

Definition at line 144 of file spi_002.h.

#define SPI_INTENSET_RXDYEN ((uint32_t) (1 << 0))

Enable Interrupt when receiver data is available

Definition at line 146 of file spi_002.h.

#define SPI_INTENSET_RXOVEN ((uint32_t) (1 << 2))

Enable Interrupt when a receiver overrun occurs

Definition at line 150 of file spi_002.h.

#define SPI_INTENSET_SSAEN ((uint32_t) (1 << 2))

Enable Interrupt when the Slave Select is asserted.

Definition at line 154 of file spi_002.h.

#define SPI_INTENSET_SSDEN ((uint32_t) (1 << 2))

Enable Interrupt when the Slave Select is deasserted..

Definition at line 156 of file spi_002.h.

#define SPI_INTENSET_TXDYEN ((uint32_t) (1 << 1))

Enable Interrupt when the transmitter holding register is available.

Definition at line 148 of file spi_002.h.

#define SPI_INTENSET_TXUREN ((uint32_t) (1 << 3))

Enable Interrupt when a transmitter underrun occurs (In Slave Mode Only)

Definition at line 152 of file spi_002.h.

#define SPI_INTSTAT_BITMASK ((uint32_t) 0x3F)

Macro defines for SPI Interrupt Status register

Definition at line 241 of file spi_002.h.

#define SPI_INTSTAT_RXOV ((uint32_t) (1 << 2)) /* Data comes while receiver buffer is in used */

Definition at line 247 of file spi_002.h.

#define SPI_INTSTAT_RXRDY ((uint32_t) (1 << 0)) /* Data is ready for read */

Definition at line 243 of file spi_002.h.

#define SPI_INTSTAT_SSA ((uint32_t) (1 << 4)) /* There is SSEL transition from deasserted to asserted */

Definition at line 251 of file spi_002.h.

#define SPI_INTSTAT_SSD ((uint32_t) (1 << 5)) /* There is SSEL transition from asserted to deasserted */

Definition at line 253 of file spi_002.h.

#define SPI_INTSTAT_TXRDY ((uint32_t) (1 << 1)) /* Data may be written to transmit buffer */

Definition at line 245 of file spi_002.h.

#define SPI_INTSTAT_TXUR ((uint32_t) (1 << 3)) /* There is no data to be sent in the next input clock */

Definition at line 249 of file spi_002.h.

#define SPI_RXDAT_BITMASK ((uint32_t) 0x11FFFF)

Macro defines for SPI Receiver Data register

Definition at line 180 of file spi_002.h.

#define SPI_RXDAT_DATA | ( |  | n | ) | ((uint32_t) ((n) & 0xFFFF))

Receiver Data

Definition at line 182 of file spi_002.h.

#define SPI_RXDAT_RXSSELN_ACTIVE ((uint32_t) 0) /* SSEL is in active state */

The state of SSEL pin

Definition at line 184 of file spi_002.h.

#define SPI_RXDAT_RXSSELN_INACTIVE ((uint32_t) (1 << 16)) /* SSEL is in inactive state */

Definition at line 185 of file spi_002.h.

#define SPI_RXDAT_SOT ((uint32_t) (1 << 20)) /* This is the first frame received after SSEL is asserted */

Start of Transfer flag

Definition at line 187 of file spi_002.h.

#define SPI_STAT_BITMASK ((uint32_t) 0x1FF)

Macro defines for SPI Status register

Definition at line 109 of file spi_002.h.

#define SPI_STAT_CLR_RXOV ((uint32_t) (1 << 2))

Definition at line 130 of file spi_002.h.

#define SPI_STAT_CLR_SSA ((uint32_t) (1 << 4))

Definition at line 134 of file spi_002.h.

#define SPI_STAT_CLR_SSD ((uint32_t) (1 << 5))

Definition at line 136 of file spi_002.h.

#define SPI_STAT_CLR_TXUR ((uint32_t) (1 << 3))

Definition at line 132 of file spi_002.h.

#define SPI_STAT_EOT ((uint32_t) (1 << 7)) /* The current frame is the last frame of the current transfer. */

Definition at line 125 of file spi_002.h.

#define SPI_STAT_FORCE_EOT ((uint32_t) (1 << 7))

Definition at line 138 of file spi_002.h.

#define SPI_STAT_LE ((uint32_t) (1 << 8)) /* SPI master function is fully idle. */

Definition at line 127 of file spi_002.h.

#define SPI_STAT_RXOV ((uint32_t) (1 << 2)) /* Data comes while receiver buffer is in used */

Definition at line 115 of file spi_002.h.

#define SPI_STAT_RXRDY ((uint32_t) (1 << 0)) /* Data is ready for read */

Definition at line 111 of file spi_002.h.

#define SPI_STAT_SSA ((uint32_t) (1 << 4)) /* There is SSEL transition from deasserted to asserted */

Definition at line 119 of file spi_002.h.

#define SPI_STAT_SSD ((uint32_t) (1 << 5)) /* There is SSEL transition from asserted to deasserted */

Definition at line 121 of file spi_002.h.

#define SPI_STAT_STALLED ((uint32_t) (1 << 6)) /* SPI is currently in a stall condition. */

Definition at line 123 of file spi_002.h.

#define SPI_STAT_TXRDY ((uint32_t) (1 << 1)) /* Data may be written to transmit buffer */

Definition at line 113 of file spi_002.h.

#define SPI_STAT_TXUR ((uint32_t) (1 << 3)) /* There is no data to be sent in the next input clock */

Definition at line 117 of file spi_002.h.

#define SPI_TXCTL_ASSERT_SSEL ((uint32_t) 0)

Definition at line 220 of file spi_002.h.

#define SPI_TXCTL_BITMASK ((uint32_t) 0xF71FF00)

Macro defines for SPI Transmitter Control register

Definition at line 218 of file spi_002.h.

#define SPI_TXCTL_DEASSERT_SSEL ((uint32_t) (1 << 16))

Definition at line 221 of file spi_002.h.

#define SPI_TXCTL_EOF ((uint32_t) (1 << 21)) /* This is the last part of the current frame */

End of Frame flag (FRAME_DELAY is applied after sending the current part)

Definition at line 225 of file spi_002.h.

#define SPI_TXCTL_EOT ((uint32_t) (1 << 20)) /* This is the last frame of the current transfer */

End of Transfer flag (TRANSFER_DELAY is applied after sending the current frame)

Definition at line 223 of file spi_002.h.

#define SPI_TXCTL_FLEN | ( |  | n | ) | ((uint32_t) (((n) & 0x0F) << 24)) /* Frame Length -1 */

Receive Ignore Flag

Definition at line 229 of file spi_002.h.

#define SPI_TXCTL_RXIGNORE ((uint32_t) (1 << 22)) /* Received data is ignored */

Receive Ignore Flag

Definition at line 227 of file spi_002.h.

#define SPI_TXDAT_DATA | ( |  | n | ) | ((uint32_t) ((n) & 0xFFFF))

Macro defines for SPI Transmitter Data Register

Definition at line 212 of file spi_002.h.

#define SPI_TXDATCTL_ASSERT_SSEL ((uint32_t) 0)

Definition at line 197 of file spi_002.h.

#define SPI_TXDATCTL_BITMASK ((uint32_t) 0xF71FFFF)

Macro defines for SPI Transmitter Data and Control register

Definition at line 193 of file spi_002.h.

#define SPI_TXDATCTL_DATA | ( |  | n | ) | ((uint32_t) ((n) & 0xFFFF))

Definition at line 195 of file spi_002.h.

#define SPI_TXDATCTL_DEASSERT_SSEL ((uint32_t) (1 << 16))

Definition at line 198 of file spi_002.h.

#define SPI_TXDATCTL_EOF ((uint32_t) (1 << 21)) /* This is the last part of the current frame */

End of Frame flag (FRAME_DELAY is applied after sending the current part)

Definition at line 202 of file spi_002.h.

#define SPI_TXDATCTL_EOT ((uint32_t) (1 << 20)) /* This is the last frame of the current transfer */

End of Transfer flag (TRANSFER_DELAY is applied after sending the current frame)

Definition at line 200 of file spi_002.h.

#define SPI_TXDATCTL_FLEN | ( |  | n | ) | ((uint32_t) (((n) & 0x0F) << 24)) /* Frame Length -1 */

Receive Ignore Flag

Definition at line 206 of file spi_002.h.

#define SPI_TXDATCTL_RXIGNORE ((uint32_t) (1 << 22)) /* Received data is ignored */

Receive Ignore Flag

Definition at line 204 of file spi_002.h.

## Enumeration Type Documentation

enum IP_SPI_CLOCK_MODE_T

SPI Clock Mode.

Enumerator:

  SPI_CLOCK_CPHA0_CPOL0 | CPHA = 0, CPOL = 0
  SPI_CLOCK_CPHA0_CPOL1 | CPHA = 0, CPOL = 1
  SPI_CLOCK_CPHA1_CPOL0 | CPHA = 1, CPOL = 0
  SPI_CLOCK_CPHA1_CPOL1 | CPHA = 1, CPOL = 1
  SPI_CLOCK_MODE0 | alias
  SPI_CLOCK_MODE1 | alias
  SPI_CLOCK_MODE2 | alias
  SPI_CLOCK_MODE3 | alias
  SPI_CLOCK_CPHA0_CPOL0 | CPHA = 0, CPOL = 0
  SPI_CLOCK_CPHA0_CPOL1 | CPHA = 0, CPOL = 1
  SPI_CLOCK_CPHA1_CPOL0 | CPHA = 1, CPOL = 0
  SPI_CLOCK_CPHA1_CPOL1 | CPHA = 1, CPOL = 1
  SPI_CLOCK_MODE0 | alias
  SPI_CLOCK_MODE1 | alias
  SPI_CLOCK_MODE2 | alias
  SPI_CLOCK_MODE3 | alias

Definition at line 262 of file spi_002.h.

enum IP_SPI_DATA_ORDER_T

SPI Data Order Mode.

Enumerator:

  SPI_DATA_MSB_FIRST |
  SPI_DATA_LSB_FIRST |
  SPI_DATA_MSB_FIRST |
  SPI_DATA_LSB_FIRST |

Definition at line 274 of file spi_002.h.

enum IP_SPI_MODE_T

SPI Mode.

Enumerator:

  SPI_MODE_MASTER |
  SPI_MODE_SLAVE |
  SPI_MODE_MASTER |
  SPI_MODE_SLAVE |

Definition at line 256 of file spi_002.h.

enum IP_SPI_SSEL_POL_T

SPI SSEL Polarity definition.

Enumerator:

  SPI_SSEL_ACTIVE_LO |
  SPI_SSEL_ACTIVE_HI |

Definition at line 280 of file spi_002.h.

## Function Documentation

STATIC INLINE void IP_SPI_ClearStatus | ( | IP_SPI_002_T * | pSPI,
|  | uint32_t | Flag
| ) |  |

Clear SPI status.

Parameters

  pSPI | : The base of SPI peripheral on the chip
  Flag | : Clear Flag (Or-ed bit value of SPI_STAT_CLR_*)

Returns
  Nothing

Definition at line 387 of file spi_002.h.

STATIC INLINE void IP_SPI_DeInit | ( | IP_SPI_002_T * | pSPI | ) |

Deinitialise the SPI.

Parameters

  pSPI | : The base of SPI peripheral on the chip

Returns
  Nothing

Note
  The SPI controller is disabled

Definition at line 332 of file spi_002.h.

void IP_SPI_DelayConfig | ( | IP_SPI_002_T * | pSPI,
|  | IP_SPI_DELAY_CONFIG_T * | pConfig
| ) |  |

Configure the SPI Delay parameters.

Parameters

  pSPI | : The base of SPI peripheral on the chip
  pConfig | : Pointer to SPI Delay configuration structure

Returns
  Nothing

Note
  The SPI controller is disabled

Definition at line 77 of file spi_002.c.

STATIC INLINE void IP_SPI_Disable | ( | IP_SPI_002_T * | pSPI | ) |

Disable SPI peripheral.

Parameters

  pSPI | : The base of SPI peripheral on the chip

Returns
  Nothing

Definition at line 321 of file spi_002.h.

STATIC INLINE void IP_SPI_DisableLoopBack | ( | IP_SPI_002_T * | pSPI | ) |

Disable loopback mode.

Parameters

  pSPI | : The base of SPI peripheral on the chip

Returns
  Nothing

Note
  Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin

Definition at line 356 of file spi_002.h.

STATIC INLINE void IP_SPI_Enable | ( | IP_SPI_002_T * | pSPI | ) |

Enable SPI peripheral.

Parameters

  pSPI | : The base of SPI peripheral on the chip

Returns
  Nothing

Definition at line 311 of file spi_002.h.

STATIC INLINE void IP_SPI_EnableLoopBack | ( | IP_SPI_002_T * | pSPI | ) |

Enable loopback mode.

Parameters

  pSPI | : The base of SPI peripheral on the chip

Returns
  Nothing

Note
  Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin

Definition at line 344 of file spi_002.h.

STATIC INLINE void IP_SPI_ForceEOT | ( | IP_SPI_002_T * | pSPI | ) |

Force to end of transfer.

Parameters

  pSPI | : The base of SPI peripheral on the chip

Returns
  Nothing

Definition at line 376 of file spi_002.h.

STATIC INLINE uint32_t IP_SPI_GetIntStatus | ( | IP_SPI_002_T * | pSPI | ) |

Get the masked interrupt status.

Parameters

  pSPI | : The base of SPI peripheral on the chip

Returns
  SPI Status (Or-ed bit value of SPI_INTSTAT*)

Note
  The return value contains a 1 for each interrupt condition that is asserted and enabled (masked)

Definition at line 420 of file spi_002.h.

STATIC INLINE uint32_t IP_SPI_GetStatus | ( | IP_SPI_002_T * | pSPI | ) |

Get the current status of SPI controller.

Parameters

  pSPI | : The base of SPI peripheral on the chip

Returns
  SPI Status (Or-ed bit value of SPI_STAT_*)

Definition at line 366 of file spi_002.h.

void IP_SPI_Init | ( | IP_SPI_002_T * | pSPI,
|  | IP_SPI_CONFIG_T * | pConfig
| ) |  |

Initialise the SPI.

Parameters

  pSPI | : The base of SPI peripheral on the chip
  pConfig | : Pointer to SPI Configuration structure

Returns
  Nothing

Note
  The SPI controller is disabled

Definition at line 51 of file spi_002.c.

STATIC INLINE void IP_SPI_IntDisable | ( | IP_SPI_002_T * | pSPI,
|  | uint32_t | IntDisMsk
| ) |  |

Disable the interrupt(s) for the SPI.

Parameters

  pSPI | : The base of SPI peripheral on the chip
  IntDisMsk | : Mask of interrupts disabled (Or-ed bit value of SPI_INTENCLR_*)

Returns
  Nothing

Definition at line 409 of file spi_002.h.

STATIC INLINE void IP_SPI_IntEnable | ( | IP_SPI_002_T * | pSPI,
|  | uint32_t | IntEnMsk
| ) |  |

Enable the interrupt(s) for the SPI.

Parameters

  pSPI | : The base of SPI peripheral on the chip
  IntEnMsk | : Mask of interrupts enabled (Or-ed bit value of SPI_INTENSET_*)

Returns
  Nothing

Definition at line 398 of file spi_002.h.

STATIC INLINE uint16_t IP_SPI_ReceiveFrame | ( | IP_SPI_002_T * | pSPI | ) |

Get received SPI data.

Parameters

  pSPI | : The base of SPI peripheral on the chip

Returns
  receive data

Definition at line 468 of file spi_002.h.

STATIC INLINE void IP_SPI_SendFrame | ( | IP_SPI_002_T * | pSPI,
|  | uint16_t | data
| ) |  |

Send SPI 16-bit data.

Parameters

  pSPI | : The base of SPI peripheral on the chip
  data | : Transmit Data

Note
  The control information is not changing during the transfer

Returns
  Nothing

Definition at line 432 of file spi_002.h.

STATIC INLINE void IP_SPI_SendFrameAndControl | ( | IP_SPI_002_T * | pSPI,
|  | uint16_t | TxData,
|  | uint8_t | Flen,
|  | uint32_t | Flag
| ) |  |

Send SPI 16-bit data and control information simutaneously.

Parameters

  pSPI | : The base of SPI peripheral on the chip
  TxData | : Transmit Data
  Flen | : Data size (1-16)
  Flag | : Flag control (Or-ed values of SPI_TXCTL_*)

Returns
  Nothing

Definition at line 458 of file spi_002.h.

STATIC INLINE void IP_SPI_SetControlInfo | ( | IP_SPI_002_T * | pSPI,
|  | uint8_t | Flen,
|  | uint32_t | Flag
| ) |  |

Set control information including SSEL, EOT, EOF RXIGNORE and FLEN.

Parameters

  pSPI | : The base of SPI peripheral on the chip
  Flen | : Data size (1-16)
  Flag | : Flag control (Or-ed values of SPI_TXCTL_*)

Note
  The control information has no effect unless data is later written to TXDAT

Returns
  Nothing

Definition at line 445 of file spi_002.h.