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clock_13xx.h
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1 /*
2 * @brief LPC13XX Clock control functions
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __CLOCK_13XX_H_
33 #define __CLOCK_13XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
58 #define SYSCTL_IRC_FREQ (12000000)
59
67 STATIC INLINE void Chip_Clock_SetupSystemPLL(uint8_t msel, uint8_t psel)
68 {
69 LPC_SYSCTL->SYSPLLCTRL = (msel & 0x1F) | ((psel & 0x3) << 5);
70 }
71
76 STATIC INLINE bool Chip_Clock_IsSystemPLLLocked(void)
77 {
78 return (bool) ((LPC_SYSCTL->SYSPLLSTAT & 1) != 0);
79 }
80
84 typedef enum CHIP_SYSCTL_PLLCLKSRC {
85 SYSCTL_PLLCLKSRC_IRC = 0,
86 SYSCTL_PLLCLKSRC_SYSOSC,
87 SYSCTL_PLLCLKSRC_RESERVED1,
88 SYSCTL_PLLCLKSRC_RESERVED2,
89 } CHIP_SYSCTL_PLLCLKSRC_T;
90
98 void Chip_Clock_SetSystemPllSource(CHIP_SYSCTL_PLLCLKSRC_T src);
99
107 STATIC INLINE void Chip_Clock_SetupUSBPLL(uint8_t msel, uint8_t psel)
108 {
109 LPC_SYSCTL->USBPLLCTRL = (msel & 0x1F) | ((psel & 0x3) << 5);
110 }
111
116 STATIC INLINE bool Chip_Clock_IsUSBPLLLocked(void)
117 {
118 return (bool) ((LPC_SYSCTL->USBPLLSTAT & 1) != 0);
119 }
120
128 void Chip_Clock_SetUSBPllSource(CHIP_SYSCTL_PLLCLKSRC_T src);
129
139 void Chip_Clock_SetPLLBypass(bool bypass, bool highfr);
140
144 typedef enum CHIP_WDTLFO_OSC {
145 WDTLFO_OSC_ILLEGAL,
146 WDTLFO_OSC_0_60,
147 WDTLFO_OSC_1_05,
148 WDTLFO_OSC_1_40,
149 WDTLFO_OSC_1_75,
150 WDTLFO_OSC_2_10,
151 WDTLFO_OSC_2_40,
152 WDTLFO_OSC_2_70,
153 WDTLFO_OSC_3_00,
154 WDTLFO_OSC_3_25,
155 WDTLFO_OSC_3_50,
156 WDTLFO_OSC_3_75,
157 WDTLFO_OSC_4_00,
158 WDTLFO_OSC_4_20,
159 WDTLFO_OSC_4_40,
160 WDTLFO_OSC_4_60
161 } CHIP_WDTLFO_OSC_T;
162
170 STATIC INLINE void Chip_Clock_SetWDTOSC(CHIP_WDTLFO_OSC_T wdtclk, uint8_t div)
171 {
172 LPC_SYSCTL->WDTOSCCTRL = (((uint32_t) wdtclk) << 5) | ((div >> 1) - 1);
173 }
174
178 typedef enum CHIP_SYSCTL_MAINCLKSRC{
179 SYSCTL_MAINCLKSRC_IRC = 0,
180 SYSCTL_MAINCLKSRC_PLLIN,
181 SYSCTL_MAINCLKSRC_WDTOSC,
182 SYSCTL_MAINCLKSRC_PLLOUT,
183 } CHIP_SYSCTL_MAINCLKSRC_T;
184
192 void Chip_Clock_SetMainClockSource(CHIP_SYSCTL_MAINCLKSRC_T src);
193
198 STATIC INLINE CHIP_SYSCTL_MAINCLKSRC_T Chip_Clock_GetMainClockSource(void)
199 {
200 return (CHIP_SYSCTL_MAINCLKSRC_T) (LPC_SYSCTL->MAINCLKSEL);
201 }
202
210 STATIC INLINE void Chip_Clock_SetSysClockDiv(uint32_t div)
211 {
212 LPC_SYSCTL->SYSAHBCLKDIV = div;
213 }
214
218 typedef enum CHIP_SYSCTL_CLOCK{
219 SYSCTL_CLOCK_SYS = 0,
220 SYSCTL_CLOCK_ROM,
221 SYSCTL_CLOCK_RAM,
222 SYSCTL_CLOCK_FLASHREG,
223 SYSCTL_CLOCK_FLASHARRAY,
224 SYSCTL_CLOCK_I2C,
225 SYSCTL_CLOCK_GPIO,
226 SYSCTL_CLOCK_CT16B0,
227 SYSCTL_CLOCK_CT16B1,
228 SYSCTL_CLOCK_CT32B0,
229 SYSCTL_CLOCK_CT32B1,
230 SYSCTL_CLOCK_SSP0,
231 SYSCTL_CLOCK_UART0,
232 SYSCTL_CLOCK_ADC,
233 SYSCTL_CLOCK_USB,
234 SYSCTL_CLOCK_WDT,
235 SYSCTL_CLOCK_IOCON,
236 SYSCTL_CLOCK_RESERVED17,
237 SYSCTL_CLOCK_SSP1,
238 #if defined(CHIP_LPC1347)
239 SYSCTL_CLOCK_PINT,
240 SYSCTL_CLOCK_RESERVED20,
241 SYSCTL_CLOCK_RESERVED21,
242 SYSCTL_CLOCK_RESERVED22,
243 SYSCTL_CLOCK_GROUP0INT,
244 SYSCTL_CLOCK_GROUP1INT,
245 SYSCTL_CLOCK_RESERVED25,
246 SYSCTL_CLOCK_RAM1,
247 SYSCTL_CLOCK_USBRAM,
248 #endif
249 } CHIP_SYSCTL_CLOCK_T;
250
256 STATIC INLINE void Chip_Clock_EnablePeriphClock(CHIP_SYSCTL_CLOCK_T clk)
257 {
258 LPC_SYSCTL->SYSAHBCLKCTRL |= (1 << clk);
259 }
260
266 STATIC INLINE void Chip_Clock_DisablePeriphClock(CHIP_SYSCTL_CLOCK_T clk)
267 {
268 LPC_SYSCTL->SYSAHBCLKCTRL &= ~(1 << clk);
269 }
270
278 STATIC INLINE void Chip_Clock_SetSSP0ClockDiv(uint32_t div)
279 {
280 LPC_SYSCTL->SSP0CLKDIV = div;
281 }
282
288 STATIC INLINE uint32_t Chip_Clock_GetSSP0ClockDiv(void)
289 {
290 return LPC_SYSCTL->SSP0CLKDIV;
291 }
292
302 STATIC INLINE void Chip_Clock_SetUARTClockDiv(uint32_t div)
303 {
304 LPC_SYSCTL->USARTCLKDIV = div;
305 }
306
312 STATIC INLINE uint32_t Chip_Clock_GetUARTClockDiv(void)
313 {
314 return LPC_SYSCTL->USARTCLKDIV;
315 }
316
324 STATIC INLINE void Chip_Clock_SetSSP1ClockDiv(uint32_t div)
325 {
326 LPC_SYSCTL->SSP1CLKDIV = div;
327 }
328
334 STATIC INLINE uint32_t Chip_Clock_GetSSP1ClockDiv(void)
335 {
336 return LPC_SYSCTL->SSP1CLKDIV;
337 }
338
346 STATIC INLINE void Chip_Clock_SetTraceClockDiv(uint32_t div)
347 {
348 LPC_SYSCTL->TRACECLKDIV = div;
349 }
350
356 STATIC INLINE uint32_t Chip_Clock_GetTraceClockDiv(void)
357 {
358 return LPC_SYSCTL->TRACECLKDIV;
359 }
360
368 STATIC INLINE void Chip_Clock_SetSystickClockDiv(uint32_t div)
369 {
370 LPC_SYSCTL->SYSTICKCLKDIV = div;
371 }
372
378 STATIC INLINE uint32_t Chip_Clock_GetSystickClockDiv(void)
379 {
380 return LPC_SYSCTL->SYSTICKCLKDIV;
381 }
382
386 typedef enum CHIP_SYSCTL_USBCLKSRC{
387 SYSCTL_USBCLKSRC_PLLOUT = 0,
388 SYSCTL_USBCLKSRC_MAINSYSCLK,
389 } CHIP_SYSCTL_USBCLKSRC_T;
390
401 void Chip_Clock_SetUSBClockSource(CHIP_SYSCTL_USBCLKSRC_T src, uint32_t div);
402
403 #if defined(CHIP_LPC1343)
404
407 typedef enum CHIP_SYSCTL_WDTCLKSRC{
408 SYSCTL_WDTCLKSRC_IRC = 0,
409 SYSCTL_WDTCLKSRC_MAINSYSCLK,
410 SYSCTL_WDTCLKSRC_WDTOSC,
411 } CHIP_SYSCTL_WDTCLKSRC_T;
412
423 void Chip_Clock_SetWDTClockSource(CHIP_SYSCTL_WDTCLKSRC_T src, uint32_t div);
424
425 #endif
426
430 typedef enum CHIP_SYSCTL_CLKOUTSRC{
431 SYSCTL_CLKOUTSRC_IRC = 0,
432 SYSCTL_CLKOUTSRC_SYSOSC,
433 SYSCTL_CLKOUTSRC_WDTOSC,
434 SYSCTL_CLKOUTSRC_MAINSYSCLK,
435 } CHIP_SYSCTL_CLKOUTSRC_T;
436
447 void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div);
448
453 STATIC INLINE uint32_t Chip_Clock_GetMainOscRate(void)
454 {
455 return CRYSTAL_MAIN_FREQ_IN;
456 }
457
462 STATIC INLINE uint32_t Chip_Clock_GetIntOscRate(void)
463 {
464 return SYSCTL_IRC_FREQ;
465 }
466
472 uint32_t Chip_Clock_GetWDTOSCRate(void);
473
478 uint32_t Chip_Clock_GetSystemPllInClockRate(void);
479
484 uint32_t Chip_Clock_GetSystemPllOutClockRate(void);
485
490 uint32_t Chip_Clock_GetUSBPllInClockRate(void);
491
496 uint32_t Chip_Clock_GetUSBPllOutClockRate(void);
497
502 uint32_t Chip_Clock_GetMainClockRate(void);
503
508 uint32_t Chip_Clock_GetSystemClockRate(void);
509
514 #ifdef __cplusplus
515 }
516 #endif
517
518 #endif /* __CLOCK_13XX_H_ */