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sdmmc_001.h
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1 /*
2 * @brief SD/SDIO (MCI) registers and control functions
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __SDMMC_001_H_
33 #define __SDMMC_001_H_
34
35 #include "sys_config.h"
36 #include "cmsis.h"
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
50 typedef struct {
51 __IO uint32_t CTRL;
52 __IO uint32_t PWREN;
53 __IO uint32_t CLKDIV;
54 __IO uint32_t CLKSRC;
55 __IO uint32_t CLKENA;
56 __IO uint32_t TMOUT;
57 __IO uint32_t CTYPE;
58 __IO uint32_t BLKSIZ;
59 __IO uint32_t BYTCNT;
60 __IO uint32_t INTMASK;
61 __IO uint32_t CMDARG;
62 __IO uint32_t CMD;
63 __I uint32_t RESP0;
64 __I uint32_t RESP1;
65 __I uint32_t RESP2;
66 __I uint32_t RESP3;
67 __I uint32_t MINTSTS;
68 __IO uint32_t RINTSTS;
69 __I uint32_t STATUS;
70 __IO uint32_t FIFOTH;
71 __I uint32_t CDETECT;
72 __I uint32_t WRTPRT;
73 __IO uint32_t GPIO;
74 __I uint32_t TCBCNT;
75 __I uint32_t TBBCNT;
76 __IO uint32_t DEBNCE;
77 __IO uint32_t USRID;
78 __I uint32_t VERID;
79 __I uint32_t RESERVED0;
80 __IO uint32_t UHS_REG;
81 __IO uint32_t RST_N;
82 __I uint32_t RESERVED1;
83 __IO uint32_t BMOD;
84 __O uint32_t PLDMND;
85 __IO uint32_t DBADDR;
86 __IO uint32_t IDSTS;
87 __IO uint32_t IDINTEN;
88 __I uint32_t DSCADDR;
89 __I uint32_t BUFADDR;
90 } IP_SDMMC_001_T;
91
94 #define MCI_DMADES0_OWN (1UL << 31)
95 #define MCI_DMADES0_CES (1 << 30)
96 #define MCI_DMADES0_ER (1 << 5)
97 #define MCI_DMADES0_CH (1 << 4)
98 #define MCI_DMADES0_FS (1 << 3)
99 #define MCI_DMADES0_LD (1 << 2)
100 #define MCI_DMADES0_DIC (1 << 1)
104 #define MCI_DMADES1_BS1(x) (x)
105 #define MCI_DMADES1_BS2(x) ((x) << 13)
106 #define MCI_DMADES1_MAXTR 4096
110 #define MCI_CTRL_USE_INT_DMAC (1 << 25)
111 #define MCI_CTRL_CARDV_MASK (0x7 << 16)
112 #define MCI_CTRL_CEATA_INT_EN (1 << 11)
113 #define MCI_CTRL_SEND_AS_CCSD (1 << 10)
114 #define MCI_CTRL_SEND_CCSD (1 << 9)
115 #define MCI_CTRL_ABRT_READ_DATA (1 << 8)
116 #define MCI_CTRL_SEND_IRQ_RESP (1 << 7)
117 #define MCI_CTRL_READ_WAIT (1 << 6)
118 #define MCI_CTRL_INT_ENABLE (1 << 4)
119 #define MCI_CTRL_DMA_RESET (1 << 2)
120 #define MCI_CTRL_FIFO_RESET (1 << 1)
121 #define MCI_CTRL_RESET (1 << 0)
125 #define MCI_POWER_ENABLE 0x1
129 #define MCI_CLOCK_DIVIDER(dn, d2) ((d2) << ((dn) * 8))
133 #define MCI_CLKSRC_CLKDIV0 0
134 #define MCI_CLKSRC_CLKDIV1 1
135 #define MCI_CLKSRC_CLKDIV2 2
136 #define MCI_CLKSRC_CLKDIV3 3
137 #define MCI_CLK_SOURCE(clksrc) (clksrc)
141 #define MCI_CLKEN_LOW_PWR (1 << 16)
142 #define MCI_CLKEN_ENABLE (1 << 0)
146 #define MCI_TMOUT_DATA(clks) ((clks) << 8)
147 #define MCI_TMOUT_DATA_MSK 0xFFFFFF00
148 #define MCI_TMOUT_RESP(clks) ((clks) & 0xFF)
149 #define MCI_TMOUT_RESP_MSK 0xFF
150
153 #define MCI_CTYPE_8BIT (1 << 16)
154 #define MCI_CTYPE_4BIT (1 << 0)
158 #define MCI_INT_SDIO (1 << 16)
159 #define MCI_INT_EBE (1 << 15)
160 #define MCI_INT_ACD (1 << 14)
161 #define MCI_INT_SBE (1 << 13)
162 #define MCI_INT_HLE (1 << 12)
163 #define MCI_INT_FRUN (1 << 11)
164 #define MCI_INT_HTO (1 << 10)
165 #define MCI_INT_DTO (1 << 9)
166 #define MCI_INT_RTO (1 << 8)
167 #define MCI_INT_DCRC (1 << 7)
168 #define MCI_INT_RCRC (1 << 6)
169 #define MCI_INT_RXDR (1 << 5)
170 #define MCI_INT_TXDR (1 << 4)
171 #define MCI_INT_DATA_OVER (1 << 3)
172 #define MCI_INT_CMD_DONE (1 << 2)
173 #define MCI_INT_RESP_ERR (1 << 1)
174 #define MCI_INT_CD (1 << 0)
178 #define MCI_CMD_START (1UL << 31)
179 #define MCI_CMD_VOLT_SWITCH (1 << 28)
180 #define MCI_CMD_BOOT_MODE (1 << 27)
181 #define MCI_CMD_DISABLE_BOOT (1 << 26)
182 #define MCI_CMD_EXPECT_BOOT_ACK (1 << 25)
183 #define MCI_CMD_ENABLE_BOOT (1 << 24)
184 #define MCI_CMD_CCS_EXP (1 << 23)
185 #define MCI_CMD_CEATA_RD (1 << 22)
186 #define MCI_CMD_UPD_CLK (1 << 21)
187 #define MCI_CMD_INIT (1 << 15)
188 #define MCI_CMD_STOP (1 << 14)
189 #define MCI_CMD_PRV_DAT_WAIT (1 << 13)
190 #define MCI_CMD_SEND_STOP (1 << 12)
191 #define MCI_CMD_STRM_MODE (1 << 11)
192 #define MCI_CMD_DAT_WR (1 << 10)
193 #define MCI_CMD_DAT_EXP (1 << 9)
194 #define MCI_CMD_RESP_CRC (1 << 8)
195 #define MCI_CMD_RESP_LONG (1 << 7)
196 #define MCI_CMD_RESP_EXP (1 << 6)
197 #define MCI_CMD_INDX(n) ((n) & 0x1F)
198
201 #define MCI_STS_GET_FCNT(x) (((x) >> 17) & 0x1FF)
202
205 #define MCI_FIFOTH_TX_WM(x) ((x) & 0xFFF)
206 #define MCI_FIFOTH_RX_WM(x) (((x) & 0xFFF) << 16)
207 #define MCI_FIFOTH_DMA_MTS_1 (0UL << 28)
208 #define MCI_FIFOTH_DMA_MTS_4 (1UL << 28)
209 #define MCI_FIFOTH_DMA_MTS_8 (2UL << 28)
210 #define MCI_FIFOTH_DMA_MTS_16 (3UL << 28)
211 #define MCI_FIFOTH_DMA_MTS_32 (4UL << 28)
212 #define MCI_FIFOTH_DMA_MTS_64 (5UL << 28)
213 #define MCI_FIFOTH_DMA_MTS_128 (6UL << 28)
214 #define MCI_FIFOTH_DMA_MTS_256 (7UL << 28)
215
218 #define MCI_BMOD_PBL1 (0 << 8)
219 #define MCI_BMOD_PBL4 (1 << 8)
220 #define MCI_BMOD_PBL8 (2 << 8)
221 #define MCI_BMOD_PBL16 (3 << 8)
222 #define MCI_BMOD_PBL32 (4 << 8)
223 #define MCI_BMOD_PBL64 (5 << 8)
224 #define MCI_BMOD_PBL128 (6 << 8)
225 #define MCI_BMOD_PBL256 (7 << 8)
226 #define MCI_BMOD_DE (1 << 7)
227 #define MCI_BMOD_DSL(len) ((len) << 2)
228 #define MCI_BMOD_FB (1 << 1)
229 #define MCI_BMOD_SWR (1 << 0)
233 #define SD_FIFO_SZ 32
236 typedef uint32_t (*MCI_IRQ_CB_FUNC_T)(uint32_t);
237
239 typedef int32_t (*PSCHECK_FUNC_T)(void);
240
242 typedef void (*PS_POWER_FUNC_T)(int32_t enable);
243
246 typedef struct {
247 volatile uint32_t des0;
248 volatile uint32_t des1;
249 volatile uint32_t des2;
250 volatile uint32_t des3;
251 } pSDMMC_DMA_T;
252
255 typedef struct _sdif_device {
256 /* MCI_IRQ_CB_FUNC_T irq_cb; */
257 pSDMMC_DMA_T mci_dma_dd[1 + (0x100000 / MCI_DMADES1_MAXTR)];
258 /* uint32_t sdio_clk_rate; */
259 /* uint32_t sdif_slot_clk_rate; */
260 /* int32_t clock_enabled; */
261 } sdif_device;
262
268 void IP_SDMMC_Init(IP_SDMMC_001_T *pSDMMC);
269
275 void IP_SDMMC_DeInit(IP_SDMMC_001_T *pSDMMC);
276
283 void IP_SDMMC_SetBlkSize(IP_SDMMC_001_T *pSDMMC, uint32_t bytes);
284
293 void IP_SDMMC_Reset(IP_SDMMC_001_T *pSDMMC, int32_t reset);
294
301 STATIC INLINE void IP_SDMMC_PowerOn(IP_SDMMC_001_T *pSDMMC)
302 {
303 pSDMMC->PWREN = 1;
304 }
305
312 STATIC INLINE void IP_SDMMC_PowerOff(IP_SDMMC_001_T *pSDMMC)
313 {
314 pSDMMC->PWREN = 0;
315 }
316
324 STATIC INLINE int32_t IP_SDMMC_CardWpOn(IP_SDMMC_001_T *pSDMMC)
325 {
326 return (pSDMMC->WRTPRT & 1);
327 }
328
336 STATIC INLINE int32_t IP_SDMMC_CardNDetect(IP_SDMMC_001_T *pSDMMC)
337 {
338 return (pSDMMC->CDETECT & 1);
339 }
340
348 int32_t IP_SDMMC_SendCmd(IP_SDMMC_001_T *pSDMMC, uint32_t cmd, uint32_t arg);
349
356 void IP_SDMMC_GetResponse(IP_SDMMC_001_T *pSDMMC, uint32_t *resp);
357
365 void IP_SDMMC_SetClock(IP_SDMMC_001_T *pSDMMC, uint32_t clk_rate, uint32_t speed);
366
373 void IP_SDMMC_SetCardType(IP_SDMMC_001_T *pSDMMC, uint32_t ctype);
374
380 void IP_SDMMC_SetClearIntFifo(IP_SDMMC_001_T *pSDMMC);
381
387 uint32_t IP_SDMMC_GetRawIntStatus(IP_SDMMC_001_T *pSDMMC);
388
395 void IP_SDMMC_SetRawIntStatus(IP_SDMMC_001_T *pSDMMC, uint32_t iVal);
396
403 void IP_SDMMC_SetIntMask(IP_SDMMC_001_T *pSDMMC, uint32_t iVal);
404
413 void IP_SDMMC_DmaSetup(IP_SDMMC_001_T *pSDMMC, sdif_device *psdif_dev, uint32_t addr, uint32_t size);
414
421 void IP_SDMMC_SetBlkSizeByteCnt(IP_SDMMC_001_T *pSDMMC, uint32_t blk_size);
422
429 void IP_SDMMC_SetByteCnt(IP_SDMMC_001_T *pSDMMC, uint32_t bytes);
430
435 #ifdef __cplusplus
436 }
437 #endif
438
439 #endif /* __SDMMC_001_H_ */