| LPCOpen Platform v1.03 LPCOpen Platform for NXP LPC Microcontrollers

- Main Page
- Modules
- Data Structures
- Files
- Related Pages

- File List
- Globals

All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
Data Structures | Macros | Functions
enet_001.h File Reference
`#include "sys_config.h"`
`#include "cmsis.h"`

Go to the source code of this file.

## Data Structures
struct | IP_ENET_001_T
| 10/100 MII & RMII Ethernet with timestamping register block structure More...
struct | IP_ENET_001_TXDESC_T
| Structure of a transmit descriptor (without timestamp) More...
struct | IP_ENET_001_ENHTXDESC_T
| Structure of a enhanced transmit descriptor (with timestamp) More...
struct | IP_ENET_001_RXDESC_T
| Structure of a receive descriptor (without timestamp) More...
struct | IP_ENET_001_ENHRXDESC_T
| Structure of a enhanced receive descriptor (with timestamp) More...

## Macros
#define | MAC_CFG_RE (1 << 2)
| MAC_CONFIG register bit defines.
#define | MAC_CFG_TE (1 << 3)
#define | MAC_CFG_DF (1 << 4)
#define | MAC_CFG_BL(n) ((n) << 5)
#define | MAC_CFG_ACS (1 << 7)
#define | MAC_CFG_LUD (1 << 8)
#define | MAC_CFG_DR (1 << 9)
#define | MAC_CFG_IPC (1 << 10)
#define | MAC_CFG_DM (1 << 11)
#define | MAC_CFG_LM (1 << 12)
#define | MAC_CFG_DO (1 << 13)
#define | MAC_CFG_FES (1 << 14)
#define | MAC_CFG_PS (1 << 15)
#define | MAC_CFG_DCRS (1 << 16)
#define | MAC_CFG_IFG(n) ((n) << 17)
#define | MAC_CFG_JE (1 << 20)
#define | MAC_CFG_JD (1 << 22)
#define | MAC_CFG_WD (1 << 23)
#define | MAC_FF_PR (1 << 0)
| MAC_FRAME_FILTER register bit defines.
#define | MAC_FF_DAIF (1 << 3)
#define | MAC_FF_PM (1 << 4)
#define | MAC_FF_DBF (1 << 5)
#define | MAC_FF_PCF(n) ((n) << 6)
#define | MAC_FF_SAIF (1 << 8)
#define | MAC_FF_SAF (1 << 9)
#define | MAC_FF_RA (1UL << 31)
#define | MAC_MIIA_GB (1 << 0)
| MAC_MII_ADDR register bit defines.
#define | MAC_MIIA_W (1 << 1)
#define | MAC_MIIA_CR(n) ((n) << 2)
#define | MAC_MIIA_GR(n) ((n) << 6)
#define | MAC_MIIA_PA(n) ((n) << 11)
#define | MAC_MIID_GDMSK (0xFFFF)
| MAC_MII_DATA register bit defines.
#define | MAC_FC_FCB (1 << 0)
| MAC_FLOW_CONTROL register bit defines.
#define | MAC_FC_TFE (1 << 1)
#define | MAC_FC_RFE (1 << 2)
#define | MAC_FC_UP (1 << 3)
#define | MAC_FC_PLT(n) ((n) << 4)
#define | MAC_FC_DZPQ (1 << 7)
#define | MAC_FC_PT(n) ((n) << 16)
#define | MAC_VT_VL(n) ((n) << 0)
| MAC_VLAN_TAG register bit defines.
#define | MAC_VT_ETC (1 << 7)
#define | MAC_PMT_PD (1 << 0)
| MAC_PMT_CTRL_STAT register bit defines.
#define | MAC_PMT_MPE (1 << 1)
#define | MAC_PMT_WFE (1 << 2)
#define | MAC_PMT_MPR (1 << 5)
#define | MAC_PMT_WFR (1 << 6)
#define | MAC_PMT_GU (1 << 9)
#define | MAC_PMT_WFFRPR (1UL << 31)
#define | MAC_IM_PMT (1 << 3)
| MAC_INTR_MASK register bit defines.
#define | MAC_ADRH_MO (1UL << 31)
| MAC_ADDR0_HIGH register bit defines.
#define | MAC_ADRH_MO (1UL << 31)
| MAC_ADDR0_HIGH register bit defines.
#define | MAC_TS_TSENA (1 << 0)
| MAC_TIMESTAMP register bit defines.
#define | MAC_TS_TSCFUP (1 << 1)
#define | MAC_TS_TSINIT (1 << 2)
#define | MAC_TS_TSUPDT (1 << 3)
#define | MAC_TS_TSTRIG (1 << 4)
#define | MAC_TS_TSADDR (1 << 5)
#define | MAC_TS_TSENAL (1 << 8)
#define | MAC_TS_TSCTRL (1 << 9)
#define | MAC_TS_TSVER2 (1 << 10)
#define | MAC_TS_TSIPENA (1 << 11)
#define | MAC_TS_TSIPV6E (1 << 12)
#define | MAC_TS_TSIPV4E (1 << 13)
#define | MAC_TS_TSEVNT (1 << 14)
#define | MAC_TS_TSMSTR (1 << 15)
#define | MAC_TS_TSCLKT(n) ((n) << 16)
#define | MAC_TS_TSENMA (1 << 18)
#define | DMA_BM_SWR (1 << 0)
| DMA_BUS_MODE register bit defines.
#define | DMA_BM_DA (1 << 1)
#define | DMA_BM_DSL(n) ((n) << 2)
#define | DMA_BM_ATDS (1 << 7)
#define | DMA_BM_PBL(n) ((n) << 8)
#define | DMA_BM_PR(n) ((n) << 14)
#define | DMA_BM_FB (1 << 16)
#define | DMA_BM_RPBL(n) ((n) << 17)
#define | DMA_BM_USP (1 << 23)
#define | DMA_BM_PBL8X (1 << 24)
#define | DMA_BM_AAL (1 << 25)
#define | DMA_BM_MB (1 << 26)
#define | DMA_BM_TXPR (1 << 27)
#define | DMA_ST_TI (1 << 0)
| DMA_STAT register bit defines.
#define | DMA_ST_TPS (1 << 1)
#define | DMA_ST_TU (1 << 2)
#define | DMA_ST_TJT (1 << 3)
#define | DMA_ST_OVF (1 << 4)
#define | DMA_ST_UNF (1 << 5)
#define | DMA_ST_RI (1 << 6)
#define | DMA_ST_RU (1 << 7)
#define | DMA_ST_RPS (1 << 8)
#define | DMA_ST_RWT (1 << 9)
#define | DMA_ST_ETI (1 << 10)
#define | DMA_ST_FBI (1 << 13)
#define | DMA_ST_ERI (1 << 14)
#define | DMA_ST_AIE (1 << 15)
#define | DMA_ST_NIS (1 << 16)
#define | DMA_ST_ALL (0x1E7FF)
#define | DMA_OM_SR (1 << 1)
| DMA_OP_MODE register bit defines.
#define | DMA_OM_OSF (1 << 2)
#define | DMA_OM_RTC(n) ((n) << 3)
#define | DMA_OM_FUF (1 << 6)
#define | DMA_OM_FEF (1 << 7)
#define | DMA_OM_ST (1 << 13)
#define | DMA_OM_TTC(n) ((n) << 14)
#define | DMA_OM_FTF (1 << 20)
#define | DMA_OM_TSF (1 << 21)
#define | DMA_OM_DFF (1 << 24)
#define | DMA_OM_RSF (1 << 25)
#define | DMA_OM_DT (1 << 26)
#define | DMA_IE_TIE (1 << 0)
| DMA_INT_EN register bit defines.
#define | DMA_IE_TSE (1 << 1)
#define | DMA_IE_TUE (1 << 2)
#define | DMA_IE_TJE (1 << 3)
#define | DMA_IE_OVE (1 << 4)
#define | DMA_IE_UNE (1 << 5)
#define | DMA_IE_RIE (1 << 6)
#define | DMA_IE_RUE (1 << 7)
#define | DMA_IE_RSE (1 << 8)
#define | DMA_IE_RWE (1 << 9)
#define | DMA_IE_ETE (1 << 10)
#define | DMA_IE_FBE (1 << 13)
#define | DMA_IE_ERE (1 << 14)
#define | DMA_IE_AIE (1 << 15)
#define | DMA_IE_NIE (1 << 16)
#define | DMA_MFRM_FMCMSK (0xFFFF)
| DMA_MFRM_BUFOF register bit defines.
#define | DMA_MFRM_OC (1 << 16)
#define | DMA_MFRM_FMA(n) (((n) & 0x0FFE0000) >> 17)
#define | DMA_MFRM_OF (1 << 28)
#define | TDES_DB (1 << 0)
| Common TRAN_DESC_T and TRAN_DESC_ENH_T CTRLSTAT field bit defines.
#define | TDES_UF (1 << 1)
#define | TDES_ED (1 << 2)
#define | TDES_CCMSK(n) (((n) & 0x000000F0) >> 3)
#define | TDES_VF (1 << 7)
#define | TDES_EC (1 << 8)
#define | TDES_LC (1 << 9)
#define | TDES_NC (1 << 10)
#define | TDES_LCAR (1 << 11)
#define | TDES_IPE (1 << 12)
#define | TDES_FF (1 << 13)
#define | TDES_JT (1 << 14)
#define | TDES_ES (1 << 15)
#define | TDES_IHE (1 << 16)
#define | TDES_TTSS (1 << 17)
#define | TDES_OWN (1UL << 31)
#define | TDES_ENH_IC (1UL << 30)
| TRAN_DESC_ENH_T only CTRLSTAT field bit defines.
#define | TDES_ENH_LS (1 << 29)
#define | TDES_ENH_FS (1 << 28)
#define | TDES_ENH_DC (1 << 27)
#define | TDES_ENH_DP (1 << 26)
#define | TDES_ENH_TTSE (1 << 25)
#define | TDES_ENH_CIC(n) ((n) << 22)
#define | TDES_ENH_TER (1 << 21)
#define | TDES_ENH_TCH (1 << 20)
#define | TDES_NORM_IC (1UL << 31)
| TRAN_DESC_T only BSIZE field bit defines.
#define | TDES_NORM_FS (1 << 30)
#define | TDES_NORM_LS (1 << 29)
#define | TDES_NORM_CIC(n) ((n) << 27)
#define | TDES_NORM_DC (1 << 26)
#define | TDES_NORM_TER (1 << 25)
#define | TDES_NORM_TCH (1 << 24)
#define | TDES_NORM_DP (1 << 23)
#define | TDES_NORM_TTSE (1 << 22)
#define | TDES_NORM_BS2(n) (((n) & 0x3FF) << 11)
#define | TDES_NORM_BS1(n) (((n) & 0x3FF) << 0)
#define | TDES_ENH_BS2(n) (((n) & 0xFFF) << 16)
| TRAN_DESC_ENH_T only BSIZE field bit defines.
#define | TDES_ENH_BS1(n) (((n) & 0xFFF) << 0)
#define | RDES_ESA (1 << 0)
| Common REC_DESC_T and REC_DESC_ENH_T STATUS field bit defines.
#define | RDES_CE (1 << 1)
#define | RDES_DRE (1 << 2)
#define | RDES_RE (1 << 3)
#define | RDES_RWT (1 << 4)
#define | RDES_FT (1 << 5)
#define | RDES_LC (1 << 6)
#define | RDES_TSA (1 << 7)
#define | RDES_LS (1 << 8)
#define | RDES_FS (1 << 9)
#define | RDES_VLAN (1 << 10)
#define | RDES_OE (1 << 11)
#define | RDES_LE (1 << 12)
#define | RDES_SAF (1 << 13)
#define | RDES_DE (1 << 14)
#define | RDES_ES (1 << 15)
#define | RDES_FLMSK(n) (((n) & 0x3FFF0000) >> 16)
#define | RDES_AFM (1 << 30)
#define | RDES_OWN (1UL << 31)
#define | RDES_DINT (1UL << 31)
| Common REC_DESC_T and REC_DESC_ENH_T CTRL field bit defines.
#define | RDES_NORM_RER (1 << 25)
| REC_DESC_T pnly CTRL field bit defines.
#define | RDES_NORM_RCH (1 << 24)
#define | RDES_NORM_BS2(n) (((n) & 0x3FF) << 11)
#define | RDES_NORM_BS1(n) (((n) & 0x3FF) << 0)
#define | RDES_ENH_RER (1 << 15)
| REC_DESC_ENH_T only CTRL field bit defines.
#define | RDES_ENH_RCH (1 << 14)
#define | RDES_ENH_BS2(n) (((n) & 0xFFF) << 16)
#define | RDES_ENH_BS1(n) (((n) & 0xFFF) << 0)
#define | RDES_ENH_IPPL(n) (((n) & 0x7) >> 2)
| REC_DESC_ENH_T only EXTSTAT field bit defines.
#define | RDES_ENH_IPHE (1 << 3)
#define | RDES_ENH_IPPLE (1 << 4)
#define | RDES_ENH_IPCSB (1 << 5)
#define | RDES_ENH_IPV4 (1 << 6)
#define | RDES_ENH_IPV6 (1 << 7)
#define | RDES_ENH_MTMSK(n) (((n) & 0xF) >> 8)
#define | EMAC_ETH_MAX_FLEN (1536)
| Maximum size of an ethernet buffer.

## Functions
void | IP_ENET_Reset (IP_ENET_001_T *pENET)
| Resets the ethernet interface.
void | IP_ENET_SetADDR (IP_ENET_001_T *pENET, const uint8_t *macAddr)
| Sets the address of the interface.
void | IP_ENET_Init (IP_ENET_001_T *pENET)
| Initialize ethernet interface.
void | IP_ENET_SetupMII (IP_ENET_001_T *pENET, uint32_t div, uint8_t addr)
| Sets up the PHY link clock divider and PHY address.
void | IP_ENET_DeInit (IP_ENET_001_T *pENET)
| De-initialize the ethernet interface.
void | IP_ENET_StartMIIWrite (IP_ENET_001_T *pENET, uint8_t reg, uint16_t data)
| Starts a PHY write via the MII.
void | IP_ENET_StartMIIRead (IP_ENET_001_T *pENET, uint8_t reg)
| Starts a PHY read via the MII.
bool | IP_ENET_IsMIIBusy (IP_ENET_001_T *pENET)
| Returns MII link (PHY) busy status.
STATIC INLINE uint16_t | IP_ENET_ReadMIIData (IP_ENET_001_T *pENET)
| Returns the value read from the PHY.
STATIC INLINE void | IP_ENET_TXEnable (IP_ENET_001_T *pENET)
| Enables ethernet transmit.
STATIC INLINE void | IP_ENET_TXDisable (IP_ENET_001_T *pENET)
| Disables ethernet transmit.
STATIC INLINE void | IP_ENET_RXEnable (IP_ENET_001_T *pENET)
| Enables ethernet packet reception.
STATIC INLINE void | IP_ENET_RXDisable (IP_ENET_001_T *pENET)
| Disables ethernet packet reception.
void | IP_ENET_SetDuplex (IP_ENET_001_T *pENET, bool full)
| Sets full or half duplex for the interface.
void | IP_ENET_SetSpeed (IP_ENET_001_T *pENET, bool speed100)
| Sets speed for the interface.
void | IP_ENET_InitDescriptors (IP_ENET_001_T *pENET, IP_ENET_001_ENHTXDESC_T *pTXDescs, IP_ENET_001_ENHRXDESC_T *pRXDescs)
| Configures the initial ethernet descriptors.
STATIC INLINE void | IP_ENET_RXStart (IP_ENET_001_T *pENET)
| Starts receive polling of RX descriptors.
STATIC INLINE void | IP_ENET_TXStart (IP_ENET_001_T *pENET)
| Starts transmit polling of TX descriptors.