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can_17xx_40xx.h
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1 /*
2 * @brief LPC17xx/40xx CAN driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __CAN_17XX_40XX_H_
33 #define __CAN_17XX_40XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
44 #define CAN_SEG1_DEFAULT_VAL 5
45 #define CAN_SEG2_DEFAULT_VAL 4
46 #define CAN_SJW_DEFAULT_VAL 0
47
52 typedef IP_CAN_AF_LUT_T CANAF_LUT_T;
54 typedef IP_CAN_STD_ID_Entry_T CAN_STD_ID_ENTRY_T;
56 typedef IP_CAN_STD_ID_RANGE_Entry_T CAN_STD_ID_RANGE_ENTRY_T;
58 typedef IP_CAN_EXT_ID_Entry_T CAN_EXT_ID_ENTRY_T;
60 typedef IP_CAN_EXT_ID_RANGE_Entry_T CAN_EXT_ID_RANGE_ENTRY_T;
62 typedef IP_CAN_MSG_T CAN_MSG_T;
64 typedef IP_CAN_BUFFER_ID_T CAN_BUFFER_ID;
66 typedef IP_CAN_AF_RAM_SECTION_T CANAF_RAM_SECTION;
67
71 typedef enum CHIP_CAN_MODE {
72 CAN_RESET_MODE = CAN_MOD_RM,
73 CAN_SELFTEST_MODE = CAN_MOD_STM,
74 CAN_TEST_MODE = CAN_MOD_TM,
75 CAN_LISTEN_ONLY_MODE = CAN_MOD_LOM,
76 CAN_SLEEP_MODE = CAN_MOD_SM,
77 CAN_OPERATION_MODE = CAN_MOD_OPERATION,
78 CAN_TRANSMIT_PRIORITY_MODE = CAN_MOD_TPM,
79 CAN_RECEIVE_PRIORITY_MODE = CAN_MOD_RPM,
80 } CHIP_CAN_MODE_T;
81
85 typedef enum CHIP_CAN_AF_MODE {
86 CAN_AF_NORMAL_MODE = 0,
87 CAN_AF_OFF_MODE = CANAF_AFMR_ACCOFF,
88 CAN_AF_BYBASS_MODE = CANAF_AFMR_ACCBP,
89 CAN_AF_FULL_MODE = CANAF_AFMR_EFCAN,
90 } CHIP_CAN_AF_MODE_T;
91
97 STATIC INLINE uint32_t Chip_CAN_GetStatus(LPC_CAN_T *pCAN)
98 {
99 return IP_CAN_GetStatus(pCAN);
100 }
101
108 STATIC INLINE void Chip_CAN_IntEnable(LPC_CAN_T *pCAN, uint32_t IntMask)
109 {
110 IP_CAN_IntEnable(pCAN, IntMask);
111 }
112
119 STATIC INLINE void Chip_CAN_IntDisable(LPC_CAN_T *pCAN, uint32_t IntMask)
120 {
121 IP_CAN_IntDisable(pCAN, IntMask);
122 }
123
129 STATIC INLINE uint32_t Chip_CAN_GetIntStatus(LPC_CAN_T *pCAN)
130 {
131 return IP_CAN_GetIntStatus(pCAN);
132 }
133
140 STATIC INLINE void Chip_CAN_FullCANIntConfig(LPC_CANAF_T *pCANAF, FunctionalState NewState)
141 {
142 IP_CAN_FullCANIntConfig(pCANAF, NewState);
143 }
144
151 STATIC INLINE uint32_t Chip_CAN_GetFullCANIntStatus(LPC_CANAF_T *pCANAF, uint8_t ObjID)
152 {
153 return IP_CAN_GetFullCANIntStatus(pCANAF, ObjID);
154 }
155
163 STATIC INLINE void Chip_CAN_SetMode(LPC_CAN_T *pCAN, CHIP_CAN_MODE_T Mode, FunctionalState NewState)
164 {
165 IP_CAN_SetMode(pCAN, Mode, NewState);
166 }
167
174 STATIC INLINE void Chip_CAN_SetAFMode(LPC_CANAF_T *pCANAF, CHIP_CAN_AF_MODE_T AfMode)
175 {
176 IP_CAN_AF_SetMode(pCANAF, AfMode);
177 }
178
185 STATIC INLINE Status Chip_CAN_SetAFLUT(LPC_CANAF_T *pCANAF, CANAF_LUT_T *pAFSections)
186 {
187 return IP_CAN_SetAFLUT(pCANAF, LPC_CANAF_RAM, pAFSections);
188 }
189
196 STATIC INLINE Status Chip_CAN_InsertFullCANEntry(LPC_CANAF_T *pCANAF, CAN_STD_ID_ENTRY_T *pEntry)
197 {
198 return IP_CAN_InsertFullCANEntry(pCANAF, LPC_CANAF_RAM, pEntry);
199 }
200
207 STATIC INLINE Status Chip_CAN_InsertIndividualSTDEntry(LPC_CANAF_T *pCANAF, CAN_STD_ID_ENTRY_T *pEntry)
208 {
209 return IP_CAN_InsertIndividualSTDEntry(pCANAF, LPC_CANAF_RAM, pEntry);
210 }
211
218 STATIC INLINE Status Chip_CAN_InsertGroupSTDEntry(LPC_CANAF_T *pCANAF, CAN_STD_ID_RANGE_ENTRY_T *pEntry)
219 {
220 return IP_CAN_InsertGroupSTDEntry(pCANAF, LPC_CANAF_RAM, pEntry);
221 }
222
229 STATIC INLINE Status Chip_CAN_InsertIndividualEXTEntry(LPC_CANAF_T *pCANAF, CAN_EXT_ID_ENTRY_T *pEntry)
230 {
231 return IP_CAN_InsertIndividualEXTEntry(pCANAF, LPC_CANAF_RAM, pEntry);
232 }
233
240 STATIC INLINE Status Chip_CAN_InsertGroupEXTEntry(LPC_CANAF_T *pCANAF, CAN_EXT_ID_RANGE_ENTRY_T *pEntry)
241 {
242 return IP_CAN_InsertGroupEXTEntry(pCANAF, LPC_CANAF_RAM, pEntry);
243 }
244
251 STATIC INLINE Status Chip_CAN_RemoveFullCANEntry(LPC_CANAF_T *pCANAF, int16_t Position)
252 {
253 return IP_CAN_RemoveFullCANEntry(pCANAF, LPC_CANAF_RAM, Position);
254 }
255
262 STATIC INLINE Status Chip_CAN_RemoveIndividualSTDEntry(LPC_CANAF_T *pCANAF, int16_t Position)
263 {
264 return IP_CAN_RemoveIndividualSTDEntry(pCANAF, LPC_CANAF_RAM, Position);
265 }
266
273 STATIC INLINE Status Chip_CAN_RemoveGroupSTDEntry(LPC_CANAF_T *pCANAF, int16_t Position)
274 {
275 return IP_CAN_RemoveGroupSTDEntry(pCANAF, LPC_CANAF_RAM, Position);
276 }
277
284 STATIC INLINE Status Chip_CAN_RemoveIndividualEXTEntry(LPC_CANAF_T *pCANAF, int16_t Position)
285 {
286 return IP_CAN_RemoveIndividualEXTEntry(pCANAF, LPC_CANAF_RAM, Position);
287 }
288
295 STATIC INLINE Status Chip_CAN_RemoveGroupEXTEntry(LPC_CANAF_T *pCANAF, int16_t Position)
296 {
297 return IP_CAN_RemoveGroupEXTEntry(pCANAF, LPC_CANAF_RAM, Position);
298 }
299
306 STATIC INLINE uint16_t Chip_CAN_GetEntriesNum(LPC_CANAF_T *pCANAF, CANAF_RAM_SECTION SectionID)
307 {
308 return IP_CAN_GetEntriesNum(pCANAF, LPC_CANAF_RAM, SectionID);
309 }
310
318 STATIC INLINE Status Chip_CAN_ReadFullCANEntry(LPC_CANAF_T *pCANAF, uint16_t Position,
319 CAN_STD_ID_ENTRY_T *pEntry)
320 {
321 return IP_CAN_ReadFullCANEntry(pCANAF, LPC_CANAF_RAM, Position, pEntry);
322 }
323
331 STATIC INLINE Status Chip_CAN_ReadIndividualSTDEntry(LPC_CANAF_T *pCANAF, uint16_t Position,
332 CAN_STD_ID_ENTRY_T *pEntry)
333 {
334 return IP_CAN_ReadIndividualSTDEntry(pCANAF, LPC_CANAF_RAM, Position, pEntry);
335 }
336
344 STATIC INLINE Status Chip_CAN_ReadGroupSTDEntry(LPC_CANAF_T *pCANAF, uint16_t Position,
345 CAN_STD_ID_RANGE_ENTRY_T *pEntry)
346 {
347 return IP_CAN_ReadGroupSTDEntry(pCANAF, LPC_CANAF_RAM, Position, pEntry);
348 }
349
357 STATIC INLINE Status Chip_CAN_ReadIndividualEXTEntry(LPC_CANAF_T *pCANAF, uint16_t Position,
358 CAN_EXT_ID_ENTRY_T *pEntry)
359 {
360 return IP_CAN_ReadIndividualEXTEntry(pCANAF, LPC_CANAF_RAM, Position, pEntry);
361 }
362
370 STATIC INLINE Status Chip_CAN_ReadGroupEXTEntry(LPC_CANAF_T *pCANAF, uint16_t Position,
371 CAN_EXT_ID_RANGE_ENTRY_T *pEntry)
372 {
373 return IP_CAN_ReadGroupEXTEntry(pCANAF, LPC_CANAF_RAM, Position, pEntry);
374 }
375
382 STATIC INLINE Status Chip_CAN_Receive(LPC_CAN_T *pCAN, CAN_MSG_T *pMsg)
383 {
384 return IP_CAN_Receive(pCAN, pMsg);
385 }
386
395 STATIC INLINE Status Chip_CAN_FullCANReceive(LPC_CANAF_T *pCANAF, uint8_t ObjID, CAN_MSG_T *pMsg, uint8_t *pSCC)
396 {
397 return IP_CAN_FullCANReceive(pCANAF, LPC_CANAF_RAM, ObjID, pMsg, pSCC);
398 }
399
407 STATIC INLINE Status Chip_CAN_Send(LPC_CAN_T *pCAN, CAN_BUFFER_ID TxBufID, CAN_MSG_T *pMsg)
408 {
409 return IP_CAN_Send(pCAN, TxBufID, pMsg);
410 }
411
417 void Chip_CAN_Init(LPC_CAN_T *pCAN);
418
424 void Chip_CAN_DeInit(LPC_CAN_T *pCAN);
425
432 Status Chip_CAN_SetBitRate(LPC_CAN_T *pCAN, uint32_t BitRate);
433
439 CAN_BUFFER_ID Chip_CAN_GetFreeTxBuf(LPC_CAN_T *pCAN);
440
445 #ifdef __cplusplus
446 }
447 #endif
448
449 #endif /* __CAN_17XX_40XX_H_ */