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timer_001.h
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1 /*
2 * @brief 32-bit Timer/PWM registers and control functions
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __TIMER_001_H_
33 #define __TIMER_001_H_
34
35 #include "sys_config.h"
36 #include "cmsis.h"
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
50 typedef struct {
51 __IO uint32_t IR;
52 __IO uint32_t TCR;
53 __IO uint32_t TC;
54 __IO uint32_t PR;
55 __IO uint32_t PC;
56 __IO uint32_t MCR;
57 __IO uint32_t MR[4];
58 __IO uint32_t CCR;
59 __IO uint32_t CR[4];
60 __IO uint32_t EMR;
61 __I uint32_t RESERVED0[12];
62 __IO uint32_t CTCR;
63 #if defined(CHIP_LPC110X) || defined(CHIP_LPC11XXLV) || defined(CHIP_LPC11AXX) || \
64 defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
65 __IO uint32_t PWMC;
66 #endif
67 } IP_TIMER_001_T;
68
70 #define TIMER_IR_CLR(n) _BIT(n)
71
73 #define TIMER_MATCH_INT(n) (_BIT((n) & 0x0F))
74
75 #define TIMER_CAP_INT(n) (_BIT((((n) & 0x0F) + 4)))
76
78 #define TIMER_ENABLE ((uint32_t) (1 << 0))
79
80 #define TIMER_RESET ((uint32_t) (1 << 1))
81
83 #define TIMER_INT_ON_MATCH(n) (_BIT(((n) * 3)))
84
85 #define TIMER_RESET_ON_MATCH(n) (_BIT((((n) * 3) + 1)))
86
87 #define TIMER_STOP_ON_MATCH(n) (_BIT((((n) * 3) + 2)))
88
90 #define TIMER_CAP_RISING(n) (_BIT(((n) * 3)))
91
92 #define TIMER_CAP_FALLING(n) (_BIT((((n) * 3) + 1)))
93
94 #define TIMER_INT_ON_CAP(n) (_BIT((((n) * 3) + 2)))
95
104 STATIC INLINE bool IP_TIMER_MatchPending(IP_TIMER_001_T *pTimer, int8_t matchnum)
105 {
106 return (bool) ((pTimer->IR & TIMER_MATCH_INT(matchnum)) != 0);
107 }
108
117 STATIC INLINE bool IP_TIMER_CapturePending(IP_TIMER_001_T *pTimer, int8_t capnum)
118 {
119 return (bool) ((pTimer->IR & TIMER_CAP_INT(capnum)) != 0);
120 }
121
129 STATIC INLINE void IP_TIMER_ClearMatch(IP_TIMER_001_T *pTimer, int8_t matchnum)
130 {
131 pTimer->IR = TIMER_IR_CLR(matchnum);
132 }
133
141 STATIC INLINE void IP_TIMER_ClearCapture(IP_TIMER_001_T *pTimer, int8_t capnum)
142 {
143 pTimer->IR = (0x10 << capnum);
144 }
145
152 STATIC INLINE void IP_TIMER_Enable(IP_TIMER_001_T *pTimer)
153 {
154 pTimer->TCR |= TIMER_ENABLE;
155 }
156
163 STATIC INLINE void IP_TIMER_Disable(IP_TIMER_001_T *pTimer)
164 {
165 pTimer->TCR &= ~TIMER_ENABLE;
166 }
167
174 STATIC INLINE uint32_t IP_TIMER_ReadCount(IP_TIMER_001_T *pTimer)
175 {
176 return pTimer->TC;
177 }
178
185 STATIC INLINE uint32_t IP_TIMER_ReadPrescale(IP_TIMER_001_T *pTimer)
186 {
187 return pTimer->PC;
188 }
189
197 STATIC INLINE void IP_TIMER_PrescaleSet(IP_TIMER_001_T *pTimer, uint32_t prescale)
198 {
199 pTimer->PR = prescale;
200 }
201
210 STATIC INLINE void IP_TIMER_SetMatch(IP_TIMER_001_T *pTimer, int8_t matchnum, uint32_t matchval)
211 {
212 pTimer->MR[matchnum] = matchval;
213 }
214
222 STATIC INLINE uint32_t IP_TIMER_ReadCapture(IP_TIMER_001_T *pTimer, int8_t capnum)
223 {
224 return pTimer->CR[capnum];
225 }
226
232 void IP_TIMER_Reset(IP_TIMER_001_T *pTimer);
233
241 STATIC INLINE void IP_TIMER_MatchEnableInt(IP_TIMER_001_T *pTimer, int8_t matchnum)
242 {
243 pTimer->MCR |= TIMER_INT_ON_MATCH(matchnum);
244 }
245
252 STATIC INLINE void IP_TIMER_MatchDisableInt(IP_TIMER_001_T *pTimer, int8_t matchnum)
253 {
254 pTimer->MCR &= ~TIMER_INT_ON_MATCH(matchnum);
255 }
256
263 STATIC INLINE void IP_TIMER_ResetOnMatchEnable(IP_TIMER_001_T *pTimer, int8_t matchnum)
264 {
265 pTimer->MCR |= TIMER_RESET_ON_MATCH(matchnum);
266 }
267
274 STATIC INLINE void IP_TIMER_ResetOnMatchDisable(IP_TIMER_001_T *pTimer, int8_t matchnum)
275 {
276 pTimer->MCR &= ~TIMER_RESET_ON_MATCH(matchnum);
277 }
278
286 STATIC INLINE void IP_TIMER_StopOnMatchEnable(IP_TIMER_001_T *pTimer, int8_t matchnum)
287 {
288 pTimer->MCR |= TIMER_STOP_ON_MATCH(matchnum);
289 }
290
298 STATIC INLINE void IP_TIMER_StopOnMatchDisable(IP_TIMER_001_T *pTimer, int8_t matchnum)
299 {
300 pTimer->MCR &= ~TIMER_STOP_ON_MATCH(matchnum);
301 }
302
311 STATIC INLINE void IP_TIMER_CaptureRisingEdgeEnable(IP_TIMER_001_T *pTimer, int8_t capnum)
312 {
313 pTimer->CCR |= TIMER_CAP_RISING(capnum);
314 }
315
324 STATIC INLINE void IP_TIMER_CaptureRisingEdgeDisable(IP_TIMER_001_T *pTimer, int8_t capnum)
325 {
326 pTimer->CCR &= ~TIMER_CAP_RISING(capnum);
327 }
328
337 STATIC INLINE void IP_TIMER_CaptureFallingEdgeEnable(IP_TIMER_001_T *pTimer, int8_t capnum)
338 {
339 pTimer->CCR |= TIMER_CAP_FALLING(capnum);
340 }
341
350 STATIC INLINE void IP_TIMER_CaptureFallingEdgeDisable(IP_TIMER_001_T *pTimer, int8_t capnum)
351 {
352 pTimer->CCR &= ~TIMER_CAP_FALLING(capnum);
353 }
354
363 STATIC INLINE void IP_TIMER_CaptureEnableInt(IP_TIMER_001_T *pTimer, int8_t capnum)
364 {
365 pTimer->CCR |= TIMER_INT_ON_CAP(capnum);
366 }
367
374 STATIC INLINE void IP_TIMER_CaptureDisableInt(IP_TIMER_001_T *pTimer, int8_t capnum)
375 {
376 pTimer->CCR &= ~TIMER_INT_ON_CAP(capnum);
377 }
378
382 typedef enum IP_TIMER_PIN_MATCH_STATE {
383 TIMER_EXTMATCH_DO_NOTHING = 0,
384 TIMER_EXTMATCH_CLEAR = 1,
385 TIMER_EXTMATCH_SET = 2,
386 TIMER_EXTMATCH_TOGGLE = 3
387 } IP_TIMER_PIN_MATCH_STATE_T;
388
399 void IP_TIMER_ExtMatchControlSet(IP_TIMER_001_T *pTimer, int8_t initial_state,
400 IP_TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum);
401
405 typedef enum IP_TIMER_CAP_SRC_STATE {
406 TIMER_CAPSRC_RISING_PCLK = 0,
407 TIMER_CAPSRC_RISING_CAPN = 1,
408 TIMER_CAPSRC_FALLING_CAPN = 2,
409 TIMER_CAPSRC_BOTH_CAPN = 3
410 } IP_TIMER_CAP_SRC_STATE_T;
411
420 void IP_TIMER_SetCountClockSrc(IP_TIMER_001_T *pTimer,
421 IP_TIMER_CAP_SRC_STATE_T capSrc, int8_t capnum);
422
427 #ifdef __cplusplus
428 }
429 #endif
430
431 #endif /* __TIMER_001_H_ */