| LPCOpen Platform v1.03 LPCOpen Platform for NXP LPC Microcontrollers

- Main Page
- Modules
- Data Structures
- Files
- Related Pages

- File List
- Globals

All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
enet_002.h
Go to the documentation of this file.
1 /*
2 * @brief Ethernet (002) control functions
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __ENET_002_H_
33 #define __ENET_002_H_
34
35 #include "sys_config.h"
36 #include "cmsis.h"
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
52 typedef struct {
53 __IO uint32_t MAC1;
54 __IO uint32_t MAC2;
55 __IO uint32_t IPGT;
56 __IO uint32_t IPGR;
57 __IO uint32_t CLRT;
58 __IO uint32_t MAXF;
59 __IO uint32_t SUPP;
60 __IO uint32_t TEST;
61 __IO uint32_t MCFG;
62 __IO uint32_t MCMD;
63 __IO uint32_t MADR;
64 __O uint32_t MWTD;
65 __I uint32_t MRDD;
66 __I uint32_t MIND;
67 uint32_t RESERVED0[2];
68 __IO uint32_t SA[3];
69 } IP_ENET_002_MAC_T;
70
74 typedef struct {
75 __IO uint32_t DESCRIPTOR;
76 __IO uint32_t STATUS;
77 __IO uint32_t DESCRIPTORNUMBER;
78 __IO uint32_t PRODUCEINDEX;
79 __IO uint32_t CONSUMEINDEX;
80 } IP_ENET_002_TRANSFER_INFO_T;
81
85 typedef struct {
86 __IO uint32_t COMMAND;
87 __I uint32_t STATUS;
88 IP_ENET_002_TRANSFER_INFO_T RX;
89 IP_ENET_002_TRANSFER_INFO_T TX;
90 uint32_t RESERVED0[10];
91 __I uint32_t TSV0;
92 __I uint32_t TSV1;
93 __I uint32_t RSV;
94 uint32_t RESERVED1[3];
95 __IO uint32_t FLOWCONTROLCOUNTER;
96 __I uint32_t FLOWCONTROLSTATUS;
97 } IP_ENET_002_CONTROL_T;
98
102 typedef struct {
103 __IO uint32_t CONTROL;
104 __I uint32_t WOLSTATUS;
105 __O uint32_t WOLCLEAR;
106 uint32_t RESERVED;
107 __IO uint32_t HashFilterL;
108 __IO uint32_t HashFilterH;
109 } IP_ENET_002_RXFILTER_T;
110
114 typedef struct {
115 __I uint32_t INTSTATUS;
116 __IO uint32_t INTENABLE;
117 __O uint32_t INTCLEAR;
118 __O uint32_t INTSET;
119 uint32_t RESERVED;
120 __IO uint32_t POWERDOWN;
121 } IP_ENET_002_MODULE_CTRL_T;
122
126 typedef struct {
127 IP_ENET_002_MAC_T MAC;
128 uint32_t RESERVED1[45];
129 IP_ENET_002_CONTROL_T CONTROL;
130 uint32_t RESERVED4[34];
131 IP_ENET_002_RXFILTER_T RXFILTER;
132 uint32_t RESERVED6[882];
133 IP_ENET_002_MODULE_CTRL_T MODULE_CONTROL;
134 } IP_ENET_002_T;
135
139 #define ENET_MAC1_MASK 0xcf1f
140 #define ENET_MAC1_RXENABLE 0x00000001
141 #define ENET_MAC1_PARF 0x00000002
142 #define ENET_MAC1_RXFLOWCTRL 0x00000004
143 #define ENET_MAC1_TXFLOWCTRL 0x00000008
144 #define ENET_MAC1_LOOPBACK 0x00000010
145 #define ENET_MAC1_RESETTX 0x00000100
146 #define ENET_MAC1_RESETMCSTX 0x00000200
147 #define ENET_MAC1_RESETRX 0x00000400
148 #define ENET_MAC1_RESETMCSRX 0x00000800
149 #define ENET_MAC1_SIMRESET 0x00004000
150 #define ENET_MAC1_SOFTRESET 0x00008000
155 #define ENET_MAC2_MASK 0x73ff
156 #define ENET_MAC2_FULLDUPLEX 0x00000001
157 #define ENET_MAC2_FLC 0x00000002
158 #define ENET_MAC2_HFEN 0x00000004
159 #define ENET_MAC2_DELAYEDCRC 0x00000008
160 #define ENET_MAC2_CRCEN 0x00000010
161 #define ENET_MAC2_PADCRCEN 0x00000020
162 #define ENET_MAC2_VLANPADEN 0x00000040
163 #define ENET_MAC2_AUTODETPADEN 0x00000080
164 #define ENET_MAC2_PPENF 0x00000100
165 #define ENET_MAC2_LPENF 0x00000200
166 #define ENET_MAC2_NOBACKOFF 0x00001000
167 #define ENET_MAC2_BP_NOBACKOFF 0x00002000
168 #define ENET_MAC2_EXCESSDEFER 0x00004000
175 #define ENET_IPGT_BTOBINTEGAP(n) ((n) & 0x7F)
176
180 #define ENET_IPGT_FULLDUPLEX (ENET_IPGT_BTOBINTEGAP(0x15))
181
185 #define ENET_IPGT_HALFDUPLEX (ENET_IPGT_BTOBINTEGAP(0x12))
186
192 #define ENET_IPGR_NBTOBINTEGAP2(n) ((n) & 0x7F)
193
195 #define ENET_IPGR_P2_DEF (ENET_IPGR_NBTOBINTEGAP2(0x12))
196
199 #define ENET_IPGR_NBTOBINTEGAP1(n) (((n) & 0x7F) << 8)
200
202 #define ENET_IPGR_P1_DEF ENET_IPGR_NBTOBINTEGAP1(0x0C)
203
209 #define ENET_CLRT_RETRANSMAX(n) ((n) & 0x0F)
210
213 #define ENET_CLRT_COLLWIN(n) (((n) & 0x3F) << 8)
214
216 #define ENET_CLRT_DEF ((ENET_CLRT_RETRANSMAX(0x0F)) | (ENET_CLRT_COLLWIN(0x37)))
217
222 #define ENET_MAXF_MAXFLEN(n) ((n) & 0xFFFF)
223 #define ENET_MAXF_MAXFLEN_DEF (0x600)
224
225 /* PHY Support Register */
226 #define ENET_SUPP_100Mbps_SPEED 0x00000100
231 #define ENET_TEST_SCPQ 0x00000001
232 #define ENET_TEST_TESTPAUSE 0x00000002
233 #define ENET_TEST_TESTBP 0x00000004
238 #define ENET_MCFG_SCANINC 0x00000001
239 #define ENET_MCFG_SUPPPREAMBLE 0x00000002
240 #define ENET_MCFG_CLOCKSEL(n) (((n) & 0x0F) << 2)
241 #define ENET_MCFG_RES_MII 0x00008000
242 #define ENET_MCFG_RESETMIIMGMT 2500000UL
247 #define ENET_MCMD_READ 0x00000001
248 #define ENET_MCMD_SCAN 0x00000002
249 #define ENET_MII_WR_TOUT 0x00050000
250 #define ENET_MII_RD_TOUT 0x00050000
255 #define ENET_MADR_REGADDR(n) ((n) & 0x1F)
256 #define ENET_MADR_PHYADDR(n) (((n) & 0x1F) << 8)
261 #define ENET_MWTD_DATA(n) ((n) & 0xFFFF)
266 #define ENET_MRDD_DATA(n) ((n) & 0xFFFF)
271 #define ENET_MIND_BUSY 0x00000001
272 #define ENET_MIND_SCANNING 0x00000002
273 #define ENET_MIND_NOTVALID 0x00000004
274 #define ENET_MIND_MIILINKFAIL 0x00000008
279 #define ENET_COMMAND_RXENABLE 0x00000001
280 #define ENET_COMMAND_TXENABLE 0x00000002
281 #define ENET_COMMAND_REGRESET 0x00000008
282 #define ENET_COMMAND_TXRESET 0x00000010
283 #define ENET_COMMAND_RXRESET 0x00000020
284 #define ENET_COMMAND_PASSRUNTFRAME 0x00000040
285 #define ENET_COMMAND_PASSRXFILTER 0x00000080
286 #define ENET_COMMAND_TXFLOWCONTROL 0x00000100
287 #define ENET_COMMAND_RMII 0x00000200
288 #define ENET_COMMAND_FULLDUPLEX 0x00000400
293 #define ENET_STATUS_RXSTATUS 0x00000001
294 #define ENET_STATUS_TXSTATUS 0x00000002
299 #define ENET_TSV0_CRCERR 0x00000001
300 #define ENET_TSV0_LCE 0x00000002
301 #define ENET_TSV0_LOR 0x00000004
302 #define ENET_TSV0_DONE 0x00000008
303 #define ENET_TSV0_MULTICAST 0x00000010
304 #define ENET_TSV0_BROADCAST 0x00000020
305 #define ENET_TSV0_PACKETDEFER 0x00000040
306 #define ENET_TSV0_EXDF 0x00000080
307 #define ENET_TSV0_EXCOL 0x00000100
308 #define ENET_TSV0_LCOL 0x00000200
309 #define ENET_TSV0_GIANT 0x00000400
310 #define ENET_TSV0_UNDERRUN 0x00000800
311 #define ENET_TSV0_TOTALBYTES 0x0FFFF000
312 #define ENET_TSV0_CONTROLFRAME 0x10000000
313 #define ENET_TSV0_PAUSE 0x20000000
314 #define ENET_TSV0_BACKPRESSURE 0x40000000
315 #define ENET_TSV0_VLAN 0x80000000
320 #define ENET_TSV1_TBC 0x0000FFFF
321 #define ENET_TSV1_TCC 0x000F0000
326 #define ENET_RSV_RBC 0x0000FFFF
327 #define ENET_RSV_PPI 0x00010000
328 #define ENET_RSV_RXDVSEEN 0x00020000
329 #define ENET_RSV_CESEEN 0x00040000
330 #define ENET_RSV_RCV 0x00080000
331 #define ENET_RSV_CRCERR 0x00100000
332 #define ENET_RSV_LCERR 0x00200000
333 #define ENET_RSV_LOR 0x00400000
334 #define ENET_RSV_ROK 0x00800000
335 #define ENET_RSV_MULTICAST 0x01000000
336 #define ENET_RSV_BROADCAST 0x02000000
337 #define ENET_RSV_DRIBBLENIBBLE 0x04000000
338 #define ENET_RSV_CONTROLFRAME 0x08000000
339 #define ENET_RSV_PAUSE 0x10000000
340 #define ENET_RSV_UO 0x20000000
341 #define ENET_RSV_VLAN 0x40000000
346 #define ENET_FLOWCONTROLCOUNTER_MC(n) ((n) & 0xFFFF)
347 #define ENET_FLOWCONTROLCOUNTER_PT(n) (((n) & 0xFFFF) << 16)
352 #define ENET_FLOWCONTROLSTATUS_MCC(n) ((n) & 0xFFFF)
357 #define ENET_RXFILTERCTRL_AUE 0x00000001
358 #define ENET_RXFILTERCTRL_ABE 0x00000002
359 #define ENET_RXFILTERCTRL_AME 0x00000004
360 #define ENET_RXFILTERCTRL_AUHE 0x00000008
361 #define ENET_RXFILTERCTRL_AMHE 0x00000010
362 #define ENET_RXFILTERCTRL_APE 0x00000020
363 #define ENET_RXFILTERCTRL_MPEW 0x00001000
364 #define ENET_RXFILTERCTRL_RFEW 0x00002000
369 #define ENET_RXFILTERWOLSTATUS_AUW 0x00000001
370 #define ENET_RXFILTERWOLSTATUS_ABW 0x00000002
371 #define ENET_RXFILTERWOLSTATUS_AMW 0x00000004
372 #define ENET_RXFILTERWOLSTATUS_AUHW 0x00000008
373 #define ENET_RXFILTERWOLSTATUS_AMHW 0x00000010
374 #define ENET_RXFILTERWOLSTATUS_APW 0x00000020
375 #define ENET_RXFILTERWOLSTATUS_RFW 0x00000080
376 #define ENET_RXFILTERWOLSTATUS_MPW 0x00000100
377 #define ENET_RXFILTERWOLSTATUS_BITMASK 0x01BF
382 #define ENET_INT_RXOVERRUN 0x00000001
383 #define ENET_INT_RXERROR 0x00000002
384 #define ENET_INT_RXFINISHED 0x00000004
385 #define ENET_INT_RXDONE 0x00000008
386 #define ENET_INT_TXUNDERRUN 0x00000010
387 #define ENET_INT_TXERROR 0x00000020
388 #define ENET_INT_TXFINISHED 0x00000040
389 #define ENET_INT_TXDONE 0x00000080
390 #define ENET_INT_SOFT 0x00001000
391 #define ENET_INT_WAKEUP 0x00002000
396 #define ENET_POWERDOWN_PD 0x80000000
401 typedef struct {
402 uint32_t Packet;
403 uint32_t Control;
404 } IP_ENET_002_RXDESC_T;
405
409 #define ENET_RCTRL_SIZE(n) (((n) - 1) & 0x7FF)
410 #define ENET_RCTRL_INT 0x80000000
415 typedef struct {
416 uint32_t StatusInfo;
417 uint32_t StatusHashCRC;
419 } IP_ENET_002_RXSTAT_T;
420
424 #define ENET_RHASH_SA 0x000001FF
425 #define ENET_RHASH_DA 0x001FF000
427 /* RX Status Information Word */
428 #define ENET_RINFO_SIZE(n) (((n) & 0x7FF) + 1)
429 #define ENET_RINFO_CTRL_FRAME 0x00040000
430 #define ENET_RINFO_VLAN 0x00080000
431 #define ENET_RINFO_FAIL_FILT 0x00100000
432 #define ENET_RINFO_MCAST 0x00200000
433 #define ENET_RINFO_BCAST 0x00400000
434 #define ENET_RINFO_CRC_ERR 0x00800000
435 #define ENET_RINFO_SYM_ERR 0x01000000
436 #define ENET_RINFO_LEN_ERR 0x02000000
437 #define ENET_RINFO_RANGE_ERR 0x04000000
438 #define ENET_RINFO_ALIGN_ERR 0x08000000
439 #define ENET_RINFO_OVERRUN 0x10000000
440 #define ENET_RINFO_NO_DESCR 0x20000000
441 #define ENET_RINFO_LAST_FLAG 0x40000000
442 #define ENET_RINFO_ERR 0x80000000
444 #define ENET_RINFO_ERR_MASK (ENET_RINFO_FAIL_FILT | ENET_RINFO_CRC_ERR | ENET_RINFO_SYM_ERR | \
445 ENET_RINFO_LEN_ERR | ENET_RINFO_ALIGN_ERR | ENET_RINFO_OVERRUN)
446
450 typedef struct {
451 uint32_t Packet;
452 uint32_t Control;
453 } IP_ENET_002_TXDESC_T;
454
458 #define ENET_TCTRL_SIZE(n) (((n) - 1) & 0x7FF)
459 #define ENET_TCTRL_OVERRIDE 0x04000000
460 #define ENET_TCTRL_HUGE 0x08000000
461 #define ENET_TCTRL_PAD 0x10000000
462 #define ENET_TCTRL_CRC 0x20000000
463 #define ENET_TCTRL_LAST 0x40000000
464 #define ENET_TCTRL_INT 0x80000000
469 typedef struct {
470 uint32_t StatusInfo;
471 } IP_ENET_002_TXSTAT_T;
472
473 /* TX Status Information Word */
474 #define ENET_TINFO_COL_CNT 0x01E00000
475 #define ENET_TINFO_DEFER 0x02000000
476 #define ENET_TINFO_EXCESS_DEF 0x04000000
477 #define ENET_TINFO_EXCESS_COL 0x08000000
478 #define ENET_TINFO_LATE_COL 0x10000000
479 #define ENET_TINFO_UNDERRUN 0x20000000
480 #define ENET_TINFO_NO_DESCR 0x40000000
481 #define ENET_TINFO_ERR 0x80000000
486 #define ENET_ETH_MAX_FLEN (1536)
487
491 typedef enum IP_ENET_002_BUFF_STATUS {
492 ENET_BUFF_EMPTY, /* buffer is empty */
493 ENET_BUFF_PARTIAL_FULL, /* buffer contains some packets */
494 ENET_BUFF_FULL, /* buffer is full */
495 } IP_ENET_002_BUFF_STATUS_T;
496
502 STATIC INLINE void IP_ENET_TXEnable(IP_ENET_002_T *pENET)
503 {
504 /* Descriptor list head pointers must be setup prior to enable */
505 pENET->CONTROL.COMMAND |= ENET_COMMAND_TXENABLE;
506 }
507
513 STATIC INLINE void IP_ENET_TXDisable(IP_ENET_002_T *pENET)
514 {
515 pENET->CONTROL.COMMAND &= ~ENET_COMMAND_TXENABLE;
516 }
517
523 STATIC INLINE void IP_ENET_RXEnable(IP_ENET_002_T *pENET)
524 {
525 /* Descriptor list head pointers must be setup prior to enable */
526 pENET->CONTROL.COMMAND |= ENET_COMMAND_RXENABLE;
527 pENET->MAC.MAC1 |= ENET_MAC1_RXENABLE;
528 }
529
535 STATIC INLINE void IP_ENET_RXDisable(IP_ENET_002_T *pENET)
536 {
537 pENET->CONTROL.COMMAND &= ~ENET_COMMAND_RXENABLE;
538 pENET->MAC.MAC1 &= ~ENET_MAC1_RXENABLE;
539 }
540
546 STATIC INLINE void IP_ENET_ResetTXLogic(IP_ENET_002_T *pENET)
547 {
548 pENET->MAC.MAC1 |= ENET_MAC1_RESETTX;
549 }
550
556 STATIC INLINE void IP_ENET_ResetRXLogic(IP_ENET_002_T *pENET)
557 {
558 pENET->MAC.MAC1 |= ENET_MAC1_RESETRX;
559 }
560
567 STATIC INLINE void IP_ENET_EnableRXFilter(IP_ENET_002_T *pENET, uint32_t mask)
568 {
569 pENET->CONTROL.COMMAND &= ~ENET_COMMAND_PASSRXFILTER;
570 pENET->RXFILTER.CONTROL |= mask;
571 }
572
579 STATIC INLINE void IP_ENET_DisableRXFilter(IP_ENET_002_T *pENET, uint32_t mask)
580 {
581 pENET->RXFILTER.CONTROL &= ~mask;
582 }
583
589 STATIC INLINE void IP_ENET_SetFullDuplex(IP_ENET_002_T *pENET)
590 {
591 pENET->MAC.MAC2 |= ENET_MAC2_FULLDUPLEX;
592 pENET->CONTROL.COMMAND |= ENET_COMMAND_FULLDUPLEX;
593 pENET->MAC.IPGT = ENET_IPGT_FULLDUPLEX;
594 }
595
601 STATIC INLINE void IP_ENET_SetHalfDuplex(IP_ENET_002_T *pENET)
602 {
603 pENET->MAC.MAC2 &= ~ENET_MAC2_FULLDUPLEX;
604 pENET->CONTROL.COMMAND &= ~ENET_COMMAND_FULLDUPLEX;
605 pENET->MAC.IPGT = ENET_IPGT_HALFDUPLEX;
606 }
607
613 STATIC INLINE void IP_ENET_Set100Mbps(IP_ENET_002_T *pENET)
614 {
615 pENET->MAC.SUPP = ENET_SUPP_100Mbps_SPEED;
616 }
617
623 STATIC INLINE void IP_ENET_Set10Mbps(IP_ENET_002_T *pENET)
624 {
625 pENET->MAC.SUPP = 0;
626 }
627
633 STATIC INLINE uint16_t IP_ENET_GetTXProduceIndex(IP_ENET_002_T *pENET)
634 {
635 return pENET->CONTROL.TX.PRODUCEINDEX;
636 }
637
643 STATIC INLINE uint16_t IP_ENET_GetTXConsumeIndex(IP_ENET_002_T *pENET)
644 {
645 return pENET->CONTROL.TX.CONSUMEINDEX;
646 }
647
653 STATIC INLINE uint16_t IP_ENET_GetRXProduceIndex(IP_ENET_002_T *pENET)
654 {
655 return pENET->CONTROL.RX.PRODUCEINDEX;
656 }
657
663 STATIC INLINE uint16_t IP_ENET_GetRXConsumeIndex(IP_ENET_002_T *pENET)
664 {
665 return pENET->CONTROL.RX.CONSUMEINDEX;
666 }
667
674 STATIC INLINE void IP_ENET_EnableInt(IP_ENET_002_T *pENET, uint32_t mask)
675 {
676 pENET->MODULE_CONTROL.INTENABLE |= mask;
677 }
678
685 STATIC INLINE void IP_ENET_DisableInt(IP_ENET_002_T *pENET, uint32_t mask)
686 {
687 pENET->MODULE_CONTROL.INTENABLE &= ~mask;
688 }
689
695 STATIC INLINE uint32_t IP_ENET_GetIntStatus(IP_ENET_002_T *pENET)
696 {
697 return pENET->MODULE_CONTROL.INTSTATUS;
698 }
699
706 STATIC INLINE void IP_ENET_ClearIntStatus(IP_ENET_002_T *pENET, uint32_t mask)
707 {
708 pENET->MODULE_CONTROL.INTCLEAR = mask;
709 }
710
718 void IP_ENET_Reset(IP_ENET_002_T *pENET);
719
726 void IP_ENET_SetADDR(IP_ENET_002_T *pENET, const uint8_t *macAddr);
727
736 void IP_ENET_Init(IP_ENET_002_T *pENET);
737
745 void IP_ENET_SetupMII(IP_ENET_002_T *pENET, uint8_t div, uint8_t addr);
746
752 void IP_ENET_DeInit(IP_ENET_002_T *pENET);
753
763 void IP_ENET_StartMIIWrite(IP_ENET_002_T *pENET, uint8_t reg, uint16_t data);
764
774 void IP_ENET_StartMIIRead(IP_ENET_002_T *pENET, uint8_t reg);
775
781 bool IP_ENET_IsMIIBusy(IP_ENET_002_T *pENET);
782
788 uint16_t IP_ENET_ReadMIIData(IP_ENET_002_T *pENET);
789
798 void IP_ENET_InitTxDescriptors(IP_ENET_002_T *pENET,
799 IP_ENET_002_TXDESC_T *pDescs,
800 IP_ENET_002_TXSTAT_T *pStatus,
801 uint32_t descNum);
802
811 void IP_ENET_InitRxDescriptors(IP_ENET_002_T *pENET,
812 IP_ENET_002_RXDESC_T *pDescs,
813 IP_ENET_002_RXSTAT_T *pStatus,
814 uint32_t descNum);
815
823 IP_ENET_002_BUFF_STATUS_T IP_ENET_GetBufferStatus(uint16_t produceIndex, uint16_t consumeIndex, uint16_t buffSize);
824
832 uint32_t IP_ENET_GetFillDescNum(uint16_t produceIndex, uint16_t consumeIndex, uint16_t buffSize);
833
841 STATIC INLINE uint32_t IP_ENET_GetFreeDescNum(uint16_t produceIndex, uint16_t consumeIndex, uint16_t buffSize)
842 {
843 return buffSize - 1 - IP_ENET_GetFillDescNum(produceIndex, consumeIndex, buffSize);
844 }
845
851 STATIC INLINE bool IP_ENET_IsTxFull(IP_ENET_002_T *pENET)
852 {
853 return ((pENET->CONTROL.TX.CONSUMEINDEX == (pENET->CONTROL.TX.PRODUCEINDEX + 1)) ||
854 ((pENET->CONTROL.TX.CONSUMEINDEX == 0) &&
855 (pENET->CONTROL.TX.PRODUCEINDEX == pENET->CONTROL.TX.DESCRIPTORNUMBER))) ? true : false;
856 }
857
863 STATIC INLINE bool IP_ENET_IsRxEmpty(IP_ENET_002_T *pENET)
864 {
865 uint32_t tem = pENET->CONTROL.RX.PRODUCEINDEX;
866 return (pENET->CONTROL.RX.CONSUMEINDEX != tem) ? false : true;
867 }
868
874 uint16_t IP_ENET_IncTXProduceIndex(IP_ENET_002_T *pENET);
875
881 uint16_t IP_ENET_IncRXConsumeIndex(IP_ENET_002_T *pENET);
882
887 #ifdef __cplusplus
888 }
889 #endif
890
891 #endif /* __ENET_002_H_ */