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evrt_18xx_43xx.h
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1 /*
2 * @brief LPC18xx/43xx event router driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __EVRT_18XX_43XX_H_
33 #define __EVRT_18XX_43XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
47 typedef struct {
48 __IO uint32_t HILO;
49 __IO uint32_t EDGE;
50 __I uint32_t RESERVED0[1012];
51 __O uint32_t CLR_EN;
52 __O uint32_t SET_EN;
53 __I uint32_t STATUS;
54 __I uint32_t ENABLE;
55 __O uint32_t CLR_STAT;
56 __O uint32_t SET_STAT;
57 } LPC_EVRT_T;
58
62 typedef enum CHIP_EVRT_SRC {
63 EVRT_SRC_WAKEUP0,
64 EVRT_SRC_WAKEUP1,
65 EVRT_SRC_WAKEUP2,
66 EVRT_SRC_WAKEUP3,
67 EVRT_SRC_ATIMER,
68 EVRT_SRC_RTC,
69 EVRT_SRC_BOD1,
70 EVRT_SRC_WWDT,
71 EVRT_SRC_ETHERNET,
72 EVRT_SRC_USB0,
73 EVRT_SRC_USB1,
74 EVRT_SRC_SDIO,
75 EVRT_SRC_CCAN,
76 EVRT_SRC_COMBINE_TIMER2,
77 EVRT_SRC_COMBINE_TIMER6,
78 EVRT_SRC_QEI,
79 EVRT_SRC_COMBINE_TIMER14,
80 EVRT_SRC_RESERVED1,
81 EVRT_SRC_RESERVED2,
82 EVRT_SRC_RESET
83 } CHIP_EVRT_SRC_T;
84
88 #define PARAM_EVRT_SOURCE(n) ((n == EVRT_SRC_WAKEUP0) || (n == EVRT_SRC_WAKEUP1) \
89 || (n == EVRT_SRC_WAKEUP2) || (n == EVRT_SRC_WAKEUP3) \
90 || (n == EVRT_SRC_ATIMER) || (n == EVRT_SRC_RTC) \
91 || (n == EVRT_SRC_BOD1) || (n == EVRT_SRC_WWDT) \
92 || (n == EVRT_SRC_ETHERNET) || (n == EVRT_SRC_USB0) \
93 || (n == EVRT_SRC_USB1) || (n == EVRT_SRC_CCAN) || (n == EVRT_SRC_SDIO) \
94 || (n == EVRT_SRC_COMBINE_TIMER2) || (n == EVRT_SRC_COMBINE_TIMER6) \
95 || (n == EVRT_SRC_QEI) || (n == EVRT_SRC_COMBINE_TIMER14) \
96 || (n == EVRT_SRC_RESET)) \
97
98
101 typedef enum CHIP_EVRT_SRC_ACTIVE {
102 EVRT_SRC_ACTIVE_LOW_LEVEL,
103 EVRT_SRC_ACTIVE_HIGH_LEVEL,
104 EVRT_SRC_ACTIVE_FALLING_EDGE,
105 EVRT_SRC_ACTIVE_RISING_EDGE
106 } CHIP_EVRT_SRC_ACTIVE_T;
107
111 #define PARAM_EVRT_SOURCE_ACTIVE_TYPE(n) ((n == EVRT_SRC_ACTIVE_LOW_LEVEL) || (n == EVRT_SRC_ACTIVE_HIGH_LEVEL) \
112 || (n == EVRT_SRC_ACTIVE_FALLING_EDGE) || (n == EVRT_SRC_ACTIVE_RISING_EDGE))
113
118 void Chip_EVRT_Init (void);
119
126 void Chip_EVRT_ConfigIntSrcActiveType(CHIP_EVRT_SRC_T EVRT_Src, CHIP_EVRT_SRC_ACTIVE_T type);
127
133 IntStatus Chip_EVRT_IsSourceInterrupting(CHIP_EVRT_SRC_T EVRT_Src);
134
141 void Chip_EVRT_SetUpIntSrc(CHIP_EVRT_SRC_T EVRT_Src, FunctionalState state);
142
147 STATIC INLINE void Chip_EVRT_DeInit(void)
148 {
149 LPC_EVRT->CLR_EN = 0xFFFF;
150 LPC_EVRT->CLR_STAT = 0xFFFF;
151 }
152
158 STATIC INLINE void Chip_EVRT_ClrPendIntSrc(CHIP_EVRT_SRC_T EVRT_Src)
159 {
160 LPC_EVRT->CLR_STAT = (1 << (uint8_t) EVRT_Src);
161 }
162
167 #ifdef __cplusplus
168 }
169 #endif
170
171 #endif /* __EVRT_18XX_43XX_H_ */