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clock_11xx.c
Go to the documentation of this file.
1 /*
2 * @brief LPC11XX System clock control functions
3 *
4 * Copyright(C) NXP Semiconductors, 2012
5 * All rights reserved.
6 *
7 * Software that is described herein is for illustrative purposes only
8 * which provides customers with programming information regarding the
9 * LPC products. This software is supplied "AS IS" without any warranties of
10 * any kind, and NXP Semiconductors and its licensor disclaim any and
11 * all warranties, express or implied, including all implied warranties of
12 * merchantability, fitness for a particular purpose and non-infringement of
13 * intellectual property rights. NXP Semiconductors assumes no responsibility
14 * or liability for the use of the software, conveys no license or rights under any
15 * patent, copyright, mask work right, or any other intellectual property rights in
16 * or to any products. NXP Semiconductors reserves the right to make changes
17 * in the software without notification. NXP Semiconductors also makes no
18 * representation or warranty that such application will be suitable for the
19 * specified use without further testing or modification.
20 *
21 * Permission to use, copy, modify, and distribute this software and its
22 * documentation is hereby granted, under NXP Semiconductors' and its
23 * licensor's relevant copyrights in the software, without fee, provided that it
24 * is used in conjunction with NXP Semiconductors microcontrollers. This
25 * copyright, permission, and disclaimer notice must appear in all copies of
26 * this code.
27 */
28
29 #include "chip.h"
30
31 /*****************************************************************************
32 * Private types/enumerations/variables
33 ****************************************************************************/
34
35 /* Inprecise clock rates for the watchdog oscillator */
36 STATIC const uint32_t wdtOSCRate[WDTLFO_OSC_4_60 + 1] = {
37 0, /* WDT_OSC_ILLEGAL */
38 600000, /* WDT_OSC_0_60 */
39 1050000, /* WDT_OSC_1_05 */
40 1400000, /* WDT_OSC_1_40 */
41 1750000, /* WDT_OSC_1_75 */
42 2100000, /* WDT_OSC_2_10 */
43 2400000, /* WDT_OSC_2_40 */
44 2700000, /* WDT_OSC_2_70 */
45 3000000, /* WDT_OSC_3_00 */
46 3250000, /* WDT_OSC_3_25 */
47 3500000, /* WDT_OSC_3_50 */
48 3750000, /* WDT_OSC_3_75 */
49 4000000, /* WDT_OSC_4_00 */
50 4200000, /* WDT_OSC_4_20 */
51 4400000, /* WDT_OSC_4_40 */
52 4600000 /* WDT_OSC_4_60 */
53 };
54
55 /*****************************************************************************
56 * Public types/enumerations/variables
57 ****************************************************************************/
58
59 /*****************************************************************************
60 * Private functions
61 ****************************************************************************/
62
63 /* Compute a WDT or LFO rate */
64 STATIC uint32_t Chip_Clock_GetWDTLFORate(uint32_t reg)
65 {
66 uint32_t div;
67 CHIP_WDTLFO_OSC_T clk;
68
69 /* Get WDT oscillator settings */
70 clk = (CHIP_WDTLFO_OSC_T) ((reg >> 5) & 0xF);
71 div = reg & 0x1F;
72
73 /* Compute clock rate and divided by divde value */
74 return wdtOSCRate[clk] / ((div + 1) << 1);
75 }
76
77 /* Compute a PLL frequency */
78 STATIC uint32_t Chip_Clock_GetPllFreq(uint32_t PllReg, uint32_t inputRate)
79 {
80 uint32_t msel = ((PllReg & 0x1F) + 1);
81
82 return inputRate * msel;
83 }
84
85 /*****************************************************************************
86 * Public functions
87 ****************************************************************************/
88
89 /* Set System PLL clock source */
90 void Chip_Clock_SetSystemPllSource(CHIP_SYSCTL_PLLCLKSRC_T src)
91 {
92 LPC_SYSCTL->SYSPLLCLKSEL = (uint32_t) src;
93 LPC_SYSCTL->SYSPLLCLKUEN = 0;
94 LPC_SYSCTL->SYSPLLCLKUEN = 1;
95 }
96
97 /* Bypass System Oscillator and set oscillator frequency range */
98 void Chip_Clock_SetPLLBypass(bool bypass, bool highfr)
99 {
100 uint32_t ctrl = 0;
101
102 if (bypass) {
103 ctrl |= (1 << 0);
104 }
105 if (highfr) {
106 ctrl |= (1 << 1);
107 }
108
109 LPC_SYSCTL->SYSOSCCTRL = ctrl;
110 }
111
112 #if defined(CHIP_LPC11UXX)
113 /* Set USB PLL clock source */
114 void Chip_Clock_SetUSBPllSource(CHIP_SYSCTL_PLLCLKSRC_T src)
115 {
116 LPC_SYSCTL->USBPLLCLKSEL = (uint32_t) src;
117 LPC_SYSCTL->USBPLLCLKUEN = 0;
118 LPC_SYSCTL->USBPLLCLKUEN = 1;
119 }
120
121 #endif
122
123 /* Set main system clock source */
124 void Chip_Clock_SetMainClockSource(CHIP_SYSCTL_MAINCLKSRC_T src)
125 {
126 LPC_SYSCTL->MAINCLKSEL = (uint32_t) src;
127 LPC_SYSCTL->MAINCLKUEN = 0;
128 LPC_SYSCTL->MAINCLKUEN = 1;
129 }
130
131 #if defined(CHIP_LPC11UXX)
132 /* Set USB clock source and divider */
133 void Chip_Clock_SetUSBClockSource(CHIP_SYSCTL_USBCLKSRC_T src, uint32_t div)
134 {
135 LPC_SYSCTL->USBCLKSEL = (uint32_t) src;
136 LPC_SYSCTL->USBCLKUEN = 0;
137 LPC_SYSCTL->USBCLKUEN = 1;
138 LPC_SYSCTL->USBCLKDIV = div;
139 }
140
141 #endif /*CHIP_LPC11UXX*/
142
143 #if defined(CHIP_LPC110X) || defined(CHIP_LPC11XXLV) || defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX)
144 /* Set WDT clock source and divider */
145 void Chip_Clock_SetWDTClockSource(CHIP_SYSCTL_WDTCLKSRC_T src, uint32_t div)
146 {
147 LPC_SYSCTL->WDTCLKSEL = (uint32_t) src;
148 LPC_SYSCTL->WDTCLKUEN = 0;
149 LPC_SYSCTL->WDTCLKUEN = 1;
150 LPC_SYSCTL->WDTCLKDIV = div;
151 }
152
153 #endif
154
155 #if !defined(CHIP_LPC110X)
156 /* Set CLKOUT clock source and divider */
157 void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div)
158 {
159 LPC_SYSCTL->CLKOUTSEL = (uint32_t) src;
160 LPC_SYSCTL->CLKOUTUEN = 0;
161 LPC_SYSCTL->CLKOUTUEN = 1;
162 LPC_SYSCTL->CLKOUTDIV = div;
163 }
164
165 #endif
166
167 /* Return estimated watchdog oscillator rate */
168 uint32_t Chip_Clock_GetWDTOSCRate(void)
169 {
170 return Chip_Clock_GetWDTLFORate(LPC_SYSCTL->WDTOSCCTRL);
171 }
172
173 #if defined(CHIP_LPC11AXX)
174 /* Return estimated low frequency oscillator rate */
175 uint32_t Chip_Clock_GetLFOOSCRate(void)
176 {
177 return Chip_Clock_GetWDTLFORate(LPC_SYSCTL->LFOSCCTRL);
178 }
179
180 #endif
181
182 /* Return System PLL input clock rate */
183 uint32_t Chip_Clock_GetSystemPllInClockRate(void)
184 {
185 uint32_t clkRate;
186
187 switch ((CHIP_SYSCTL_PLLCLKSRC_T) (LPC_SYSCTL->SYSPLLCLKSEL & 0x3)) {
188 case SYSCTL_PLLCLKSRC_IRC:
189 clkRate = Chip_Clock_GetIntOscRate();
190 break;
191
192 case SYSCTL_PLLCLKSRC_MAINOSC:
193 clkRate = Chip_Clock_GetMainOscRate();
194 break;
195
196 #if defined(CHIP_LPC11AXX)
197 case SYSCTL_PLLCLKSRC_EXT_CLKIN:
198 clkRate = Chip_Clock_GetExtClockInRate();
199 break;
200 #endif
201
202 default:
203 clkRate = 0;
204 }
205
206 return clkRate;
207 }
208
209 /* Return System PLL output clock rate */
210 uint32_t Chip_Clock_GetSystemPllOutClockRate(void)
211 {
212 return Chip_Clock_GetPllFreq(LPC_SYSCTL->SYSPLLCTRL,
213 Chip_Clock_GetSystemPllInClockRate());
214 }
215
216 #if defined(CHIP_LPC11UXX)
217 /* Return USB PLL input clock rate */
218 uint32_t Chip_Clock_GetUSBPllInClockRate(void)
219 {
220 uint32_t clkRate;
221
222 switch ((CHIP_SYSCTL_PLLCLKSRC_T) (LPC_SYSCTL->USBPLLCLKSEL & 0x3)) {
223 case SYSCTL_PLLCLKSRC_IRC:
224 clkRate = Chip_Clock_GetIntOscRate();
225 break;
226
227 case SYSCTL_PLLCLKSRC_MAINOSC:
228 clkRate = Chip_Clock_GetMainOscRate();
229 break;
230
231 default:
232 clkRate = 0;
233 }
234
235 return clkRate;
236 }
237
238 /* Return USB PLL output clock rate */
239 uint32_t Chip_Clock_GetUSBPllOutClockRate(void)
240 {
241 return Chip_Clock_GetPllFreq(LPC_SYSCTL->USBPLLCTRL,
242 Chip_Clock_GetUSBPllInClockRate());
243 }
244
245 #endif
246
247 /* Return main clock rate */
248 uint32_t Chip_Clock_GetMainClockRate(void)
249 {
250 uint32_t clkRate = 0;
251
252 switch ((CHIP_SYSCTL_MAINCLKSRC_T) (LPC_SYSCTL->MAINCLKSEL & 0x3)) {
253 case SYSCTL_MAINCLKSRC_IRC:
254 clkRate = Chip_Clock_GetIntOscRate();
255 break;
256
257 case SYSCTL_MAINCLKSRC_PLLIN:
258 clkRate = Chip_Clock_GetSystemPllInClockRate();
259 break;
260
261 #if defined(CHIP_LPC11AXX)
262 case SYSCTL_MAINCLKSRC_LFOSC:
263 clkRate = Chip_Clock_GetLFOOSCRate();
264 break;
265
266 #else
267 case SYSCTL_MAINCLKSRC_WDTOSC:
268 clkRate = Chip_Clock_GetWDTOSCRate();
269 break;
270 #endif
271
272 case SYSCTL_MAINCLKSRC_PLLOUT:
273 clkRate = Chip_Clock_GetSystemPllOutClockRate();
274 break;
275 }
276
277 return clkRate;
278 }
279
280 /* Return system clock rate */
281 uint32_t Chip_Clock_GetSystemClockRate(void)
282 {
283 /* No point in checking for divide by 0 */
284 return Chip_Clock_GetMainClockRate() / LPC_SYSCTL->SYSAHBCLKDIV;
285 }