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Data Structures | Macros | Enumerations | Functions
enet_002.h File Reference
`#include "sys_config.h"`
`#include "cmsis.h"`

Go to the source code of this file.

## Data Structures
struct | IP_ENET_002_MAC_T
| Ethernet (002) MAC register block structure. More...
struct | IP_ENET_002_TRANSFER_INFO_T
| Ethernet Transfer register Block Structure. More...
struct | IP_ENET_002_CONTROL_T
| Ethernet Control register block structure. More...
struct | IP_ENET_002_RXFILTER_T
| Ethernet Receive Filter register block structure. More...
struct | IP_ENET_002_MODULE_CTRL_T
| Ethernet Module Control register block structure. More...
struct | IP_ENET_002_T
| Ethernet register block structure. More...
struct | IP_ENET_002_RXDESC_T
| RX Descriptor structure. More...
struct | IP_ENET_002_RXSTAT_T
| RX Status structure. More...
struct | IP_ENET_002_TXDESC_T
| TX Descriptor structure. More...
struct | IP_ENET_002_TXSTAT_T
| TX Status structure. More...

## Macros
#define | ENET_MAC1_MASK 0xcf1f
| MAC Configuration Register 1 bit definitions.
#define | ENET_MAC1_RXENABLE 0x00000001
#define | ENET_MAC1_PARF 0x00000002
#define | ENET_MAC1_RXFLOWCTRL 0x00000004
#define | ENET_MAC1_TXFLOWCTRL 0x00000008
#define | ENET_MAC1_LOOPBACK 0x00000010
#define | ENET_MAC1_RESETTX 0x00000100
#define | ENET_MAC1_RESETMCSTX 0x00000200
#define | ENET_MAC1_RESETRX 0x00000400
#define | ENET_MAC1_RESETMCSRX 0x00000800
#define | ENET_MAC1_SIMRESET 0x00004000
#define | ENET_MAC1_SOFTRESET 0x00008000
#define | ENET_MAC2_MASK 0x73ff
| MAC Configuration Register 2 bit definitions.
#define | ENET_MAC2_FULLDUPLEX 0x00000001
#define | ENET_MAC2_FLC 0x00000002
#define | ENET_MAC2_HFEN 0x00000004
#define | ENET_MAC2_DELAYEDCRC 0x00000008
#define | ENET_MAC2_CRCEN 0x00000010
#define | ENET_MAC2_PADCRCEN 0x00000020
#define | ENET_MAC2_VLANPADEN 0x00000040
#define | ENET_MAC2_AUTODETPADEN 0x00000080
#define | ENET_MAC2_PPENF 0x00000100
#define | ENET_MAC2_LPENF 0x00000200
#define | ENET_MAC2_NOBACKOFF 0x00001000
#define | ENET_MAC2_BP_NOBACKOFF 0x00002000
#define | ENET_MAC2_EXCESSDEFER 0x00004000
#define | ENET_IPGT_BTOBINTEGAP(n) ((n) & 0x7F)
| Back-to-Back Inter-Packet-Gap Register bit definitions.
#define | ENET_IPGT_FULLDUPLEX (ENET_IPGT_BTOBINTEGAP(0x15))
#define | ENET_IPGT_HALFDUPLEX (ENET_IPGT_BTOBINTEGAP(0x12))
#define | ENET_IPGR_NBTOBINTEGAP2(n) ((n) & 0x7F)
| Non Back-to-Back Inter-Packet-Gap Register bit definitions.
#define | ENET_IPGR_P2_DEF (ENET_IPGR_NBTOBINTEGAP2(0x12))
#define | ENET_IPGR_NBTOBINTEGAP1(n) (((n) & 0x7F) << 8)
#define | ENET_IPGR_P1_DEF ENET_IPGR_NBTOBINTEGAP1(0x0C)
#define | ENET_CLRT_RETRANSMAX(n) ((n) & 0x0F)
| Collision Window/Retry Register bit definitions.
#define | ENET_CLRT_COLLWIN(n) (((n) & 0x3F) << 8)
#define | ENET_CLRT_DEF ((ENET_CLRT_RETRANSMAX(0x0F)) | (ENET_CLRT_COLLWIN(0x37)))
#define | ENET_MAXF_MAXFLEN(n) ((n) & 0xFFFF)
| Maximum Frame Register bit definitions.
#define | ENET_MAXF_MAXFLEN_DEF (0x600)
#define | ENET_SUPP_100Mbps_SPEED 0x00000100
#define | ENET_TEST_SCPQ 0x00000001
| Test Register bit definitions.
#define | ENET_TEST_TESTPAUSE 0x00000002
#define | ENET_TEST_TESTBP 0x00000004
#define | ENET_MCFG_SCANINC 0x00000001
| MII Management Configuration Register bit definitions.
#define | ENET_MCFG_SUPPPREAMBLE 0x00000002
#define | ENET_MCFG_CLOCKSEL(n) (((n) & 0x0F) << 2)
#define | ENET_MCFG_RES_MII 0x00008000
#define | ENET_MCFG_RESETMIIMGMT 2500000UL
#define | ENET_MCMD_READ 0x00000001
| MII Management Command Register bit definitions.
#define | ENET_MCMD_SCAN 0x00000002
#define | ENET_MII_WR_TOUT 0x00050000
#define | ENET_MII_RD_TOUT 0x00050000
#define | ENET_MADR_REGADDR(n) ((n) & 0x1F)
| MII Management Address Register bit definitions.
#define | ENET_MADR_PHYADDR(n) (((n) & 0x1F) << 8)
#define | ENET_MWTD_DATA(n) ((n) & 0xFFFF)
| MII Management Write Data Register bit definitions.
#define | ENET_MRDD_DATA(n) ((n) & 0xFFFF)
| MII Management Read Data Register bit definitions.
#define | ENET_MIND_BUSY 0x00000001
| MII Management Indicators Register bit definitions.
#define | ENET_MIND_SCANNING 0x00000002
#define | ENET_MIND_NOTVALID 0x00000004
#define | ENET_MIND_MIILINKFAIL 0x00000008
#define | ENET_COMMAND_RXENABLE 0x00000001
| Command Register bit definitions.
#define | ENET_COMMAND_TXENABLE 0x00000002
#define | ENET_COMMAND_REGRESET 0x00000008
#define | ENET_COMMAND_TXRESET 0x00000010
#define | ENET_COMMAND_RXRESET 0x00000020
#define | ENET_COMMAND_PASSRUNTFRAME 0x00000040
#define | ENET_COMMAND_PASSRXFILTER 0x00000080
#define | ENET_COMMAND_TXFLOWCONTROL 0x00000100
#define | ENET_COMMAND_RMII 0x00000200
#define | ENET_COMMAND_FULLDUPLEX 0x00000400
#define | ENET_STATUS_RXSTATUS 0x00000001
| Status Register bit definitions.
#define | ENET_STATUS_TXSTATUS 0x00000002
#define | ENET_TSV0_CRCERR 0x00000001
| Transmit Status Vector 0 Register bit definitions.
#define | ENET_TSV0_LCE 0x00000002
#define | ENET_TSV0_LOR 0x00000004
#define | ENET_TSV0_DONE 0x00000008
#define | ENET_TSV0_MULTICAST 0x00000010
#define | ENET_TSV0_BROADCAST 0x00000020
#define | ENET_TSV0_PACKETDEFER 0x00000040
#define | ENET_TSV0_EXDF 0x00000080
#define | ENET_TSV0_EXCOL 0x00000100
#define | ENET_TSV0_LCOL 0x00000200
#define | ENET_TSV0_GIANT 0x00000400
#define | ENET_TSV0_UNDERRUN 0x00000800
#define | ENET_TSV0_TOTALBYTES 0x0FFFF000
#define | ENET_TSV0_CONTROLFRAME 0x10000000
#define | ENET_TSV0_PAUSE 0x20000000
#define | ENET_TSV0_BACKPRESSURE 0x40000000
#define | ENET_TSV0_VLAN 0x80000000
#define | ENET_TSV1_TBC 0x0000FFFF
| Transmit Status Vector 0 Register bit definitions.
#define | ENET_TSV1_TCC 0x000F0000
#define | ENET_RSV_RBC 0x0000FFFF
| Receive Status Vector Register bit definitions.
#define | ENET_RSV_PPI 0x00010000
#define | ENET_RSV_RXDVSEEN 0x00020000
#define | ENET_RSV_CESEEN 0x00040000
#define | ENET_RSV_RCV 0x00080000
#define | ENET_RSV_CRCERR 0x00100000
#define | ENET_RSV_LCERR 0x00200000
#define | ENET_RSV_LOR 0x00400000
#define | ENET_RSV_ROK 0x00800000
#define | ENET_RSV_MULTICAST 0x01000000
#define | ENET_RSV_BROADCAST 0x02000000
#define | ENET_RSV_DRIBBLENIBBLE 0x04000000
#define | ENET_RSV_CONTROLFRAME 0x08000000
#define | ENET_RSV_PAUSE 0x10000000
#define | ENET_RSV_UO 0x20000000
#define | ENET_RSV_VLAN 0x40000000
#define | ENET_FLOWCONTROLCOUNTER_MC(n) ((n) & 0xFFFF)
| Flow Control Counter Register bit definitions.
#define | ENET_FLOWCONTROLCOUNTER_PT(n) (((n) & 0xFFFF) << 16)
#define | ENET_FLOWCONTROLSTATUS_MCC(n) ((n) & 0xFFFF)
| Flow Control Status Register bit definitions.
#define | ENET_RXFILTERCTRL_AUE 0x00000001
| Receive Filter Control Register bit definitions.
#define | ENET_RXFILTERCTRL_ABE 0x00000002
#define | ENET_RXFILTERCTRL_AME 0x00000004
#define | ENET_RXFILTERCTRL_AUHE 0x00000008
#define | ENET_RXFILTERCTRL_AMHE 0x00000010
#define | ENET_RXFILTERCTRL_APE 0x00000020
#define | ENET_RXFILTERCTRL_MPEW 0x00001000
#define | ENET_RXFILTERCTRL_RFEW 0x00002000
#define | ENET_RXFILTERWOLSTATUS_AUW 0x00000001
| Receive Filter WoL Status/Clear Register bit definitions.
#define | ENET_RXFILTERWOLSTATUS_ABW 0x00000002
#define | ENET_RXFILTERWOLSTATUS_AMW 0x00000004
#define | ENET_RXFILTERWOLSTATUS_AUHW 0x00000008
#define | ENET_RXFILTERWOLSTATUS_AMHW 0x00000010
#define | ENET_RXFILTERWOLSTATUS_APW 0x00000020
#define | ENET_RXFILTERWOLSTATUS_RFW 0x00000080
#define | ENET_RXFILTERWOLSTATUS_MPW 0x00000100
#define | ENET_RXFILTERWOLSTATUS_BITMASK 0x01BF
#define | ENET_INT_RXOVERRUN 0x00000001
| Interrupt Status/Enable/Clear/Set Register bit definitions.
#define | ENET_INT_RXERROR 0x00000002
#define | ENET_INT_RXFINISHED 0x00000004
#define | ENET_INT_RXDONE 0x00000008
#define | ENET_INT_TXUNDERRUN 0x00000010
#define | ENET_INT_TXERROR 0x00000020
#define | ENET_INT_TXFINISHED 0x00000040
#define | ENET_INT_TXDONE 0x00000080
#define | ENET_INT_SOFT 0x00001000
#define | ENET_INT_WAKEUP 0x00002000
#define | ENET_POWERDOWN_PD 0x80000000
| Power Down Register bit definitions.
#define | ENET_RCTRL_SIZE(n) (((n) - 1) & 0x7FF)
| RX Descriptor Control structure type definition.
#define | ENET_RCTRL_INT 0x80000000
#define | ENET_RHASH_SA 0x000001FF
| RX Status Hash CRC Word definition.
#define | ENET_RHASH_DA 0x001FF000
#define | ENET_RINFO_SIZE(n) (((n) & 0x7FF) + 1)
#define | ENET_RINFO_CTRL_FRAME 0x00040000
#define | ENET_RINFO_VLAN 0x00080000
#define | ENET_RINFO_FAIL_FILT 0x00100000
#define | ENET_RINFO_MCAST 0x00200000
#define | ENET_RINFO_BCAST 0x00400000
#define | ENET_RINFO_CRC_ERR 0x00800000
#define | ENET_RINFO_SYM_ERR 0x01000000
#define | ENET_RINFO_LEN_ERR 0x02000000
#define | ENET_RINFO_RANGE_ERR 0x04000000
#define | ENET_RINFO_ALIGN_ERR 0x08000000
#define | ENET_RINFO_OVERRUN 0x10000000
#define | ENET_RINFO_NO_DESCR 0x20000000
#define | ENET_RINFO_LAST_FLAG 0x40000000
#define | ENET_RINFO_ERR 0x80000000
#define | ENET_RINFO_ERR_MASK
#define | ENET_TCTRL_SIZE(n) (((n) - 1) & 0x7FF)
| TX Descriptor Control structure type definition.
#define | ENET_TCTRL_OVERRIDE 0x04000000
#define | ENET_TCTRL_HUGE 0x08000000
#define | ENET_TCTRL_PAD 0x10000000
#define | ENET_TCTRL_CRC 0x20000000
#define | ENET_TCTRL_LAST 0x40000000
#define | ENET_TCTRL_INT 0x80000000
#define | ENET_TINFO_COL_CNT 0x01E00000
#define | ENET_TINFO_DEFER 0x02000000
#define | ENET_TINFO_EXCESS_DEF 0x04000000
#define | ENET_TINFO_EXCESS_COL 0x08000000
#define | ENET_TINFO_LATE_COL 0x10000000
#define | ENET_TINFO_UNDERRUN 0x20000000
#define | ENET_TINFO_NO_DESCR 0x40000000
#define | ENET_TINFO_ERR 0x80000000
#define | ENET_ETH_MAX_FLEN (1536)
| Maximum size of an ethernet buffer.

## Enumerations
enum | IP_ENET_002_BUFF_STATUS_T { ENET_BUFF_EMPTY, ENET_BUFF_PARTIAL_FULL, ENET_BUFF_FULL }
| ENET Buffer status definition. More...

## Functions
STATIC INLINE void | IP_ENET_TXEnable (IP_ENET_002_T *pENET)
| Enables ethernet transmit.
STATIC INLINE void | IP_ENET_TXDisable (IP_ENET_002_T *pENET)
| Disables ethernet transmit.
STATIC INLINE void | IP_ENET_RXEnable (IP_ENET_002_T *pENET)
| Enables ethernet packet reception.
STATIC INLINE void | IP_ENET_RXDisable (IP_ENET_002_T *pENET)
| Disables ethernet packet reception.
STATIC INLINE void | IP_ENET_ResetTXLogic (IP_ENET_002_T *pENET)
| Reset Tx Logic.
STATIC INLINE void | IP_ENET_ResetRXLogic (IP_ENET_002_T *pENET)
| Reset Rx Logic.
STATIC INLINE void | IP_ENET_EnableRXFilter (IP_ENET_002_T *pENET, uint32_t mask)
| Enable Rx Filter.
STATIC INLINE void | IP_ENET_DisableRXFilter (IP_ENET_002_T *pENET, uint32_t mask)
| Disable Rx Filter.
STATIC INLINE void | IP_ENET_SetFullDuplex (IP_ENET_002_T *pENET)
| Sets full duplex for the ENET interface.
STATIC INLINE void | IP_ENET_SetHalfDuplex (IP_ENET_002_T *pENET)
| Sets half duplex for the ENET interface.
STATIC INLINE void | IP_ENET_Set100Mbps (IP_ENET_002_T *pENET)
| Selects 100Mbps for the current operating speed.
STATIC INLINE void | IP_ENET_Set10Mbps (IP_ENET_002_T *pENET)
| Selects 10Mbps for the current operating speed.
STATIC INLINE uint16_t | IP_ENET_GetTXProduceIndex (IP_ENET_002_T *pENET)
| Get the current Tx Produce Descriptor Index.
STATIC INLINE uint16_t | IP_ENET_GetTXConsumeIndex (IP_ENET_002_T *pENET)
| Get the current Tx Consume Descriptor Index.
STATIC INLINE uint16_t | IP_ENET_GetRXProduceIndex (IP_ENET_002_T *pENET)
| Get the current Rx Produce Descriptor Index.
STATIC INLINE uint16_t | IP_ENET_GetRXConsumeIndex (IP_ENET_002_T *pENET)
| Get the current Rx Consume Descriptor Index.
STATIC INLINE void | IP_ENET_EnableInt (IP_ENET_002_T *pENET, uint32_t mask)
| Enable ENET interrupts.
STATIC INLINE void | IP_ENET_DisableInt (IP_ENET_002_T *pENET, uint32_t mask)
| Disable ENET interrupts.
STATIC INLINE uint32_t | IP_ENET_GetIntStatus (IP_ENET_002_T *pENET)
| Get the interrupt status.
STATIC INLINE void | IP_ENET_ClearIntStatus (IP_ENET_002_T *pENET, uint32_t mask)
| Clear the interrupt status.
void | IP_ENET_Reset (IP_ENET_002_T *pENET)
| Resets the ethernet interface.
void | IP_ENET_SetADDR (IP_ENET_002_T *pENET, const uint8_t *macAddr)
| Sets the address of the interface.
void | IP_ENET_Init (IP_ENET_002_T *pENET)
| Initialize ethernet interface.
void | IP_ENET_SetupMII (IP_ENET_002_T *pENET, uint8_t div, uint8_t addr)
| Sets up the PHY link clock divider and PHY address.
void | IP_ENET_DeInit (IP_ENET_002_T *pENET)
| De-initialize the ethernet interface.
void | IP_ENET_StartMIIWrite (IP_ENET_002_T *pENET, uint8_t reg, uint16_t data)
| Starts a PHY write via the MII.
void | IP_ENET_StartMIIRead (IP_ENET_002_T *pENET, uint8_t reg)
| Starts a PHY read via the MII.
bool | IP_ENET_IsMIIBusy (IP_ENET_002_T *pENET)
| Returns MII link (PHY) busy status.
uint16_t | IP_ENET_ReadMIIData (IP_ENET_002_T *pENET)
| Returns the value read from the PHY.
void | IP_ENET_InitTxDescriptors (IP_ENET_002_T *pENET, IP_ENET_002_TXDESC_T *pDescs, IP_ENET_002_TXSTAT_T *pStatus, uint32_t descNum)
| Configures the initial ethernet transmit descriptors.
void | IP_ENET_InitRxDescriptors (IP_ENET_002_T *pENET, IP_ENET_002_RXDESC_T *pDescs, IP_ENET_002_RXSTAT_T *pStatus, uint32_t descNum)
| Configures the initial ethernet receive descriptors.
IP_ENET_002_BUFF_STATUS_T | IP_ENET_GetBufferStatus (uint16_t produceIndex, uint16_t consumeIndex, uint16_t buffSize)
| Get status for the descriptor list.
uint32_t | IP_ENET_GetFillDescNum (uint16_t produceIndex, uint16_t consumeIndex, uint16_t buffSize)
| Get the number of descriptors filled.
STATIC INLINE uint32_t | IP_ENET_GetFreeDescNum (uint16_t produceIndex, uint16_t consumeIndex, uint16_t buffSize)
| Get the number of free descriptors.
STATIC INLINE bool | IP_ENET_IsTxFull (IP_ENET_002_T *pENET)
| Check if Tx buffer is full.
STATIC INLINE bool | IP_ENET_IsRxEmpty (IP_ENET_002_T *pENET)
| Check if Rx buffer is empty.
uint16_t | IP_ENET_IncTXProduceIndex (IP_ENET_002_T *pENET)
| Increase the current Tx Produce Descriptor Index.
uint16_t | IP_ENET_IncRXConsumeIndex (IP_ENET_002_T *pENET)
| Increase the current Rx Consume Descriptor Index.