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gpdma_001.h
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1 /*
2 * @brief GPDMA Registers and control functions
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __GPDMA_001_H_
33 #define __GPDMA_001_H_
34
35 #include "sys_config.h"
36 #include "cmsis.h"
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
51 typedef struct {
52 __IO uint32_t SRCADDR;
53 __IO uint32_t DESTADDR;
54 __IO uint32_t LLI;
55 __IO uint32_t CONTROL;
56 __IO uint32_t CONFIG;
57 __I uint32_t RESERVED1[3];
58 } IP_GPDMA_001_CH_T;
59
60 #define GPDMA_CHANNELS 8
61
65 typedef struct {
66 __I uint32_t INTSTAT;
67 __I uint32_t INTTCSTAT;
68 __O uint32_t INTTCCLEAR;
69 __I uint32_t INTERRSTAT;
70 __O uint32_t INTERRCLR;
71 __I uint32_t RAWINTTCSTAT;
72 __I uint32_t RAWINTERRSTAT;
73 __I uint32_t ENBLDCHNS;
74 __IO uint32_t SOFTBREQ;
75 __IO uint32_t SOFTSREQ;
76 __IO uint32_t SOFTLBREQ;
77 __IO uint32_t SOFTLSREQ;
78 __IO uint32_t CONFIG;
79 __IO uint32_t SYNC;
80 __I uint32_t RESERVED0[50];
81 IP_GPDMA_001_CH_T CH[GPDMA_CHANNELS];
82 } IP_GPDMA_001_T;
83
87 #define GPDMA_DMACCxControl_TransferSize(n) (((n & 0xFFF) << 0))
88 #define GPDMA_DMACCxControl_SBSize(n) (((n & 0x07) << 12))
89 #define GPDMA_DMACCxControl_DBSize(n) (((n & 0x07) << 15))
90 #define GPDMA_DMACCxControl_SWidth(n) (((n & 0x07) << 18))
91 #define GPDMA_DMACCxControl_DWidth(n) (((n & 0x07) << 21))
92 #define GPDMA_DMACCxControl_SI ((1UL << 26))
93 #define GPDMA_DMACCxControl_DI ((1UL << 27))
94 #if defined(CHIP_LPC43XX) || defined(CHIP_LPC18XX)
95 #define GPDMA_DMACCxControl_SrcTransUseAHBMaster1 ((1UL << 24))
96 #define GPDMA_DMACCxControl_DestTransUseAHBMaster1 ((1UL << 25))
97 #else
98 #define GPDMA_DMACCxControl_SrcTransUseAHBMaster1 0
99 #define GPDMA_DMACCxControl_DestTransUseAHBMaster1 0
100 #endif
101 #define GPDMA_DMACCxControl_Prot1 ((1UL << 28))
102 #define GPDMA_DMACCxControl_Prot2 ((1UL << 29))
103 #define GPDMA_DMACCxControl_Prot3 ((1UL << 30))
104 #define GPDMA_DMACCxControl_I ((1UL << 31))
109 #define GPDMA_DMACConfig_E ((0x01))
110 #define GPDMA_DMACConfig_M ((0x02))
111 #define GPDMA_DMACConfig_BITMASK ((0x03))
112
116 #define GPDMA_DMACCxConfig_E ((1UL << 0))
117 #define GPDMA_DMACCxConfig_SrcPeripheral(n) (((n & 0x1F) << 1))
118 #define GPDMA_DMACCxConfig_DestPeripheral(n) (((n & 0x1F) << 6))
119 #define GPDMA_DMACCxConfig_TransferType(n) (((n & 0x7) << 11))
120 #define GPDMA_DMACCxConfig_IE ((1UL << 14))
121 #define GPDMA_DMACCxConfig_ITC ((1UL << 15))
122 #define GPDMA_DMACCxConfig_L ((1UL << 16))
123 #define GPDMA_DMACCxConfig_A ((1UL << 17))
124 #define GPDMA_DMACCxConfig_H ((1UL << 18))
129 typedef enum IP_GPDMA_STATECLEAR {
130 GPDMA_STATCLR_INTTC,
131 GPDMA_STATCLR_INTERR
132 } IP_GPDMA_STATECLEAR_T;
133
137 typedef enum IP_GPDMA_STATUS {
138 GPDMA_STAT_INT,
139 GPDMA_STAT_INTTC,
140 GPDMA_STAT_INTERR,
141 GPDMA_STAT_RAWINTTC,
142 GPDMA_STAT_RAWINTERR,
143 GPDMA_STAT_ENABLED_CH
144 } IP_GPDMA_STATUS_T;
145
149 typedef enum IP_GPDMA_FLOW_CONTROL {
150 GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA = ((0UL)),
151 GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA = ((1UL)),
152 GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA = ((2UL)),
153 GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA = ((3UL)),
154 GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL = ((4UL)),
155 GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL = ((5UL)),
156 GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL = ((6UL)),
157 GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL = ((7UL))
158 } IP_GPDMA_FLOW_CONTROL_T;
159
163 typedef struct {
164 uint32_t ChannelNum;
169 uint32_t TransferSize;
170 uint32_t TransferWidth;
171 uint32_t SrcAddr;
173 uint32_t DstAddr;
175 uint32_t TransferType;
181 } GPDMA_Channel_CFG_T;
182
188 void IP_GPDMA_Init(IP_GPDMA_001_T *pGPDMA);
189
202 uint32_t IP_GPDMA_MakeCtrlWord(const GPDMA_Channel_CFG_T *GPDMAChannelConfig,
203 uint32_t GPDMA_LUTPerBurstSrcConn,
204 uint32_t GPDMA_LUTPerBurstDstConn,
205 uint32_t GPDMA_LUTPerWidSrcConn,
206 uint32_t GPDMA_LUTPerWidDstConn);
207
218 Status IP_GPDMA_Setup(IP_GPDMA_001_T *pGPDMA,
219 GPDMA_Channel_CFG_T *GPDMAChannelConfig,
220 uint32_t CtrlWord,
221 uint32_t LinkListItem,
222 uint8_t SrcPeripheral,
223 uint8_t DstPeripheral);
224
238 IntStatus IP_GPDMA_IntGetStatus(IP_GPDMA_001_T *pGPDMA, IP_GPDMA_STATUS_T type, uint8_t channel);
239
249 void IP_GPDMA_ClearIntPending(IP_GPDMA_001_T *pGPDMA, IP_GPDMA_STATECLEAR_T type, uint8_t channel);
250
258 void IP_GPDMA_ChannelCmd(IP_GPDMA_001_T *pGPDMA, uint8_t channelNum, FunctionalState NewState);
259
264 #ifdef __cplusplus
265 }
266 #endif
267
268 #endif /* __GPDMA_001_H_ */