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gpdma_001.c
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1 /*
2 * @brief GPDMA Registers and control functions
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #include "gpdma_001.h"
33
34 /*****************************************************************************
35 * Private types/enumerations/variables
36 ****************************************************************************/
37
38 /*****************************************************************************
39 * Public types/enumerations/variables
40 ****************************************************************************/
41
42 /*****************************************************************************
43 * Private functions
44 ****************************************************************************/
45
46 /*****************************************************************************
47 * Public functions
48 ****************************************************************************/
49
50 /* Initialize the GPDMA */
51 void IP_GPDMA_Init(IP_GPDMA_001_T *pGPDMA) {
52 uint8_t i;
53 /* Reset all channel configuration register */
54 for (i = 8; i > 0; i--) {
55 pGPDMA->CH[i - 1].CONFIG = 0;
56 }
57
58 /* Clear all DMA interrupt and error flag */
59 pGPDMA->INTTCCLEAR = 0xFF;
60 pGPDMA->INTERRCLR = 0xFF;
61 }
62
63 /* Read the status from different registers according to the type */
64 IntStatus IP_GPDMA_IntGetStatus(IP_GPDMA_001_T *pGPDMA, IP_GPDMA_STATUS_T type, uint8_t channel) {
68 switch (type) {
69 case GPDMA_STAT_INT:/* check status of DMA channel interrupts */
70 return (IntStatus) (pGPDMA->INTSTAT & (((1UL << channel) & 0xFF)));
71
72 case GPDMA_STAT_INTTC: /* check terminal count interrupt request status for DMA */
73 return (IntStatus) (pGPDMA->INTTCSTAT & (((1UL << channel) & 0xFF)));
74
75 case GPDMA_STAT_INTERR: /* check interrupt status for DMA channels */
76 return (IntStatus) (pGPDMA->INTERRSTAT & (((1UL << channel) & 0xFF)));
77
78 case GPDMA_STAT_RAWINTTC: /* check status of the terminal count interrupt for DMA channels */
79 return (IntStatus) (pGPDMA->RAWINTTCSTAT & (((1UL << channel) & 0xFF)));
80
81 case GPDMA_STAT_RAWINTERR: /* check status of the error interrupt for DMA channels */
82 return (IntStatus) (pGPDMA->RAWINTERRSTAT & (((1UL << channel) & 0xFF)));
83
84 default:/* check enable status for DMA channels */
85 return (IntStatus) (pGPDMA->ENBLDCHNS & (((1UL << channel) & 0xFF)));
86 }
87 }
88
89 /* Clear the Interrupt Flag from different registers according to the type */
90 void IP_GPDMA_ClearIntPending(IP_GPDMA_001_T *pGPDMA, IP_GPDMA_STATECLEAR_T type, uint8_t channel) {
91 if (type == GPDMA_STATCLR_INTTC) {
92 /* clears the terminal count interrupt request on DMA channel */
93 pGPDMA->INTTCCLEAR = (((1UL << (channel)) & 0xFF));
94 }
95 else {
96 /* clear the error interrupt request */
97 pGPDMA->INTERRCLR = (((1UL << (channel)) & 0xFF));
98 }
99 }
100
101 /* Enable or Disable the GPDMA Channel */
102 void IP_GPDMA_ChannelCmd(IP_GPDMA_001_T *pGPDMA, uint8_t channelNum, FunctionalState NewState) {
103 IP_GPDMA_001_CH_T *pDMAch;
104
105 /* Get Channel pointer */
106 pDMAch = (IP_GPDMA_001_CH_T *) &(pGPDMA->CH[channelNum]);
107
108 if (NewState == ENABLE) {
109 pDMAch->CONFIG |= GPDMA_DMACCxConfig_E;
110 }
111 else {
112 pDMAch->CONFIG &= ~GPDMA_DMACCxConfig_E;
113 }
114 }
115
116 uint32_t IP_GPDMA_MakeCtrlWord(const GPDMA_Channel_CFG_T *GPDMAChannelConfig,
117 uint32_t GPDMA_LUTPerBurstSrcConn,
118 uint32_t GPDMA_LUTPerBurstDstConn,
119 uint32_t GPDMA_LUTPerWidSrcConn,
120 uint32_t GPDMA_LUTPerWidDstConn)
121 {
122 uint32_t ctrl_word = 0;
123
124 switch (GPDMAChannelConfig->TransferType) {
125 /* Memory to memory */
126 case GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA:
127 ctrl_word = GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize)
128 | GPDMA_DMACCxControl_SBSize((4UL))
129 | GPDMA_DMACCxControl_DBSize((4UL))
130 | GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth)
131 | GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth)
132 | GPDMA_DMACCxControl_SI
133 | GPDMA_DMACCxControl_DI
134 | GPDMA_DMACCxControl_I;
135 break;
136
137 case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA:
138 case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL:
139 ctrl_word = GPDMA_DMACCxControl_TransferSize((uint32_t) GPDMAChannelConfig->TransferSize)
140 | GPDMA_DMACCxControl_SBSize(GPDMA_LUTPerBurstDstConn)
141 | GPDMA_DMACCxControl_DBSize(GPDMA_LUTPerBurstDstConn)
142 | GPDMA_DMACCxControl_SWidth(GPDMA_LUTPerWidDstConn)
143 | GPDMA_DMACCxControl_DWidth(GPDMA_LUTPerWidDstConn)
144 | GPDMA_DMACCxControl_DestTransUseAHBMaster1
145 | GPDMA_DMACCxControl_SI
146 | GPDMA_DMACCxControl_I;
147 break;
148
149 case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA:
150 case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL:
151 ctrl_word = GPDMA_DMACCxControl_TransferSize((uint32_t) GPDMAChannelConfig->TransferSize)
152 | GPDMA_DMACCxControl_SBSize(GPDMA_LUTPerBurstSrcConn)
153 | GPDMA_DMACCxControl_DBSize(GPDMA_LUTPerBurstSrcConn)
154 | GPDMA_DMACCxControl_SWidth(GPDMA_LUTPerWidSrcConn)
155 | GPDMA_DMACCxControl_DWidth(GPDMA_LUTPerWidSrcConn)
156 | GPDMA_DMACCxControl_SrcTransUseAHBMaster1
157 | GPDMA_DMACCxControl_DI
158 | GPDMA_DMACCxControl_I;
159 break;
160
161 case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA:
162 case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL:
163 case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL:
164 ctrl_word = GPDMA_DMACCxControl_TransferSize((uint32_t) GPDMAChannelConfig->TransferSize)
165 | GPDMA_DMACCxControl_SBSize(GPDMA_LUTPerBurstSrcConn)
166 | GPDMA_DMACCxControl_DBSize(GPDMA_LUTPerBurstDstConn)
167 | GPDMA_DMACCxControl_SWidth(GPDMA_LUTPerWidSrcConn)
168 | GPDMA_DMACCxControl_DWidth(GPDMA_LUTPerWidDstConn)
169 | GPDMA_DMACCxControl_SrcTransUseAHBMaster1
170 | GPDMA_DMACCxControl_DestTransUseAHBMaster1
171 | GPDMA_DMACCxControl_I;
172
173 break;
174
175 /* Do not support any more transfer type, return ERROR */
176 default:
177 return ERROR;
178 }
179 return ctrl_word;
180 }
181
182 /* Set up the DPDMA according to the specification configuration details */
183 Status IP_GPDMA_Setup(IP_GPDMA_001_T *pGPDMA,
184 GPDMA_Channel_CFG_T *GPDMAChannelConfig,
185 uint32_t CtrlWord,
186 uint32_t LinkListItem,
187 uint8_t SrcPeripheral,
188 uint8_t DstPeripheral)
189 {
190 IP_GPDMA_001_CH_T *pDMAch;
191
192 if (pGPDMA->ENBLDCHNS & ((((1UL << (GPDMAChannelConfig->ChannelNum)) & 0xFF)))) {
193 /* This channel is enabled, return ERROR, need to release this channel first */
194 return ERROR;
195 }
196
197 /* Get Channel pointer */
198 pDMAch = (IP_GPDMA_001_CH_T *) &(pGPDMA->CH[GPDMAChannelConfig->ChannelNum]);
199
200 /* Reset the Interrupt status */
201 pGPDMA->INTTCCLEAR = (((1UL << (GPDMAChannelConfig->ChannelNum)) & 0xFF));
202 pGPDMA->INTERRCLR = (((1UL << (GPDMAChannelConfig->ChannelNum)) & 0xFF));
203
204 /* Assign Linker List Item value */
205 pDMAch->LLI = LinkListItem;
206
207 /* Enable DMA channels, little endian */
208 pGPDMA->CONFIG = GPDMA_DMACConfig_E;
209 while (!(pGPDMA->CONFIG & GPDMA_DMACConfig_E)) {}
210
211 pDMAch->SRCADDR = GPDMAChannelConfig->SrcAddr;
212 pDMAch->DESTADDR = GPDMAChannelConfig->DstAddr;
213
214 /* Configure DMA Channel, enable Error Counter and Terminate counter */
215 pDMAch->CONFIG = GPDMA_DMACCxConfig_IE
216 | GPDMA_DMACCxConfig_ITC /*| GPDMA_DMACCxConfig_E*/
217 | GPDMA_DMACCxConfig_TransferType((uint32_t) GPDMAChannelConfig->TransferType)
218 | GPDMA_DMACCxConfig_SrcPeripheral(SrcPeripheral)
219 | GPDMA_DMACCxConfig_DestPeripheral(DstPeripheral);
220
221 pDMAch->CONTROL = CtrlWord;
222
223 return SUCCESS;
224 }