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HAL_LPC18xx.c
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1 /*
2 * @brief HAL USB functions for the LPC18xx microcontrollers
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #if defined(__LPC18XX__) || defined(__LPC43XX__)
33
34 #include "../HAL.h"
35 #include "../../USBTask.h"
36
37 #if defined(USB_CAN_BE_DEVICE)
38 #include "../../Device.h"
39
40 void HAL_USBConnect(uint8_t corenum, uint32_t con)
41 {
42 #if defined(USB_DEVICE_ROM_DRIVER)
43 if (con) {
44 USBD_API->hw->Connect(UsbHandle, 1);
45 }
46 else {
47 USBD_API->hw->Connect(UsbHandle, 0);
48 }
49 #else
50 if (con) {
51 USB_REG(corenum)->USBCMD_D |= (1 << 0);
52 }
53 else {
54 USB_REG(corenum)->USBCMD_D &= ~(1 << 0);
55 }
56 #endif
57 }
58
59 #endif
60
61 IP_USBHS_001_T * const USB_REG_BASE_ADDR[LPC18_43_MAX_USB_CORE] = {LPC_USB0, LPC_USB1};
62
63 /* Support for USB0 and USB1, 2 cores */
64 static bool coreEnabled[2];
65
66 void HAL_USBInit(uint8_t corenum)
67 {
68 /* Just exit if already enabled */
69 if (!coreEnabled[corenum]) {
70 /* if other code is not enabled, the enable USB PLL */
71 if (!coreEnabled[1 - corenum]) {
72 /* Neither core is enabled, so enable USB PLL first */
73 Chip_Clock_EnablePLL(CGU_USB_PLL);
74
75 /* Wait for PLL lock */
76 while (!(Chip_Clock_GetPLLStatus(CGU_USB_PLL) & CGU_PLL_LOCKED));
77 }
78
79 if (corenum == 0) {
80 /* For core 0, enable USB0 base clock */
81 Chip_Clock_EnableBaseClock(CLK_BASE_USB0);
82 Chip_Clock_EnableOpts(CLK_MX_USB0, true, true, 1);
83
84 /* Turn on the phy */
85 Chip_CREG_EnableUSB0Phy(true);
86 }
87 else {
88 /* For core 1, enable USB1 base clock */
89 Chip_Clock_EnableBaseClock(CLK_BASE_USB1);
90 Chip_Clock_EnableOpts(CLK_MX_USB1, true, true, 1);
91
92 /* Turn on the phy */
93 Chip_CREG_EnableUSB0Phy(true);
94 #if defined(USB_CAN_BE_HOST)
95 /* enable USB1_DP and USB1_DN on chip FS phy */
96 if (corenum && USB_CurrentMode[corenum] == USB_MODE_Host)LPC_SCU->SFSUSB = 0x16;
97 #endif
98 #if defined(USB_CAN_BE_DEVICE)
99 /* enable USB1_DP and USB1_DN on chip FS phy */
100 if (corenum && USB_CurrentMode[corenum] == USB_MODE_Device)LPC_SCU->SFSUSB = 0x12;
101 #endif
102 LPC_USB1->PORTSC1_D |= (1 << 24);
103 }
104
105 coreEnabled[corenum] = true;
106 }
107
108 #if defined(USB_CAN_BE_DEVICE) && (!defined(USB_DEVICE_ROM_DRIVER))
109 /* reset the controller */
110 USB_REG(corenum)->USBCMD_D = USBCMD_D_Reset;
111 /* wait for reset to complete */
112 while (USB_REG(corenum)->USBCMD_D & USBCMD_D_Reset) ;
113
114 /* Program the controller to be the USB device controller */
115 USB_REG(corenum)->USBMODE_D = (0x2 << 0) /*| (1<<4)*//*| (1<<3)*/;
116 if (corenum == 0) {
117 /* set OTG transcever in proper state, device is present
118 on the port(CCS=1), port enable/disable status change(PES=1). */
119 LPC_USB0->OTGSC = (1 << 3) | (1 << 0) /*| (1<<16)| (1<<24)| (1<<25)| (1<<26)| (1<<27)| (1<<28)| (1<<29)| (1<<30)*/;
120 #if (USB_FORCED_FULLSPEED)
121 LPC_USB0->PORTSC1_D |= (1 << 24);
122 #endif
123 }
124 HAL_Reset(corenum);
125 #endif
126 }
127
128 void HAL_USBDeInit(uint8_t corenum, uint8_t mode)
129 {
130 HAL_DisableUSBInterrupt(corenum);
131 if (mode == USB_MODE_Device) {
132 #if defined(USB_CAN_BE_HOST)
133 USB_REG(corenum)->USBSTS_H = 0xFFFFFFFF; /* clear all current interrupts */
134 USB_REG(corenum)->PORTSC1_H &= ~(1 << 12); /* clear port power */
135 USB_REG(corenum)->USBMODE_H = (1 << 0); /* set USB mode reserve */
136 #endif
137 }
138 else if (mode == USB_MODE_Host) {
139 #if defined(USB_CAN_BE_DEVICE)
140 /* Clear all pending interrupts */
141 USB_REG(corenum)->USBSTS_D = 0xFFFFFFFF;
142 USB_REG(corenum)->ENDPTNAK = 0xFFFFFFFF;
143 USB_REG(corenum)->ENDPTNAKEN = 0;
144 USB_REG(corenum)->ENDPTSETUPSTAT = USB_REG(corenum)->ENDPTSETUPSTAT;
145 USB_REG(corenum)->ENDPTCOMPLETE = USB_REG(corenum)->ENDPTCOMPLETE;
146 while (USB_REG(corenum)->ENDPTPRIME) ; /* Wait until all bits are 0 */
147 USB_REG(corenum)->ENDPTFLUSH = 0xFFFFFFFF;
148 while (USB_REG(corenum)->ENDPTFLUSH) ; /* Wait until all bits are 0 */
149 #endif
150 }
151
152 /* Disable USB PHY if both USB cores are disabled */
153 if (coreEnabled[1 - corenum]) {
154 /* Turn off the phy (prior to PLL disabled) */
155 Chip_CREG_EnableUSB0Phy(false);
156 }
157
158 /* Power down USB clocking */
159 if (corenum == 0) {
160 Chip_Clock_Disable(CLK_MX_USB0);
161 Chip_Clock_DisableBaseClock(CLK_BASE_USB0);
162 }
163 else {
164 Chip_Clock_Disable(CLK_MX_USB1);
165 Chip_Clock_DisableBaseClock(CLK_BASE_USB1);
166 }
167
168 /* Disable USB PLL if both USB cores are disabled */
169 if (coreEnabled[1 - corenum]) {
170 /* Disable USB PLL */
171 Chip_Clock_DisablePLL(CGU_USB_PLL);
172 }
173
174 coreEnabled[corenum] = false;
175 }
176
177 void HAL_EnableUSBInterrupt(uint8_t corenum)
178 {
179 NVIC_EnableIRQ((corenum) ? USB1_IRQn : USB0_IRQn); // enable USB interrupts
180 }
181
182 void HAL_DisableUSBInterrupt(uint8_t corenum)
183 {
184 NVIC_DisableIRQ((corenum) ? USB1_IRQn : USB0_IRQn); // disable USB interrupts
185 }
186
187 void USB0_IRQHandler(void)
188 {
189 if (USB_CurrentMode[0] == USB_MODE_Host) {
190 #ifdef USB_CAN_BE_HOST
191 HcdIrqHandler(0);
192 #endif
193 }
194 if (USB_CurrentMode[0] == USB_MODE_Device) {
195 #ifdef USB_CAN_BE_DEVICE
196 #ifdef USB_DEVICE_ROM_DRIVER
197 UsbdRom_IrqHandler();
198 #else
199 DcdIrqHandler(0);
200 #endif
201 #endif
202 }
203 }
204
205 void USB1_IRQHandler(void)
206 {
207 if (USB_CurrentMode[1] == USB_MODE_Host) {
208 #ifdef USB_CAN_BE_HOST
209 HcdIrqHandler(1);
210 #endif
211 }
212 if (USB_CurrentMode[1] == USB_MODE_Device) {
213 #ifdef USB_CAN_BE_DEVICE
214 #ifdef USB_DEVICE_ROM_DRIVER
215 UsbdRom_IrqHandler();
216 #else
217 DcdIrqHandler(1);
218 #endif
219 #endif
220 }
221 }
222
223 #endif /*__LPC18XX__*/