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Macros | Typedefs | Functions
cpu.h File Reference
`#include <cpu_def.h>`
`#include <cpu_cfg.h>`

Go to the source code of this file.

## Macros
#define | CPU_CFG_ADDR_SIZE CPU_WORD_SIZE_32 /* Defines CPU address word size (in octets). */
#define | CPU_CFG_DATA_SIZE CPU_WORD_SIZE_32 /* Defines CPU data word size (in octets). */
#define | CPU_CFG_ENDIAN_TYPE CPU_ENDIAN_TYPE_LITTLE /* Defines CPU data word-memory order (see Note #2). */
#define | CPU_CFG_STK_GROWTH CPU_STK_GROWTH_HI_TO_LO /* Defines CPU stack growth order (see Note #1). */
#define | CPU_CFG_CRITICAL_METHOD CPU_CRITICAL_METHOD_STATUS_LOCAL
#define | CPU_SR_ALLOC() CPU_SR cpu_sr = (CPU_SR)0
#define | CPU_INT_DIS() do { cpu_sr = CPU_SR_Save(); } while (0) /* Save CPU status word & disable interrupts.*/
#define | CPU_INT_EN() do { CPU_SR_Restore(cpu_sr); } while (0) /* Restore CPU status word. */
#define | CPU_CRITICAL_ENTER() do { CPU_INT_DIS(); } while (0) /* Disable interrupts. */
#define | CPU_CRITICAL_EXIT() do { CPU_INT_EN(); } while (0) /* Re-enable interrupts. */
#define | CPU_CFG_LEAD_ZEROS_ASM_PRESENT /* See Note #1. */
#define | CPU_INT_STK_PTR 0u
#define | CPU_INT_RESET 1u
#define | CPU_INT_NMI 2u
#define | CPU_INT_HFAULT 3u
#define | CPU_INT_MEM 4u
#define | CPU_INT_BUSFAULT 5u
#define | CPU_INT_USAGEFAULT 6u
#define | CPU_INT_RSVD_07 7u
#define | CPU_INT_RSVD_08 8u
#define | CPU_INT_RSVD_09 9u
#define | CPU_INT_RSVD_10 10u
#define | CPU_INT_SVCALL 11u
#define | CPU_INT_DBGMON 12u
#define | CPU_INT_RSVD_13 13u
#define | CPU_INT_PENDSV 14u
#define | CPU_INT_SYSTICK 15u
#define | CPU_INT_EXT0 16u
#define | CPU_REG_NVIC_ST_CTRL (*((CPU_REG32 *)(0xE000E010))) /* SysTick Ctrl & Status Reg. */
#define | CPU_REG_NVIC_ST_RELOAD (*((CPU_REG32 *)(0xE000E014))) /* SysTick Reload Value Reg. */
#define | CPU_REG_NVIC_ST_CURRENT (*((CPU_REG32 *)(0xE000E018))) /* SysTick Current Value Reg. */
#define | CPU_REG_NVIC_ST_CAL (*((CPU_REG32 *)(0xE000E01C))) /* SysTick Calibration Value Reg. */
#define | CPU_REG_NVIC_SETEN(n) (*((CPU_REG32 *)(0xE000E100 + (n) * 4u))) /* IRQ Set En Reg. */
#define | CPU_REG_NVIC_CLREN(n) (*((CPU_REG32 *)(0xE000E180 + (n) * 4u))) /* IRQ Clr En Reg. */
#define | CPU_REG_NVIC_SETPEND(n) (*((CPU_REG32 *)(0xE000E200 + (n) * 4u))) /* IRQ Set Pending Reg. */
#define | CPU_REG_NVIC_CLRPEND(n) (*((CPU_REG32 *)(0xE000E280 + (n) * 4u))) /* IRQ Clr Pending Reg. */
#define | CPU_REG_NVIC_ACTIVE(n) (*((CPU_REG32 *)(0xE000E300 + (n) * 4u))) /* IRQ Active Reg. */
#define | CPU_REG_NVIC_PRIO(n) (*((CPU_REG32 *)(0xE000E400 + (n) * 4u))) /* IRQ Prio Reg. */
#define | CPU_REG_NVIC_CPUID (*((CPU_REG32 *)(0xE000ED00))) /* CPUID Base Reg. */
#define | CPU_REG_NVIC_ICSR (*((CPU_REG32 *)(0xE000ED04))) /* Int Ctrl State Reg. */
#define | CPU_REG_NVIC_VTOR (*((CPU_REG32 *)(0xE000ED08))) /* Vect Tbl Offset Reg. */
#define | CPU_REG_NVIC_AIRCR (*((CPU_REG32 *)(0xE000ED0C))) /* App Int/Reset Ctrl Reg. */
#define | CPU_REG_NVIC_SCR (*((CPU_REG32 *)(0xE000ED10))) /* System Ctrl Reg. */
#define | CPU_REG_NVIC_CCR (*((CPU_REG32 *)(0xE000ED14))) /* Cfg Ctrl Reg. */
#define | CPU_REG_NVIC_SHPRI1 (*((CPU_REG32 *)(0xE000ED18))) /* System Handlers 4 to 7 Prio. */
#define | CPU_REG_NVIC_SHPRI2 (*((CPU_REG32 *)(0xE000ED1C))) /* System Handlers 8 to 11 Prio. */
#define | CPU_REG_NVIC_SHPRI3 (*((CPU_REG32 *)(0xE000ED20))) /* System Handlers 12 to 15 Prio. */
#define | CPU_REG_NVIC_SHCSR (*((CPU_REG32 *)(0xE000ED24))) /* System Handler Ctrl & State Reg. */
#define | CPU_REG_NVIC_CFSR (*((CPU_REG32 *)(0xE000ED28))) /* Configurable Fault Status Reg. */
#define | CPU_REG_NVIC_HFSR (*((CPU_REG32 *)(0xE000ED2C))) /* Hard Fault Status Reg. */
#define | CPU_REG_NVIC_DFSR (*((CPU_REG32 *)(0xE000ED30))) /* Debug Fault Status Reg. */
#define | CPU_REG_NVIC_PFR0 (*((CPU_REG32 *)(0xE000ED40))) /* Processor Feature Reg 0. */
#define | CPU_REG_NVIC_PFR1 (*((CPU_REG32 *)(0xE000ED44))) /* Processor Feature Reg 1. */
#define | CPU_REG_NVIC_DFR0 (*((CPU_REG32 *)(0xE000ED48))) /* Debug Feature Reg 0. */
#define | CPU_REG_NVIC_AFR0 (*((CPU_REG32 *)(0xE000ED4C))) /* Aux Feature Reg 0. */
#define | CPU_REG_NVIC_MMFR0 (*((CPU_REG32 *)(0xE000ED50))) /* Memory Model Feature Reg 0. */
#define | CPU_REG_NVIC_MMFR1 (*((CPU_REG32 *)(0xE000ED54))) /* Memory Model Feature Reg 1. */
#define | CPU_REG_NVIC_MMFR2 (*((CPU_REG32 *)(0xE000ED58))) /* Memory Model Feature Reg 2. */
#define | CPU_REG_NVIC_MMFR3 (*((CPU_REG32 *)(0xE000ED5C))) /* Memory Model Feature Reg 3. */
#define | CPU_REG_NVIC_ISAFR0 (*((CPU_REG32 *)(0xE000ED60))) /* ISA Feature Reg 0. */
#define | CPU_REG_NVIC_ISAFR1 (*((CPU_REG32 *)(0xE000ED64))) /* ISA Feature Reg 1. */
#define | CPU_REG_NVIC_ISAFR2 (*((CPU_REG32 *)(0xE000ED68))) /* ISA Feature Reg 2. */
#define | CPU_REG_NVIC_ISAFR3 (*((CPU_REG32 *)(0xE000ED6C))) /* ISA Feature Reg 3. */
#define | CPU_REG_NVIC_ISAFR4 (*((CPU_REG32 *)(0xE000ED70))) /* ISA Feature Reg 4. */
#define | CPU_REG_NVIC_SW_TRIG (*((CPU_REG32 *)(0xE000EF00))) /* Software Trigger Int Reg. */
#define | CPU_REG_MPU_TYPE (*((CPU_REG32 *)(0xE000ED90))) /* MPU Type Reg. */
#define | CPU_REG_MPU_CTRL (*((CPU_REG32 *)(0xE000ED94))) /* MPU Ctrl Reg. */
#define | CPU_REG_MPU_REG_NBR (*((CPU_REG32 *)(0xE000ED98))) /* MPU Region Nbr Reg. */
#define | CPU_REG_MPU_REG_BASE (*((CPU_REG32 *)(0xE000ED9C))) /* MPU Region Base Addr Reg. */
#define | CPU_REG_MPU_REG_ATTR (*((CPU_REG32 *)(0xE000EDA0))) /* MPU Region Attrib & Size Reg. */
#define | CPU_REG_DBG_CTRL (*((CPU_REG32 *)(0xE000EDF0))) /* Debug Halting Ctrl & Status Reg. */
#define | CPU_REG_DBG_SELECT (*((CPU_REG32 *)(0xE000EDF4))) /* Debug Core Reg Selector Reg. */
#define | CPU_REG_DBG_DATA (*((CPU_REG32 *)(0xE000EDF8))) /* Debug Core Reg Data Reg. */
#define | CPU_REG_DBG_INT (*((CPU_REG32 *)(0xE000EDFC))) /* Debug Except & Monitor Ctrl Reg. */
#define | CPU_REG_NVIC_ST_CTRL_COUNTFLAG 0x00010000
#define | CPU_REG_NVIC_ST_CTRL_CLKSOURCE 0x00000004
#define | CPU_REG_NVIC_ST_CTRL_TICKINT 0x00000002
#define | CPU_REG_NVIC_ST_CTRL_ENABLE 0x00000001
#define | CPU_REG_NVIC_ST_CAL_NOREF 0x80000000
#define | CPU_REG_NVIC_ST_CAL_SKEW 0x40000000
#define | CPU_REG_NVIC_ICSR_NMIPENDSET 0x80000000
#define | CPU_REG_NVIC_ICSR_PENDSVSET 0x10000000
#define | CPU_REG_NVIC_ICSR_PENDSVCLR 0x08000000
#define | CPU_REG_NVIC_ICSR_PENDSTSET 0x04000000
#define | CPU_REG_NVIC_ICSR_PENDSTCLR 0x02000000
#define | CPU_REG_NVIC_ICSR_ISRPREEMPT 0x00800000
#define | CPU_REG_NVIC_ICSR_ISRPENDING 0x00400000
#define | CPU_REG_NVIC_ICSR_RETTOBASE 0x00000800
#define | CPU_REG_NVIC_VTOR_TBLBASE 0x20000000
#define | CPU_REG_NVIC_AIRCR_ENDIANNESS 0x00008000
#define | CPU_REG_NVIC_AIRCR_SYSRESETREQ 0x00000004
#define | CPU_REG_NVIC_AIRCR_VECTCLRACTIVE 0x00000002
#define | CPU_REG_NVIC_AIRCR_VECTRESET 0x00000001
#define | CPU_REG_NVIC_SCR_SEVONPEND 0x00000010
#define | CPU_REG_NVIC_SCR_SLEEPDEEP 0x00000004
#define | CPU_REG_NVIC_SCR_SLEEPONEXIT 0x00000002
#define | CPU_REG_NVIC_CCR_STKALIGN 0x00000200
#define | CPU_REG_NVIC_CCR_BFHFNMIGN 0x00000100
#define | CPU_REG_NVIC_CCR_DIV_0_TRP 0x00000010
#define | CPU_REG_NVIC_CCR_UNALIGN_TRP 0x00000008
#define | CPU_REG_NVIC_CCR_USERSETMPEND 0x00000002
#define | CPU_REG_NVIC_CCR_NONBASETHRDENA 0x00000001
#define | CPU_REG_NVIC_SHCSR_USGFAULTENA 0x00040000
#define | CPU_REG_NVIC_SHCSR_BUSFAULTENA 0x00020000
#define | CPU_REG_NVIC_SHCSR_MEMFAULTENA 0x00010000
#define | CPU_REG_NVIC_SHCSR_SVCALLPENDED 0x00008000
#define | CPU_REG_NVIC_SHCSR_BUSFAULTPENDED 0x00004000
#define | CPU_REG_NVIC_SHCSR_MEMFAULTPENDED 0x00002000
#define | CPU_REG_NVIC_SHCSR_USGFAULTPENDED 0x00001000
#define | CPU_REG_NVIC_SHCSR_SYSTICKACT 0x00000800
#define | CPU_REG_NVIC_SHCSR_PENDSVACT 0x00000400
#define | CPU_REG_NVIC_SHCSR_MONITORACT 0x00000100
#define | CPU_REG_NVIC_SHCSR_SVCALLACT 0x00000080
#define | CPU_REG_NVIC_SHCSR_USGFAULTACT 0x00000008
#define | CPU_REG_NVIC_SHCSR_BUSFAULTACT 0x00000002
#define | CPU_REG_NVIC_SHCSR_MEMFAULTACT 0x00000001
#define | CPU_REG_NVIC_CFSR_DIVBYZERO 0x02000000
#define | CPU_REG_NVIC_CFSR_UNALIGNED 0x01000000
#define | CPU_REG_NVIC_CFSR_NOCP 0x00080000
#define | CPU_REG_NVIC_CFSR_INVPC 0x00040000
#define | CPU_REG_NVIC_CFSR_INVSTATE 0x00020000
#define | CPU_REG_NVIC_CFSR_UNDEFINSTR 0x00010000
#define | CPU_REG_NVIC_CFSR_BFARVALID 0x00008000
#define | CPU_REG_NVIC_CFSR_STKERR 0x00001000
#define | CPU_REG_NVIC_CFSR_UNSTKERR 0x00000800
#define | CPU_REG_NVIC_CFSR_IMPRECISERR 0x00000400
#define | CPU_REG_NVIC_CFSR_PRECISERR 0x00000200
#define | CPU_REG_NVIC_CFSR_IBUSERR 0x00000100
#define | CPU_REG_NVIC_CFSR_MMARVALID 0x00000080
#define | CPU_REG_NVIC_CFSR_MSTKERR 0x00000010
#define | CPU_REG_NVIC_CFSR_MUNSTKERR 0x00000008
#define | CPU_REG_NVIC_CFSR_DACCVIOL 0x00000002
#define | CPU_REG_NVIC_CFSR_IACCVIOL 0x00000001
#define | CPU_REG_NVIC_HFSR_DEBUGEVT 0x80000000
#define | CPU_REG_NVIC_HFSR_FORCED 0x40000000
#define | CPU_REG_NVIC_HFSR_VECTTBL 0x00000002
#define | CPU_REG_NVIC_DFSR_EXTERNAL 0x00000010
#define | CPU_REG_NVIC_DFSR_VCATCH 0x00000008
#define | CPU_REG_NVIC_DFSR_DWTTRAP 0x00000004
#define | CPU_REG_NVIC_DFSR_BKPT 0x00000002
#define | CPU_REG_NVIC_DFSR_HALTED 0x00000001
#define | CPU_MSK_NVIC_ICSR_VECT_ACTIVE 0x000001FF

## Typedefs
typedef void | CPU_VOID
typedef char | CPU_CHAR
typedef unsigned char | CPU_BOOLEAN
typedef unsigned char | CPU_INT08U
typedef signed char | CPU_INT08S
typedef unsigned short | CPU_INT16U
typedef signed short | CPU_INT16S
typedef unsigned int | CPU_INT32U
typedef signed int | CPU_INT32S
typedef unsigned long long | CPU_INT64U
typedef signed long long | CPU_INT64S
typedef float | CPU_FP32
typedef double | CPU_FP64
typedef volatile CPU_INT08U | CPU_REG08
typedef volatile CPU_INT16U | CPU_REG16
typedef volatile CPU_INT32U | CPU_REG32
typedef volatile CPU_INT64U | CPU_REG64
typedef void(* | CPU_FNCT_VOID )(void)
typedef void(* | CPU_FNCT_PTR )(void *p_obj)
typedef CPU_INT32U | CPU_ADDR
typedef CPU_INT32U | CPU_DATA
typedef CPU_DATA | CPU_ALIGN
typedef CPU_ADDR | CPU_SIZE_T
typedef CPU_INT32U | CPU_STK
typedef CPU_ADDR | CPU_STK_SIZE
typedef CPU_INT32U | CPU_SR

## Functions
void | CPU_IntDis (void)
void | CPU_IntEn (void)
void | CPU_IntSrcDis (CPU_INT08U pos)
void | CPU_IntSrcEn (CPU_INT08U pos)
void | CPU_IntSrcPendClr (CPU_INT08U pos)
CPU_INT16S | CPU_IntSrcPrioGet (CPU_INT08U pos)
void | CPU_IntSrcPrioSet (CPU_INT08U pos, CPU_INT08U prio)
CPU_SR | CPU_SR_Save (void)
void | CPU_SR_Restore (CPU_SR cpu_sr)
CPU_DATA | CPU_CntLeadZeros (CPU_DATA val)
CPU_DATA | CPU_RevBits (CPU_DATA val)
void | CPU_WaitForInt (void)
void | CPU_WaitForExcept (void)
void | CPU_BitBandClr (CPU_ADDR addr, CPU_INT08U bit_nbr)
void | CPU_BitBandSet (CPU_ADDR addr, CPU_INT08U bit_nbr)

## Macro Definition Documentation

#define CPU_CFG_ADDR_SIZE CPU_WORD_SIZE_32 /* Defines CPU address word size (in octets). */

Definition at line 165 of file cpu.h.

#define CPU_CFG_CRITICAL_METHOD CPU_CRITICAL_METHOD_STATUS_LOCAL

Definition at line 293 of file cpu.h.

#define CPU_CFG_DATA_SIZE CPU_WORD_SIZE_32 /* Defines CPU data word size (in octets). */

Definition at line 166 of file cpu.h.

#define CPU_CFG_ENDIAN_TYPE CPU_ENDIAN_TYPE_LITTLE /* Defines CPU data word-memory order (see Note #2). */

Definition at line 168 of file cpu.h.

#define CPU_CFG_LEAD_ZEROS_ASM_PRESENT /* See Note #1. */

Definition at line 360 of file cpu.h.

#define CPU_CFG_STK_GROWTH CPU_STK_GROWTH_HI_TO_LO /* Defines CPU stack growth order (see Note #1). */

Definition at line 213 of file cpu.h.

#define CPU_CRITICAL_ENTER | ( |  | ) | do { CPU_INT_DIS(); } while (0) /* Disable interrupts. */

Definition at line 322 of file cpu.h.

#define CPU_CRITICAL_EXIT | ( |  | ) | do { CPU_INT_EN(); } while (0) /* Re-enable interrupts. */

Definition at line 323 of file cpu.h.

#define CPU_INT_BUSFAULT 5u

Definition at line 388 of file cpu.h.

#define CPU_INT_DBGMON 12u

Definition at line 395 of file cpu.h.

#define CPU_INT_DIS | ( |  | ) | do { cpu_sr = CPU_SR_Save(); } while (0) /* Save CPU status word & disable interrupts.*/

Definition at line 306 of file cpu.h.

#define CPU_INT_EN | ( |  | ) | do { CPU_SR_Restore(cpu_sr); } while (0) /* Restore CPU status word. */

Definition at line 307 of file cpu.h.

#define CPU_INT_EXT0 16u

Definition at line 399 of file cpu.h.

#define CPU_INT_HFAULT 3u

Definition at line 386 of file cpu.h.

#define CPU_INT_MEM 4u

Definition at line 387 of file cpu.h.

#define CPU_INT_NMI 2u

Definition at line 385 of file cpu.h.

#define CPU_INT_PENDSV 14u

Definition at line 397 of file cpu.h.

#define CPU_INT_RESET 1u

Definition at line 384 of file cpu.h.

#define CPU_INT_RSVD_07 7u

Definition at line 390 of file cpu.h.

#define CPU_INT_RSVD_08 8u

Definition at line 391 of file cpu.h.

#define CPU_INT_RSVD_09 9u

Definition at line 392 of file cpu.h.

#define CPU_INT_RSVD_10 10u

Definition at line 393 of file cpu.h.

#define CPU_INT_RSVD_13 13u

Definition at line 396 of file cpu.h.

#define CPU_INT_STK_PTR 0u

Definition at line 383 of file cpu.h.

#define CPU_INT_SVCALL 11u

Definition at line 394 of file cpu.h.

#define CPU_INT_SYSTICK 15u

Definition at line 398 of file cpu.h.

#define CPU_INT_USAGEFAULT 6u

Definition at line 389 of file cpu.h.

#define CPU_MSK_NVIC_ICSR_VECT_ACTIVE 0x000001FF

Definition at line 569 of file cpu.h.

#define CPU_REG_DBG_CTRL (*((CPU_REG32 *)(0xE000EDF0))) /* Debug Halting Ctrl & Status Reg. */

Definition at line 459 of file cpu.h.

#define CPU_REG_DBG_DATA (*((CPU_REG32 *)(0xE000EDF8))) /* Debug Core Reg Data Reg. */

Definition at line 461 of file cpu.h.

#define CPU_REG_DBG_INT (*((CPU_REG32 *)(0xE000EDFC))) /* Debug Except & Monitor Ctrl Reg. */

Definition at line 462 of file cpu.h.

#define CPU_REG_DBG_SELECT (*((CPU_REG32 *)(0xE000EDF4))) /* Debug Core Reg Selector Reg. */

Definition at line 460 of file cpu.h.

#define CPU_REG_MPU_CTRL (*((CPU_REG32 *)(0xE000ED94))) /* MPU Ctrl Reg. */

Definition at line 454 of file cpu.h.

#define CPU_REG_MPU_REG_ATTR (*((CPU_REG32 *)(0xE000EDA0))) /* MPU Region Attrib & Size Reg. */

Definition at line 457 of file cpu.h.

#define CPU_REG_MPU_REG_BASE (*((CPU_REG32 *)(0xE000ED9C))) /* MPU Region Base Addr Reg. */

Definition at line 456 of file cpu.h.

#define CPU_REG_MPU_REG_NBR (*((CPU_REG32 *)(0xE000ED98))) /* MPU Region Nbr Reg. */

Definition at line 455 of file cpu.h.

#define CPU_REG_MPU_TYPE (*((CPU_REG32 *)(0xE000ED90))) /* MPU Type Reg. */

Definition at line 453 of file cpu.h.

#define CPU_REG_NVIC_ACTIVE | ( |  | n | ) | (*((CPU_REG32 *)(0xE000E300 + (n) * 4u))) /* IRQ Active Reg. */

Definition at line 418 of file cpu.h.

#define CPU_REG_NVIC_AFR0 (*((CPU_REG32 *)(0xE000ED4C))) /* Aux Feature Reg 0. */

Definition at line 441 of file cpu.h.

#define CPU_REG_NVIC_AIRCR (*((CPU_REG32 *)(0xE000ED0C))) /* App Int/Reset Ctrl Reg. */

Definition at line 424 of file cpu.h.

#define CPU_REG_NVIC_AIRCR_ENDIANNESS 0x00008000

Definition at line 497 of file cpu.h.

#define CPU_REG_NVIC_AIRCR_SYSRESETREQ 0x00000004

Definition at line 498 of file cpu.h.

#define CPU_REG_NVIC_AIRCR_VECTCLRACTIVE 0x00000002

Definition at line 499 of file cpu.h.

#define CPU_REG_NVIC_AIRCR_VECTRESET 0x00000001

Definition at line 500 of file cpu.h.

#define CPU_REG_NVIC_CCR (*((CPU_REG32 *)(0xE000ED14))) /* Cfg Ctrl Reg. */

Definition at line 426 of file cpu.h.

#define CPU_REG_NVIC_CCR_BFHFNMIGN 0x00000100

Definition at line 509 of file cpu.h.

#define CPU_REG_NVIC_CCR_DIV_0_TRP 0x00000010

Definition at line 510 of file cpu.h.

#define CPU_REG_NVIC_CCR_NONBASETHRDENA 0x00000001

Definition at line 513 of file cpu.h.

#define CPU_REG_NVIC_CCR_STKALIGN 0x00000200

Definition at line 508 of file cpu.h.

#define CPU_REG_NVIC_CCR_UNALIGN_TRP 0x00000008

Definition at line 511 of file cpu.h.

#define CPU_REG_NVIC_CCR_USERSETMPEND 0x00000002

Definition at line 512 of file cpu.h.

#define CPU_REG_NVIC_CFSR (*((CPU_REG32 *)(0xE000ED28))) /* Configurable Fault Status Reg. */

Definition at line 431 of file cpu.h.

#define CPU_REG_NVIC_CFSR_BFARVALID 0x00008000

Definition at line 538 of file cpu.h.

#define CPU_REG_NVIC_CFSR_DACCVIOL 0x00000002

Definition at line 547 of file cpu.h.

#define CPU_REG_NVIC_CFSR_DIVBYZERO 0x02000000

Definition at line 532 of file cpu.h.

#define CPU_REG_NVIC_CFSR_IACCVIOL 0x00000001

Definition at line 548 of file cpu.h.

#define CPU_REG_NVIC_CFSR_IBUSERR 0x00000100

Definition at line 543 of file cpu.h.

#define CPU_REG_NVIC_CFSR_IMPRECISERR 0x00000400

Definition at line 541 of file cpu.h.

#define CPU_REG_NVIC_CFSR_INVPC 0x00040000

Definition at line 535 of file cpu.h.

#define CPU_REG_NVIC_CFSR_INVSTATE 0x00020000

Definition at line 536 of file cpu.h.

#define CPU_REG_NVIC_CFSR_MMARVALID 0x00000080

Definition at line 544 of file cpu.h.

#define CPU_REG_NVIC_CFSR_MSTKERR 0x00000010

Definition at line 545 of file cpu.h.

#define CPU_REG_NVIC_CFSR_MUNSTKERR 0x00000008

Definition at line 546 of file cpu.h.

#define CPU_REG_NVIC_CFSR_NOCP 0x00080000

Definition at line 534 of file cpu.h.

#define CPU_REG_NVIC_CFSR_PRECISERR 0x00000200

Definition at line 542 of file cpu.h.

#define CPU_REG_NVIC_CFSR_STKERR 0x00001000

Definition at line 539 of file cpu.h.

#define CPU_REG_NVIC_CFSR_UNALIGNED 0x01000000

Definition at line 533 of file cpu.h.

#define CPU_REG_NVIC_CFSR_UNDEFINSTR 0x00010000

Definition at line 537 of file cpu.h.

#define CPU_REG_NVIC_CFSR_UNSTKERR 0x00000800

Definition at line 540 of file cpu.h.

#define CPU_REG_NVIC_CLREN | ( |  | n | ) | (*((CPU_REG32 *)(0xE000E180 + (n) * 4u))) /* IRQ Clr En Reg. */

Definition at line 415 of file cpu.h.

#define CPU_REG_NVIC_CLRPEND | ( |  | n | ) | (*((CPU_REG32 *)(0xE000E280 + (n) * 4u))) /* IRQ Clr Pending Reg. */

Definition at line 417 of file cpu.h.

#define CPU_REG_NVIC_CPUID (*((CPU_REG32 *)(0xE000ED00))) /* CPUID Base Reg. */

Definition at line 421 of file cpu.h.

#define CPU_REG_NVIC_DFR0 (*((CPU_REG32 *)(0xE000ED48))) /* Debug Feature Reg 0. */

Definition at line 440 of file cpu.h.

#define CPU_REG_NVIC_DFSR (*((CPU_REG32 *)(0xE000ED30))) /* Debug Fault Status Reg. */

Definition at line 433 of file cpu.h.

#define CPU_REG_NVIC_DFSR_BKPT 0x00000002

Definition at line 559 of file cpu.h.

#define CPU_REG_NVIC_DFSR_DWTTRAP 0x00000004

Definition at line 558 of file cpu.h.

#define CPU_REG_NVIC_DFSR_EXTERNAL 0x00000010

Definition at line 556 of file cpu.h.

#define CPU_REG_NVIC_DFSR_HALTED 0x00000001

Definition at line 560 of file cpu.h.

#define CPU_REG_NVIC_DFSR_VCATCH 0x00000008

Definition at line 557 of file cpu.h.

#define CPU_REG_NVIC_HFSR (*((CPU_REG32 *)(0xE000ED2C))) /* Hard Fault Status Reg. */

Definition at line 432 of file cpu.h.

#define CPU_REG_NVIC_HFSR_DEBUGEVT 0x80000000

Definition at line 551 of file cpu.h.

#define CPU_REG_NVIC_HFSR_FORCED 0x40000000

Definition at line 552 of file cpu.h.

#define CPU_REG_NVIC_HFSR_VECTTBL 0x00000002

Definition at line 553 of file cpu.h.

#define CPU_REG_NVIC_ICSR (*((CPU_REG32 *)(0xE000ED04))) /* Int Ctrl State Reg. */

Definition at line 422 of file cpu.h.

#define CPU_REG_NVIC_ICSR_ISRPENDING 0x00400000

Definition at line 490 of file cpu.h.

#define CPU_REG_NVIC_ICSR_ISRPREEMPT 0x00800000

Definition at line 489 of file cpu.h.

#define CPU_REG_NVIC_ICSR_NMIPENDSET 0x80000000

Definition at line 484 of file cpu.h.

#define CPU_REG_NVIC_ICSR_PENDSTCLR 0x02000000

Definition at line 488 of file cpu.h.

#define CPU_REG_NVIC_ICSR_PENDSTSET 0x04000000

Definition at line 487 of file cpu.h.

#define CPU_REG_NVIC_ICSR_PENDSVCLR 0x08000000

Definition at line 486 of file cpu.h.

#define CPU_REG_NVIC_ICSR_PENDSVSET 0x10000000

Definition at line 485 of file cpu.h.

#define CPU_REG_NVIC_ICSR_RETTOBASE 0x00000800

Definition at line 491 of file cpu.h.

#define CPU_REG_NVIC_ISAFR0 (*((CPU_REG32 *)(0xE000ED60))) /* ISA Feature Reg 0. */

Definition at line 446 of file cpu.h.

#define CPU_REG_NVIC_ISAFR1 (*((CPU_REG32 *)(0xE000ED64))) /* ISA Feature Reg 1. */

Definition at line 447 of file cpu.h.

#define CPU_REG_NVIC_ISAFR2 (*((CPU_REG32 *)(0xE000ED68))) /* ISA Feature Reg 2. */

Definition at line 448 of file cpu.h.

#define CPU_REG_NVIC_ISAFR3 (*((CPU_REG32 *)(0xE000ED6C))) /* ISA Feature Reg 3. */

Definition at line 449 of file cpu.h.

#define CPU_REG_NVIC_ISAFR4 (*((CPU_REG32 *)(0xE000ED70))) /* ISA Feature Reg 4. */

Definition at line 450 of file cpu.h.

#define CPU_REG_NVIC_MMFR0 (*((CPU_REG32 *)(0xE000ED50))) /* Memory Model Feature Reg 0. */

Definition at line 442 of file cpu.h.

#define CPU_REG_NVIC_MMFR1 (*((CPU_REG32 *)(0xE000ED54))) /* Memory Model Feature Reg 1. */

Definition at line 443 of file cpu.h.

#define CPU_REG_NVIC_MMFR2 (*((CPU_REG32 *)(0xE000ED58))) /* Memory Model Feature Reg 2. */

Definition at line 444 of file cpu.h.

#define CPU_REG_NVIC_MMFR3 (*((CPU_REG32 *)(0xE000ED5C))) /* Memory Model Feature Reg 3. */

Definition at line 445 of file cpu.h.

#define CPU_REG_NVIC_PFR0 (*((CPU_REG32 *)(0xE000ED40))) /* Processor Feature Reg 0. */

Definition at line 438 of file cpu.h.

#define CPU_REG_NVIC_PFR1 (*((CPU_REG32 *)(0xE000ED44))) /* Processor Feature Reg 1. */

Definition at line 439 of file cpu.h.

#define CPU_REG_NVIC_PRIO | ( |  | n | ) | (*((CPU_REG32 *)(0xE000E400 + (n) * 4u))) /* IRQ Prio Reg. */

Definition at line 419 of file cpu.h.

#define CPU_REG_NVIC_SCR (*((CPU_REG32 *)(0xE000ED10))) /* System Ctrl Reg. */

Definition at line 425 of file cpu.h.

#define CPU_REG_NVIC_SCR_SEVONPEND 0x00000010

Definition at line 503 of file cpu.h.

#define CPU_REG_NVIC_SCR_SLEEPDEEP 0x00000004

Definition at line 504 of file cpu.h.

#define CPU_REG_NVIC_SCR_SLEEPONEXIT 0x00000002

Definition at line 505 of file cpu.h.

#define CPU_REG_NVIC_SETEN | ( |  | n | ) | (*((CPU_REG32 *)(0xE000E100 + (n) * 4u))) /* IRQ Set En Reg. */

Definition at line 414 of file cpu.h.

#define CPU_REG_NVIC_SETPEND | ( |  | n | ) | (*((CPU_REG32 *)(0xE000E200 + (n) * 4u))) /* IRQ Set Pending Reg. */

Definition at line 416 of file cpu.h.

#define CPU_REG_NVIC_SHCSR (*((CPU_REG32 *)(0xE000ED24))) /* System Handler Ctrl & State Reg. */

Definition at line 430 of file cpu.h.

#define CPU_REG_NVIC_SHCSR_BUSFAULTACT 0x00000002

Definition at line 528 of file cpu.h.

#define CPU_REG_NVIC_SHCSR_BUSFAULTENA 0x00020000

Definition at line 517 of file cpu.h.

#define CPU_REG_NVIC_SHCSR_BUSFAULTPENDED 0x00004000

Definition at line 520 of file cpu.h.

#define CPU_REG_NVIC_SHCSR_MEMFAULTACT 0x00000001

Definition at line 529 of file cpu.h.

#define CPU_REG_NVIC_SHCSR_MEMFAULTENA 0x00010000

Definition at line 518 of file cpu.h.

#define CPU_REG_NVIC_SHCSR_MEMFAULTPENDED 0x00002000

Definition at line 521 of file cpu.h.

#define CPU_REG_NVIC_SHCSR_MONITORACT 0x00000100

Definition at line 525 of file cpu.h.

#define CPU_REG_NVIC_SHCSR_PENDSVACT 0x00000400

Definition at line 524 of file cpu.h.

#define CPU_REG_NVIC_SHCSR_SVCALLACT 0x00000080

Definition at line 526 of file cpu.h.

#define CPU_REG_NVIC_SHCSR_SVCALLPENDED 0x00008000

Definition at line 519 of file cpu.h.

#define CPU_REG_NVIC_SHCSR_SYSTICKACT 0x00000800

Definition at line 523 of file cpu.h.

#define CPU_REG_NVIC_SHCSR_USGFAULTACT 0x00000008

Definition at line 527 of file cpu.h.

#define CPU_REG_NVIC_SHCSR_USGFAULTENA 0x00040000

Definition at line 516 of file cpu.h.

#define CPU_REG_NVIC_SHCSR_USGFAULTPENDED 0x00001000

Definition at line 522 of file cpu.h.

#define CPU_REG_NVIC_SHPRI1 (*((CPU_REG32 *)(0xE000ED18))) /* System Handlers 4 to 7 Prio. */

Definition at line 427 of file cpu.h.

#define CPU_REG_NVIC_SHPRI2 (*((CPU_REG32 *)(0xE000ED1C))) /* System Handlers 8 to 11 Prio. */

Definition at line 428 of file cpu.h.

#define CPU_REG_NVIC_SHPRI3 (*((CPU_REG32 *)(0xE000ED20))) /* System Handlers 12 to 15 Prio. */

Definition at line 429 of file cpu.h.

#define CPU_REG_NVIC_ST_CAL (*((CPU_REG32 *)(0xE000E01C))) /* SysTick Calibration Value Reg. */

Definition at line 412 of file cpu.h.

#define CPU_REG_NVIC_ST_CAL_NOREF 0x80000000

Definition at line 480 of file cpu.h.

#define CPU_REG_NVIC_ST_CAL_SKEW 0x40000000

Definition at line 481 of file cpu.h.

#define CPU_REG_NVIC_ST_CTRL (*((CPU_REG32 *)(0xE000E010))) /* SysTick Ctrl & Status Reg. */

Definition at line 409 of file cpu.h.

#define CPU_REG_NVIC_ST_CTRL_CLKSOURCE 0x00000004

Definition at line 474 of file cpu.h.

#define CPU_REG_NVIC_ST_CTRL_COUNTFLAG 0x00010000

Definition at line 473 of file cpu.h.

#define CPU_REG_NVIC_ST_CTRL_ENABLE 0x00000001

Definition at line 476 of file cpu.h.

#define CPU_REG_NVIC_ST_CTRL_TICKINT 0x00000002

Definition at line 475 of file cpu.h.

#define CPU_REG_NVIC_ST_CURRENT (*((CPU_REG32 *)(0xE000E018))) /* SysTick Current Value Reg. */

Definition at line 411 of file cpu.h.

#define CPU_REG_NVIC_ST_RELOAD (*((CPU_REG32 *)(0xE000E014))) /* SysTick Reload Value Reg. */

Definition at line 410 of file cpu.h.

#define CPU_REG_NVIC_SW_TRIG (*((CPU_REG32 *)(0xE000EF00))) /* Software Trigger Int Reg. */

Definition at line 451 of file cpu.h.

#define CPU_REG_NVIC_VTOR (*((CPU_REG32 *)(0xE000ED08))) /* Vect Tbl Offset Reg. */

Definition at line 423 of file cpu.h.

#define CPU_REG_NVIC_VTOR_TBLBASE 0x20000000

Definition at line 494 of file cpu.h.

#define CPU_SR_ALLOC | ( |  | ) | CPU_SR cpu_sr = (CPU_SR)0

Definition at line 299 of file cpu.h.

## Typedef Documentation

typedef CPU_INT32U CPU_ADDR

Definition at line 179 of file cpu.h.

typedef CPU_DATA CPU_ALIGN

Definition at line 196 of file cpu.h.

typedef unsigned char CPU_BOOLEAN

Definition at line 117 of file cpu.h.

typedef char CPU_CHAR

Definition at line 116 of file cpu.h.

typedef CPU_INT32U CPU_DATA

Definition at line 188 of file cpu.h.

typedef void(* CPU_FNCT_PTR)(void *p_obj)

Definition at line 138 of file cpu.h.

typedef void(* CPU_FNCT_VOID)(void)

Definition at line 137 of file cpu.h.

typedef float CPU_FP32

Definition at line 127 of file cpu.h.

typedef double CPU_FP64

Definition at line 128 of file cpu.h.

typedef signed char CPU_INT08S

Definition at line 119 of file cpu.h.

typedef unsigned char CPU_INT08U

Definition at line 118 of file cpu.h.

typedef signed short CPU_INT16S

Definition at line 121 of file cpu.h.

typedef unsigned short CPU_INT16U

Definition at line 120 of file cpu.h.

typedef signed int CPU_INT32S

Definition at line 123 of file cpu.h.

typedef unsigned int CPU_INT32U

Definition at line 122 of file cpu.h.

typedef signed long long CPU_INT64S

Definition at line 125 of file cpu.h.

typedef unsigned long long CPU_INT64U

Definition at line 124 of file cpu.h.

typedef volatile CPU_INT08U CPU_REG08

Definition at line 131 of file cpu.h.

typedef volatile CPU_INT16U CPU_REG16

Definition at line 132 of file cpu.h.

typedef volatile CPU_INT32U CPU_REG32

Definition at line 133 of file cpu.h.

typedef volatile CPU_INT64U CPU_REG64

Definition at line 134 of file cpu.h.

typedef CPU_ADDR CPU_SIZE_T

Definition at line 197 of file cpu.h.

typedef CPU_INT32U CPU_SR

Definition at line 295 of file cpu.h.

typedef CPU_INT32U CPU_STK

Definition at line 215 of file cpu.h.

typedef CPU_ADDR CPU_STK_SIZE

Definition at line 216 of file cpu.h.

typedef void CPU_VOID

Definition at line 115 of file cpu.h.

## Function Documentation

void CPU_BitBandClr | ( | CPU_ADDR | addr,
|  | CPU_INT08U | bit_nbr
| ) |  |

Definition at line 132 of file cpu_c_m0.c.

void CPU_BitBandSet | ( | CPU_ADDR | addr,
|  | CPU_INT08U | bit_nbr
| ) |  |

Definition at line 175 of file cpu_c_m0.c.

CPU_DATA CPU_CntLeadZeros | ( | CPU_DATA | val | ) |

Definition at line 349 of file os_cpu_c_m0.c.

void CPU_IntDis | ( | void |  | ) |

void CPU_IntEn | ( | void |  | ) |

void CPU_IntSrcDis | ( | CPU_INT08U | pos | ) |

Definition at line 249 of file cpu_c_m0.c.

void CPU_IntSrcEn | ( | CPU_INT08U | pos | ) |

Definition at line 338 of file cpu_c_m0.c.

void CPU_IntSrcPendClr | ( | CPU_INT08U | pos | ) |

Definition at line 437 of file cpu_c_m0.c.

CPU_INT16S CPU_IntSrcPrioGet | ( | CPU_INT08U | pos | ) |

Definition at line 644 of file cpu_c_m0.c.

void CPU_IntSrcPrioSet | ( | CPU_INT08U | pos,
|  | CPU_INT08U | prio
| ) |  |

Definition at line 509 of file cpu_c_m0.c.

CPU_DATA CPU_RevBits | ( | CPU_DATA | val | ) |

void CPU_SR_Restore | ( | CPU_SR | cpu_sr | ) |

CPU_SR CPU_SR_Save | ( | void |  | ) |

void CPU_WaitForExcept | ( | void |  | ) |

void CPU_WaitForInt | ( | void |  | ) |