| LPCOpen Platform v1.03 LPCOpen Platform for NXP LPC Microcontrollers

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chip_clocks.h File Reference
`#include "sys_config.h"`

Go to the source code of this file.

## Enumerations
enum | CHIP_CGU_CLKIN_T { CLKIN_32K, CLKIN_IRC, CLKIN_ENET_RX, CLKIN_ENET_TX, CLKIN_CLKIN, CLKIN_RESERVED1, CLKIN_CRYSTAL, CLKIN_USBPLL, CLKIN_AUDIOPLL, CLKIN_MAINPLL, CLKIN_RESERVED2, CLKIN_RESERVED3, CLKIN_IDIVA, CLKIN_IDIVB, CLKIN_IDIVC, CLKIN_IDIVD, CLKIN_IDIVE, CLKINPUT_PD }
| CGU clock input list These are possible input clocks for the CGU and can come from both external (crystal) and internal (PLL) sources. These clock inputs can be routed to the base clocks (CHIP_CGU_BASE_CLK_T). More...
enum | CHIP_CGU_BASE_CLK_T { CLK_BASE_SAFE, CLK_BASE_USB0, CLK_BASE_RESERVED1, CLK_BASE_USB1, CLK_BASE_MX, CLK_BASE_SPIFI, CLK_BASE_RESERVED2, CLK_BASE_PHY_RX, CLK_BASE_PHY_TX, CLK_BASE_APB1, CLK_BASE_APB3, CLK_BASE_LCD, CLK_BASE_RESERVED3, CLK_BASE_SDIO, CLK_BASE_SSP0, CLK_BASE_SSP1, CLK_BASE_UART0, CLK_BASE_UART1, CLK_BASE_UART2, CLK_BASE_UART3, CLK_BASE_OUT, CLK_BASE_RESERVED4, CLK_BASE_RESERVED5, CLK_BASE_RESERVED6, CLK_BASE_RESERVED7, CLK_BASE_APLL, CLK_BASE_CGU_OUT0, CLK_BASE_CGU_OUT1, CLK_BASE_LAST, CLK_BASE_NONE = CLK_BASE_LAST }
| CGU base clocks CGU base clocks are clocks that are associated with a single input clock and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH clock can be configured to use the CLKIN_MAINPLL input clock, which will in turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and CLK_PERIPH_SGPIO periphral clocks. More...
enum | CHIP_CGU_IDIV_T { CLK_IDIV_A, CLK_IDIV_B, CLK_IDIV_C, CLK_IDIV_D, CLK_IDIV_E, CLK_IDIV_LAST }
| CGU dividers CGU dividers provide an extra clock state where a specific clock can be divided before being routed to a peripheral group. A divider accepts an input clock and then divides it. To use the divided clock for a base clock group, use the divider as the input clock for the base clock (for example, use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider). More...
enum | CHIP_CCU_CLK_T { CLK_APB3_BUS, CLK_APB3_I2C1, CLK_APB3_DAC, CLK_APB3_ADC0, CLK_APB3_ADC1, CLK_APB3_CAN0, CLK_APB1_BUS = 32, CLK_APB1_MOTOCON, CLK_APB1_I2C0, CLK_APB1_I2S, CLK_APB1_CAN1, CLK_SPIFI = 64, CLK_MX_BUS = 96, CLK_MX_SPIFI, CLK_MX_GPIO, CLK_MX_LCD, CLK_MX_ETHERNET, CLK_MX_USB0, CLK_MX_EMC, CLK_MX_SDIO, CLK_MX_DMA, CLK_MX_MXCORE, RESERVED_ALIGN = CLK_MX_MXCORE + 3, CLK_MX_SCT, CLK_MX_USB1, CLK_MX_EMC_DIV, CLK_MX_FLASHA, CLK_MX_FLASHB, CLK_RESERVED1, CLK_RESERVED2, CLK_MX_EEPROM, CLK_MX_WWDT = 128, CLK_MX_UART0, CLK_MX_UART1, CLK_MX_SSP0, CLK_MX_TIMER0, CLK_MX_TIMER1, CLK_MX_SCU, CLK_MX_CREG, CLK_MX_RITIMER = 160, CLK_MX_UART2, CLK_MX_UART3, CLK_MX_TIMER2, CLK_MX_TIMER3, CLK_MX_SSP1, CLK_MX_QEI, CLK_RESERVED3 = 192, CLK_RESERVED3A, CLK_RESERVED4, CLK_RESERVED5, CLK_USB0 = 224, CLK_USB1 = 256, CLK_RESERVED7 = 320, CLK_RESERVED8, CLK_CCU1_LAST, CLK_CCU2_START, CLK_APLL = CLK_CCU2_START, RESERVED_ALIGNB = CLK_CCU2_START + 31, CLK_APB2_UART3, RESERVED_ALIGNC = CLK_CCU2_START + 63, CLK_APB2_UART2, RESERVED_ALIGND = CLK_CCU2_START + 95, CLK_APB0_UART1, RESERVED_ALIGNE = CLK_CCU2_START + 127, CLK_APB0_UART0, RESERVED_ALIGNF = CLK_CCU2_START + 159, CLK_APB2_SSP1, RESERVED_ALIGNG = CLK_CCU2_START + 191, CLK_APB0_SSP0, RESERVED_ALIGNH = CLK_CCU2_START + 223, CLK_APB2_SDIO, CLK_CCU2_LAST }
| Peripheral clocks Peripheral clocks are individual clocks routed to peripherals. Although multiple peripherals may share a same base clock, each peripheral's clock can be enabled or disabled individually. Some peripheral clocks also have additional dividers associated with them. More...