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syscon_8xx.h
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1 /*
2 * @brief LPC8xx System & Control driver inclusion file
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __SYSCTL_8XX_H_
33 #define __SYSCTL_8XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
47 #define SYSCTL_RST_POR (1 << 0)
48 #define SYSCTL_RST_EXTRST (1 << 1)
49 #define SYSCTL_RST_WDT (1 << 2)
50 #define SYSCTL_RST_BOD (1 << 3)
51 #define SYSCTL_RST_SYSRST (1 << 4)
56 #define SYSCTL_WAKEUP_SPI0TINT (1 << 0)
57 #define SYSCTL_WAKEUP_SPI1INT (1 << 1)
58 #define SYSCTL_WAKEUP_USART0INT (1 << 3)
59 #define SYSCTL_WAKEUP_USART1INT (1 << 4)
60 #define SYSCTL_WAKEUP_USART2INT (1 << 5)
61 #define SYSCTL_WAKEUP_I2CINT (1 << 8)
62 #define SYSCTL_WAKEUP_WWDTINT (1 << 12)
63 #define SYSCTL_WAKEUP_BODINT (1 << 13)
64 #define SYSCTL_WAKEUP_WKTINT (1 << 15)
69 #define SYSCTL_DEEPSLP_BOD_PD (1 << 3)
70 #define SYSCTL_DEEPSLP_WDTOSC_PD (1 << 6)
75 #define SYSCTL_SLPWAKE_IRCOUT_PD (1 << 0)
76 #define SYSCTL_SLPWAKE_IRC_PD (1 << 1)
77 #define SYSCTL_SLPWAKE_FLASH_PD (1 << 2)
78 #define SYSCTL_SLPWAKE_BOD_PD (1 << 3)
79 #define SYSCTL_SLPWAKE_SYSOSC_PD (1 << 5)
80 #define SYSCTL_SLPWAKE_WDTOSC_PD (1 << 6)
81 #define SYSCTL_SLPWAKE_SYSPLL_PD (1 << 7)
82 #define SYSCTL_SLPWAKE_ACMP_PD (1 << 15)
87 #define SYSCTL_NMISRC_ENABLE ((uint32_t) 1 << 31)
92 typedef struct {
93 __IO uint32_t SYSMEMREMAP;
94 __IO uint32_t PRESETCTRL;
95 __IO uint32_t SYSPLLCTRL;
96 __IO uint32_t SYSPLLSTAT;
97 uint32_t RESERVED0[4];
98 __IO uint32_t SYSOSCCTRL;
99 __IO uint32_t WDTOSCCTRL;
100 uint32_t RESERVED1[2];
101 __IO uint32_t SYSRSTSTAT;
102 uint32_t RESERVED2[3];
103 __IO uint32_t SYSPLLCLKSEL;
104 __IO uint32_t SYSPLLCLKUEN;
105 uint32_t RESERVED3[10];
106 __IO uint32_t MAINCLKSEL;
107 __IO uint32_t MAINCLKUEN;
108 __IO uint32_t SYSAHBCLKDIV;
109 uint32_t RESERVED4[1];
110 __IO uint32_t SYSAHBCLKCTRL;
111 uint32_t RESERVED5[4];
112 __IO uint32_t UARTCLKDIV;
113 uint32_t RESERVED6[18];
114 __IO uint32_t CLKOUTSEL;
115 __IO uint32_t CLKOUTUEN;
116 __IO uint32_t CLKOUTDIV;
117 uint32_t RESERVED7;
118 __IO uint32_t UARTFRGDIV;
119 __IO uint32_t UARTFRGMULT;
120 uint32_t RESERVED8[1];
121 __IO uint32_t EXTTRACECMD;
122 __IO uint32_t PIOPORCAP0;
123 uint32_t RESERVED9[12];
124 __IO uint32_t IOCONCLKDIV[7];
125 __IO uint32_t BODCTRL;
126 __IO uint32_t SYSTCKCAL;
127 uint32_t RESERVED10[6];
128 __IO uint32_t IRQLATENCY;
129 __IO uint32_t NMISRC;
130 __IO uint32_t PINTSEL[8];
131 uint32_t RESERVED11[27];
132 __IO uint32_t STARTERP0;
133 uint32_t RESERVED12[3];
134 __IO uint32_t STARTERP1;
135 uint32_t RESERVED13[6];
136 __IO uint32_t PDSLEEPCFG;
137 __IO uint32_t PDAWAKECFG;
138 __IO uint32_t PDRUNCFG;
139 uint32_t RESERVED14[110];
140 __I uint32_t DEVICEID;
141 } LPC_SYSCTL_T;
142
146 typedef enum CHIP_SYSCTL_BOOT_MODE_REMAP {
147 REMAP_BOOT_LOADER_MODE,
148 REMAP_USER_RAM_MODE,
149 REMAP_USER_FLASH_MODE
150 } CHIP_SYSCTL_BOOT_MODE_REMAP_T;
151
155 typedef enum {
156 RESET_SPI0,
157 RESET_SPI1,
158 RESET_UARTFBRG,
159 RESET_USART0,
160 RESET_USART1,
161 RESET_USART2,
162 RESET_I2C,
163 RESET_MRT,
164 RESET_SCT,
165 RESET_WKT,
166 RESET_GPIO,
167 RESET_FLASH,
168 RESET_ACMP
169 } CHIP_SYSCTL_PERIPH_RESET_T;
170
174 typedef enum CHIP_SYSCTL_BODRSTLVL {
175 SYSCTL_BODRSTLVL_0,
176 SYSCTL_BODRSTLVL_1,
177 SYSCTL_BODRSTLVL_2,
178 SYSCTL_BODRSTLVL_3,
179 } CHIP_SYSCTL_BODRSTLVL_T;
180
184 typedef enum CHIP_SYSCTL_BODRINTVAL {
185 SYSCTL_BODINTVAL_LVL0, /* Brown-out interrupt at 1.65 ~ 1.80v */
186 SYSCTL_BODINTVAL_LVL1, /* Brown-out interrupt at 2.22v ~ 2.35v*/
187 SYSCTL_BODINTVAL_LVL2, /* Brown-out interrupt at 2.52v ~ 2.66v */
188 SYSCTL_BODINTVAL_LVL3, /* Brown-out interrupt at 2.80v ~ 2.90v */
189 } CHIP_SYSCTL_BODRINTVAL_T;
190
196 STATIC INLINE void Chip_SYSCTL_Map(CHIP_SYSCTL_BOOT_MODE_REMAP_T remap)
197 {
198 LPC_SYSCTL->SYSMEMREMAP = (uint32_t) remap;
199 }
200
208 STATIC INLINE void Chip_SYSCTL_AssertPeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
209 {
210 LPC_SYSCTL->PRESETCTRL &= ~(1 << (uint32_t) periph);
211 }
212
218 STATIC INLINE void Chip_SYSCTL_DeassertPeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
219 {
220 LPC_SYSCTL->PRESETCTRL |= (1 << (uint32_t) periph);
221 }
222
228 STATIC INLINE void Chip_SYSCTL_PeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
229 {
230 Chip_SYSCTL_AssertPeriphReset(periph);
231 Chip_SYSCTL_DeassertPeriphReset(periph);
232 }
233
239 STATIC INLINE uint32_t Chip_SYSCTL_GetSystemRSTStatus(void)
240 {
241 return LPC_SYSCTL->SYSRSTSTAT;
242 }
243
250 STATIC INLINE void Chip_SYSCTL_ClearSystemRSTStatus(uint32_t reset)
251 {
252 LPC_SYSCTL->SYSRSTSTAT = reset;
253 }
254
260 STATIC INLINE uint32_t Chip_SYSCTL_GetPORPIOStatus(void)
261 {
262 return LPC_SYSCTL->PIOPORCAP0;
263 }
264
273 STATIC INLINE void Chip_SYSCTL_SetBODLevels(CHIP_SYSCTL_BODRSTLVL_T rstlvl,
274 CHIP_SYSCTL_BODRINTVAL_T intlvl)
275 {
276 LPC_SYSCTL->BODCTRL = ((uint32_t) rstlvl) | (((uint32_t) intlvl) << 2);
277 }
278
283 STATIC INLINE void Chip_SYSCTL_EnableBODReset(void)
284 {
285 LPC_SYSCTL->BODCTRL |= (1 << 4);
286 }
287
292 STATIC INLINE void Chip_SYSCTL_DisableBODReset(void)
293 {
294 LPC_SYSCTL->BODCTRL &= ~(1 << 4);
295 }
296
302 STATIC INLINE void Chip_SYSCTL_SetSYSTCKCAL(uint32_t sysCalVal)
303 {
304 LPC_SYSCTL->SYSTCKCAL = sysCalVal;
305 }
306
314 STATIC INLINE void Chip_SYSCTL_SetIRQLatency(uint32_t latency)
315 {
316 LPC_SYSCTL->IRQLATENCY = latency;
317 }
318
323 STATIC INLINE uint32_t Chip_SYSCTL_GetIRQLatency(void)
324 {
325 return LPC_SYSCTL->IRQLATENCY;
326 }
327
335 STATIC INLINE void Chip_SYSCTL_SetNMISource(uint32_t intsrc)
336 {
337 LPC_SYSCTL->NMISRC = intsrc;
338 }
339
344 STATIC INLINE void Chip_SYSCTL_EnableNMISource(void)
345 {
346 LPC_SYSCTL->NMISRC |= SYSCTL_NMISRC_ENABLE;
347 }
348
353 STATIC INLINE void Chip_SYSCTL_DisableNMISource(void)
354 {
355 LPC_SYSCTL->NMISRC &= ~(SYSCTL_NMISRC_ENABLE);
356 }
357
367 STATIC INLINE void Chip_SYSCTL_SetPinInterrupt(uint32_t intno, uint32_t pin)
368 {
369 LPC_SYSCTL->PINTSEL[intno] = (uint32_t) pin;
370 }
371
379 STATIC INLINE void Chip_SYSCTL_EnablePINTWakeuup(uint32_t pin)
380 {
381 LPC_SYSCTL->STARTERP0 |= (1 << pin);
382 }
383
390 STATIC INLINE void Chip_SYSCTL_DisablePINTWakeup(uint32_t pin)
391 {
392 LPC_SYSCTL->STARTERP0 &= ~(1 << pin);
393 }
394
400 STATIC INLINE void Chip_SYSCTL_EnablePeriphWakeup(uint32_t periphmask)
401 {
402 LPC_SYSCTL->STARTERP1 |= periphmask;
403 }
404
410 STATIC INLINE void Chip_SYSCTL_DisablePeriphWakeup(uint32_t periphmask)
411 {
412 LPC_SYSCTL->STARTERP1 &= ~periphmask;
413 }
414
420 STATIC INLINE uint32_t Chip_SYSCTL_GetDeepSleepPD(void)
421 {
422 return LPC_SYSCTL->PDSLEEPCFG;
423 }
424
430 STATIC INLINE uint32_t Chip_SYSCTL_GetWakeup(void)
431 {
432 return LPC_SYSCTL->PDAWAKECFG;
433 }
434
440 STATIC INLINE uint32_t Chip_SYSCTL_GetPowerStates(void)
441 {
442 return LPC_SYSCTL->PDRUNCFG;
443 }
444
449 STATIC INLINE uint32_t Chip_SYSCTL_GetDeviceID(void)
450 {
451 return LPC_SYSCTL->DEVICEID;
452 }
453
459 STATIC INLINE void Chip_SYSCTL_SetUSARTFRGDivider(uint8_t div)
460 {
461 LPC_SYSCTL->UARTFRGDIV = (uint32_t) div;
462 }
463
468 STATIC INLINE uint32_t Chip_SYSCTL_GetUSARTFRGDivider(void)
469 {
470 return LPC_SYSCTL->UARTFRGDIV;
471 }
472
478 STATIC INLINE void Chip_SYSCTL_SetUSARTFRGMultiplier(uint8_t mult)
479 {
480 LPC_SYSCTL->UARTFRGMULT = (uint32_t) mult;
481 }
482
487 STATIC INLINE uint32_t Chip_SYSCTL_GetUSARTFRGMultiplier(void)
488 {
489 return LPC_SYSCTL->UARTFRGMULT;
490 }
491
502 void Chip_SYSCTL_SetDeepSleepPD(uint32_t sleepmask);
503
514 void Chip_SYSCTL_SetWakeup(uint32_t wakeupmask);
515
521 void Chip_SYSCTL_PowerDown(uint32_t powerdownmask);
522
528 void Chip_SYSCTL_PowerUp(uint32_t powerupmask);
529
534 #ifdef __cplusplus
535 }
536 #endif
537
538 #endif /* __SYSCTL_8XX_H_ */