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CHIP: LPC17xx/40xx Clock Driver
LPC17xx/40xx chip specific drivers

## Detailed Description

## Modules
| CHIP: LPC17xx/40xx Clock Driver driver options

## Macros
#define | SYSCTL_OSCRANGE_15_25 (1 << 4)
#define | SYSCTL_OSCEC (1 << 5)
#define | SYSCTL_OSCSTAT (1 << 6)
#define | SYSCTL_IRC_FREQ (12000000)
#define | SYSCTL_PLL_ENABLE (1 << 0)
#define | SYSCTL_PLLSTS_ENABLED (1 << 8)
#define | SYSCTL_PLLSTS_LOCKED (1 << 10)

## Enumerations
enum | CHIP_SYSCTL_CLOCK_T { SYSCTL_CLOCK_SYS = 0, SYSCTL_CLOCK_ROM, SYSCTL_CLOCK_RAM, SYSCTL_CLOCK_FLASHREG, SYSCTL_CLOCK_FLASHARRAY, SYSCTL_CLOCK_I2C, SYSCTL_CLOCK_GPIO, SYSCTL_CLOCK_CT16B0, SYSCTL_CLOCK_CT16B1, SYSCTL_CLOCK_CT32B0, SYSCTL_CLOCK_CT32B1, SYSCTL_CLOCK_SSP0, SYSCTL_CLOCK_UART0, SYSCTL_CLOCK_ADC, SYSCTL_CLOCK_RESERVED14, SYSCTL_CLOCK_WDT, SYSCTL_CLOCK_IOCON, SYSCTL_CLOCK_RESERVED17, SYSCTL_CLOCK_SSP1, SYSCTL_CLOCK_PINT, SYSCTL_CLOCK_RESERVED20, SYSCTL_CLOCK_RESERVED21, SYSCTL_CLOCK_RESERVED22, SYSCTL_CLOCK_P0INT, SYSCTL_CLOCK_GROUP0INT = SYSCTL_CLOCK_P0INT, SYSCTL_CLOCK_P1INT, SYSCTL_CLOCK_GROUP1INT = SYSCTL_CLOCK_P1INT, SYSCTL_CLOCK_RESERVED25, SYSCTL_CLOCK_RESERVED26, SYSCTL_CLOCK_RESERVED27, SYSCTL_CLOCK_SYS = 0, SYSCTL_CLOCK_ROM, SYSCTL_CLOCK_RAM, SYSCTL_CLOCK_FLASHREG, SYSCTL_CLOCK_FLASHARRAY, SYSCTL_CLOCK_I2C, SYSCTL_CLOCK_GPIO, SYSCTL_CLOCK_CT16B0, SYSCTL_CLOCK_CT16B1, SYSCTL_CLOCK_CT32B0, SYSCTL_CLOCK_CT32B1, SYSCTL_CLOCK_SSP0, SYSCTL_CLOCK_UART0, SYSCTL_CLOCK_ADC, SYSCTL_CLOCK_USB, SYSCTL_CLOCK_WDT, SYSCTL_CLOCK_IOCON, SYSCTL_CLOCK_RESERVED17, SYSCTL_CLOCK_SSP1, SYSCTL_CLOCK_LCD, SYSCTL_CLOCK_TIMER0, SYSCTL_CLOCK_TIMER1, SYSCTL_CLOCK_UART0, SYSCTL_CLOCK_UART1, SYSCTL_CLOCK_PWM0, SYSCTL_CLOCK_PWM1, SYSCTL_CLOCK_I2C0, SYSCTL_CLOCK_UART4, SYSCTL_CLOCK_RTC, SYSCTL_CLOCK_SSP1, SYSCTL_CLOCK_EMC, SYSCTL_CLOCK_ADC, SYSCTL_CLOCK_CAN1, SYSCTL_CLOCK_CAN2, SYSCTL_CLOCK_GPIO, SYSCTL_CLOCK_SPIFI, SYSCTL_CLOCK_MCPWM, SYSCTL_CLOCK_QEI, SYSCTL_CLOCK_I2C1, SYSCTL_CLOCK_SSP2, SYSCTL_CLOCK_SSP0, SYSCTL_CLOCK_TIMER2, SYSCTL_CLOCK_TIMER3, SYSCTL_CLOCK_UART2, SYSCTL_CLOCK_UART3, SYSCTL_CLOCK_I2C2, SYSCTL_CLOCK_I2S, SYSCTL_CLOCK_SDC, SYSCTL_CLOCK_GPDMA, SYSCTL_CLOCK_ENET, SYSCTL_CLOCK_USB, SYSCTL_CLOCK_RSVD32, SYSCTL_CLOCK_RSVD33, SYSCTL_CLOCK_RSVD34, SYSCTL_CLOCK_RSVD35, SYSCTL_CLOCK_SYS = 0, SYSCTL_CLOCK_ROM, SYSCTL_CLOCK_RAM, SYSCTL_CLOCK_FLASHREG, SYSCTL_CLOCK_FLASH, SYSCTL_CLOCK_I2C, SYSCTL_CLOCK_GPIO, SYSCTL_CLOCK_SWM, SYSCTL_CLOCK_SCT, SYSCTL_CLOCK_WKT, SYSCTL_CLOCK_MRT, SYSCTL_CLOCK_SPI0, SYSCTL_CLOCK_SPI1, SYSCTL_CLOCK_CRC, SYSCTL_CLOCK_UART0, SYSCTL_CLOCK_UART1, SYSCTL_CLOCK_UART2, SYSCTL_CLOCK_WWDT, SYSCTL_CLOCK_IOCON, SYSCTL_CLOCK_ACOMP }
enum | CHIP_SYSCTL_EMC_DIV_T { SYSCTL_EMC_DIV1 = 0, SYSCTL_EMC_DIV2 = 1 }
enum | CHIP_SYSCTL_CCLKSRC_T { SYSCTL_CCLKSRC_SYSCLK, SYSCTL_CCLKSRC_MAINPLL }
enum | CHIP_SYSCTL_USBCLKSRC_T { SYSCTL_USBCLKSRC_PLLOUT = 0, SYSCTL_USBCLKSRC_MAINSYSCLK, SYSCTL_USBCLKSRC_SYSCLK, SYSCTL_USBCLKSRC_MAINPLL, SYSCTL_USBCLKSRC_USBPLL, SYSCTL_USBCLKSRC_RESERVED }
enum | CHIP_SYSCTL_PLLCLKSRC_T { SYSCTL_PLLCLKSRC_IRC = 0, SYSCTL_PLLCLKSRC_MAINOSC, SYSCTL_PLLCLKSRC_RESERVED1, SYSCTL_PLLCLKSRC_RESERVED2, SYSCTL_PLLCLKSRC_IRC = 0, SYSCTL_PLLCLKSRC_SYSOSC, SYSCTL_PLLCLKSRC_RESERVED1, SYSCTL_PLLCLKSRC_RESERVED2, SYSCTL_PLLCLKSRC_IRC, SYSCTL_PLLCLKSRC_MAINOSC, SYSCTL_PLLCLKSRC_RESERVED1, SYSCTL_PLLCLKSRC_RESERVED2, SYSCTL_PLLCLKSRC_IRC = 0, SYSCTL_PLLCLKSRC_SYSOSC, SYSCTL_PLLCLKSRC_RESERVED, SYSCTL_PLLCLKSRC_EXT_CLKIN }
enum | CHIP_SYSCTL_SPIFICLKSRC_T { SYSCTL_SPIFICLKSRC_SYSCLK, SYSCTL_SPIFICLKSRC_MAINPLL, SYSCTL_SPIFICLKSRC_USBPLL, SYSCTL_SPIFICLKSRC_RESERVED }
enum | CHIP_SYSCTL_CLKOUTSRC_T { SYSCTL_CLKOUTSRC_IRC = 0, SYSCTL_CLKOUTSRC_MAINOSC, SYSCTL_CLKOUTSRC_WDTOSC, SYSCTL_CLKOUTSRC_LFOSC = SYSCTL_CLKOUTSRC_WDTOSC, SYSCTL_CLKOUTSRC_MAINSYSCLK, SYSCTL_CLKOUTSRC_IRC = 0, SYSCTL_CLKOUTSRC_SYSOSC, SYSCTL_CLKOUTSRC_WDTOSC, SYSCTL_CLKOUTSRC_MAINSYSCLK, SYSCTL_CLKOUTSRC_CPU, SYSCTL_CLKOUTSRC_MAINOSC, SYSCTL_CLKOUTSRC_IRC, SYSCTL_CLKOUTSRC_USB, SYSCTL_CLKOUTSRC_RTC, SYSCTL_CLKOUTSRC_SPIFI, SYSCTL_CLKOUTSRC_WATCHDOGOSC, SYSCTL_CLKOUTSRC_RESERVED3, SYSCTL_CLKOUTSRC_IRC = 0, SYSCTL_CLKOUTSRC_SYSOSC, SYSCTL_CLKOUTSRC_WDTOSC, SYSCTL_CLKOUTSRC_MAINSYSCLK }

## Functions
void | Chip_Clock_EnablePLL (CHIP_SYSCTL_PLL_T pllNum, uint32_t flags)
| Enables or connects a PLL.
void | Chip_Clock_DisablePLL (CHIP_SYSCTL_PLL_T pllNum, uint32_t flags)
| Disables or disconnects a PLL.
void | Chip_Clock_SetupPLL (CHIP_SYSCTL_PLL_T pllNum, uint32_t msel, uint32_t psel)
| Sets up a PLL.
STATIC INLINE uint32_t | Chip_Clock_GetPLLStatus (CHIP_SYSCTL_PLL_T pllNum)
| Returns PLL status.
STATIC INLINE bool | Chip_Clock_IsMainPLLEnabled (void)
| Read PLL0 enable status.
STATIC INLINE bool | Chip_Clock_IsUSBPLLEnabled (void)
| Read PLL1 enable status.
STATIC INLINE bool | Chip_Clock_IsMainPLLLocked (void)
| Read PLL0 lock status.
STATIC INLINE bool | Chip_Clock_IsUSBPLLLocked (void)
| Read PLL1 lock status.
STATIC INLINE void | Chip_Clock_FeedPLL (CHIP_SYSCTL_PLL_T pllNum)
| Feeds a PLL.
void | Chip_Clock_EnablePeriphClock (CHIP_SYSCTL_CLOCK_T clk)
| Enables power and clocking for a peripheral.
void | Chip_Clock_DisablePeriphClock (CHIP_SYSCTL_CLOCK_T clk)
| Disables power and clocking for a peripheral.
bool | Chip_Clock_IsPeripheralClockEnabled (CHIP_SYSCTL_CLOCK_T clk)
| Returns power enables state for a peripheral.
STATIC INLINE void | Chip_Clock_SetEMCClockDiv (CHIP_SYSCTL_EMC_DIV_T emcDiv)
| Selects a EMC divider rate.
STATIC INLINE uint32_t | Chip_Clock_GetEMCClockDiv (void)
| Get EMC divider rate.
void | Chip_Clock_SetCPUClockSource (CHIP_SYSCTL_CCLKSRC_T src)
| Sets the current CPU clock source.
CHIP_SYSCTL_CCLKSRC_T | Chip_Clock_GetCPUClockSource (void)
| Returns the current CPU clock source.
void | Chip_Clock_SetCPUClockDiv (uint32_t div)
| Sets the CPU clock divider.
uint32_t | Chip_Clock_GetCPUClockDiv (void)
| Gets the CPU clock divider.
void | Chip_Clock_SetUSBClockSource (CHIP_SYSCTL_USBCLKSRC_T src)
| Sets the USB clock divider source.
STATIC INLINE CHIP_SYSCTL_USBCLKSRC_T | Chip_Clock_GetUSBClockSource (void)
| Gets the USB clock divider source.
void | Chip_Clock_SetUSBClockDiv (uint32_t div)
| Sets the USB clock divider.
uint32_t | Chip_Clock_GetUSBClockDiv (void)
| Gets the USB clock divider.
STATIC INLINE void | Chip_Clock_SetMainPllSource (CHIP_SYSCTL_PLLCLKSRC_T src)
| Selects a input clock source for SYSCLK.
STATIC INLINE CHIP_SYSCTL_PLLCLKSRC_T | Chip_Clock_GetMainPllSource (void)
| Returns the input clock source for SYSCLK.
STATIC INLINE void | Chip_Clock_SetPCLKDiv (uint32_t div)
| Sets a clock divider for all peripherals.
STATIC INLINE uint32_t | Chip_Clock_GetPCLKDiv (void)
| Gets the clock divider for all peripherals.
void | Chip_Clock_SetSPIFIClockSource (CHIP_SYSCTL_SPIFICLKSRC_T src)
| Sets the SPIFI clock divider source.
STATIC INLINE CHIP_SYSCTL_SPIFICLKSRC_T | Chip_Clock_GetSPIFIClockSource (void)
| Gets the SPIFI clock divider source.
void | Chip_Clock_SetSPIFIClockDiv (uint32_t div)
| Sets the SPIFI clock divider.
STATIC INLINE uint32_t | Chip_Clock_GetSPIFIClockDiv (void)
| Gets the SPIFI clock divider.
STATIC INLINE void | Chip_Clock_SetLCDClockDiv (uint32_t div)
| Set the LCD clock prescaler.
STATIC INLINE uint32_t | Chip_Clock_GetLCDClockDiv (void)
| Get the LCD clock prescaler.
void | Chip_Clock_SetCLKOUTSource (CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div)
| Selects a source clock and divider rate for the CLKOUT pin.
STATIC INLINE void | Chip_Clock_EnableCLKOUT (void)
| Enables the clock on the CLKOUT pin.
STATIC INLINE void | Chip_Clock_DisableCLKOUT (void)
| Disables the clock on the CLKOUT pin.
STATIC INLINE bool | Chip_Clock_IsCLKOUTEnabled (void)
| Returns the CLKOUT activity indication status.
STATIC INLINE uint32_t | Chip_Clock_GetMainOscRate (void)
| Returns the main oscillator clock rate.
STATIC INLINE uint32_t | Chip_Clock_GetIntOscRate (void)
| Returns the internal oscillator (IRC) clock rate.
STATIC INLINE uint32_t | Chip_Clock_GetRTCOscRate (void)
| Returns the RTC oscillator clock rate.
uint32_t | Chip_Clock_GetSYSCLKRate (void)
| Returns the current SYSCLK clock rate.
STATIC INLINE uint32_t | Chip_Clock_GetMainPllInClockRate (void)
| Return Main PLL (PLL0) input clock rate.
uint32_t | Chip_Clock_GetMainPllOutClockRate (void)
| Return PLL0 (Main PLL) output clock rate.
STATIC INLINE uint32_t | Chip_Clock_GetUSBPllInClockRate (void)
| Return USB PLL input clock rate.
uint32_t | Chip_Clock_GetUSBPllOutClockRate (void)
| Return USB PLL output clock rate.
uint32_t | Chip_Clock_GetMainClockRate (void)
| Return main clock rate.
uint32_t | Chip_Clock_GetSystemClockRate (void)
| Return system clock rate.
uint32_t | Chip_Clock_GetUSBClockRate (void)
| Gets the USB clock (USB_CLK) rate.
uint32_t | Chip_Clock_GetSPIFIClockRate (void)
| Returns the SPIFI clock rate.
STATIC INLINE uint32_t | Chip_Clock_GetEMCClockRate (void)
| Returns clock rate for EMC.
uint32_t | Chip_Clock_GetPeripheralClockRate (CHIP_SYSCTL_PCLK_T clk)
| Returns clock rate for a peripheral (from peripheral clock)
STATIC INLINE uint32_t | Chip_Clock_GetRTCClockRate (void)
| Returns clock rate for RTC.
STATIC INLINE uint32_t | Chip_Clock_GetENETClockRate (void)
| Returns clock rate for Ethernet.
STATIC INLINE uint32_t | Chip_Clock_GetGPDMAClockRate (void)
| Returns clock rate for GPDMA.

## Macro Definition Documentation

#define SYSCTL_IRC_FREQ (12000000)

Definition at line 70 of file clock_17xx_40xx.h.

#define SYSCTL_OSCEC (1 << 5)

SCS register - main oscillator enable

Definition at line 63 of file clock_17xx_40xx.h.

#define SYSCTL_OSCRANGE_15_25 (1 << 4)

SCS register - main oscillator range 15 to 25MHz

Definition at line 62 of file clock_17xx_40xx.h.

#define SYSCTL_OSCSTAT (1 << 6)

SCS register - main oscillator is ready status Internal oscillator frequency

Definition at line 64 of file clock_17xx_40xx.h.

#define SYSCTL_PLL_ENABLE (1 << 0)

PLL enable flag

Definition at line 73 of file clock_17xx_40xx.h.

#define SYSCTL_PLLSTS_ENABLED (1 << 8)

PLL enable flag

Definition at line 119 of file clock_17xx_40xx.h.

#define SYSCTL_PLLSTS_LOCKED (1 << 10)

PLL connect flag

Definition at line 120 of file clock_17xx_40xx.h.

## Enumeration Type Documentation

enum CHIP_SYSCTL_CCLKSRC_T

Selectable CPU clock sources

Enumerator:

  SYSCTL_CCLKSRC_SYSCLK | Select Sysclk as the input to the CPU clock divider.
  SYSCTL_CCLKSRC_MAINPLL | Select the output of the Main PLL as the input to the CPU clock divider.

Definition at line 359 of file clock_17xx_40xx.h.

enum CHIP_SYSCTL_CLKOUTSRC_T

Clock sources for the CLKOUT pin

Enumerator:

  SYSCTL_CLKOUTSRC_IRC | Internal oscillator for CLKOUT
  SYSCTL_CLKOUTSRC_MAINOSC | Main oscillator for CLKOUT
  SYSCTL_CLKOUTSRC_WDTOSC | Watchdog oscillator for CLKOUT
  SYSCTL_CLKOUTSRC_LFOSC | LF oscillator rate (LPC11A/Exx only) for CLKOUT
  SYSCTL_CLKOUTSRC_MAINSYSCLK | Main system clock for CLKOUT
  SYSCTL_CLKOUTSRC_IRC | Internal oscillator for CLKOUT
  SYSCTL_CLKOUTSRC_SYSOSC | Main oscillator for CLKOUT
  SYSCTL_CLKOUTSRC_WDTOSC | Watchdog oscillator for CLKOUT
  SYSCTL_CLKOUTSRC_MAINSYSCLK | Main system clock for CLKOUT
  SYSCTL_CLKOUTSRC_CPU | CPU clock as CLKOUT source
  SYSCTL_CLKOUTSRC_MAINOSC | Main oscillator clock as CLKOUT source
  SYSCTL_CLKOUTSRC_IRC | IRC oscillator clock as CLKOUT source
  SYSCTL_CLKOUTSRC_USB | USB clock as CLKOUT source
  SYSCTL_CLKOUTSRC_RTC | RTC clock as CLKOUT source
  SYSCTL_CLKOUTSRC_SPIFI | SPIFI clock as CLKOUT source
  SYSCTL_CLKOUTSRC_WATCHDOGOSC | Watchdog oscillator as CLKOUT source
  SYSCTL_CLKOUTSRC_RESERVED3 |
  SYSCTL_CLKOUTSRC_IRC | Internal oscillator for CLKOUT
  SYSCTL_CLKOUTSRC_SYSOSC | System oscillator for CLKOUT
  SYSCTL_CLKOUTSRC_WDTOSC | Watchdog oscillator for CLKOUT
  SYSCTL_CLKOUTSRC_MAINSYSCLK | Main system clock for CLKOUT

Definition at line 658 of file clock_17xx_40xx.h.

enum CHIP_SYSCTL_CLOCK_T

Power control for peripherals

Enumerator:

  SYSCTL_CLOCK_SYS | 0: System clock
  SYSCTL_CLOCK_ROM | 1: ROM clock
  SYSCTL_CLOCK_RAM | 2: RAM clock
  SYSCTL_CLOCK_FLASHREG | 3: FLASH register interface clock
  SYSCTL_CLOCK_FLASHARRAY | 4: FLASH array access clock
  SYSCTL_CLOCK_I2C | 5: I2C clock, not on LPC110x
  SYSCTL_CLOCK_GPIO | 6: GPIO clock
  SYSCTL_CLOCK_CT16B0 | 7: 16-bit Counter/timer 0 clock
  SYSCTL_CLOCK_CT16B1 | 8: 16-bit Counter/timer 1 clock
  SYSCTL_CLOCK_CT32B0 | 9: 32-bit Counter/timer 0 clock
  SYSCTL_CLOCK_CT32B1 | 10: 32-bit Counter/timer 1 clock
  SYSCTL_CLOCK_SSP0 | 11: SSP0 clock
  SYSCTL_CLOCK_UART0 | 12: UART0 clock
  SYSCTL_CLOCK_ADC | 13: ADC clock
  SYSCTL_CLOCK_RESERVED14 | 14: Reserved
  SYSCTL_CLOCK_WDT | 15: Watchdog timer clock
  SYSCTL_CLOCK_IOCON | 16: IOCON block clock
  SYSCTL_CLOCK_RESERVED17 | 17: Reserved
  SYSCTL_CLOCK_SSP1 | 18: SSP1 clock, LPC11A/C/E/Uxx only
  SYSCTL_CLOCK_PINT | 19: GPIO Pin int register interface clock, LPC11A/E/Uxx only
  SYSCTL_CLOCK_RESERVED20 | 20: Reserved
  SYSCTL_CLOCK_RESERVED21 | 21: Reserved
  SYSCTL_CLOCK_RESERVED22 | 22: Reserved
  SYSCTL_CLOCK_P0INT | 23: GPIO GROUP1 interrupt register clock, LPC11Axx only
  SYSCTL_CLOCK_GROUP0INT | 23: GPIO GROUP0 interrupt register interface clock, LPC11E/Uxx only
  SYSCTL_CLOCK_P1INT | 24: GPIO GROUP1 interrupt register clock, LPC11Axx only
  SYSCTL_CLOCK_GROUP1INT | 24: GPIO GROUP1 interrupt register interface clock, LPC11E/Uxx only
  SYSCTL_CLOCK_RESERVED25 | 25: Reserved
  SYSCTL_CLOCK_RESERVED26 | 26: Reserved
  SYSCTL_CLOCK_RESERVED27 | 27: Reserved
  SYSCTL_CLOCK_SYS | 0: System clock
  SYSCTL_CLOCK_ROM | 1: ROM clock
  SYSCTL_CLOCK_RAM | 2: RAM clock
  SYSCTL_CLOCK_FLASHREG | 3: FLASH register interface clock
  SYSCTL_CLOCK_FLASHARRAY | 4: FLASH array access clock
  SYSCTL_CLOCK_I2C | 5: I2C clock
  SYSCTL_CLOCK_GPIO | 6: GPIO clock
  SYSCTL_CLOCK_CT16B0 | 7: 16-bit Counter/timer 0 clock
  SYSCTL_CLOCK_CT16B1 | 8: 16-bit Counter/timer 1 clock
  SYSCTL_CLOCK_CT32B0 | 9: 32-bit Counter/timer 0 clock
  SYSCTL_CLOCK_CT32B1 | 10: 32-bit Counter/timer 1 clock
  SYSCTL_CLOCK_SSP0 | 11: SSP0 clock
  SYSCTL_CLOCK_UART0 | 12: UART0 clock
  SYSCTL_CLOCK_ADC | 13: ADC clock
  SYSCTL_CLOCK_USB | 14: USBREG clock
  SYSCTL_CLOCK_WDT | 15: Watchdog timer clock
  SYSCTL_CLOCK_IOCON | 16: IOCON block clock
  SYSCTL_CLOCK_RESERVED17 | 17: Reserved
  SYSCTL_CLOCK_SSP1 | 18: SSP1 clock
  SYSCTL_CLOCK_LCD | LCD clock
  SYSCTL_CLOCK_TIMER0 | Timer 0 clock
  SYSCTL_CLOCK_TIMER1 | Timer 1 clock
  SYSCTL_CLOCK_UART0 | UART 0 clock
  SYSCTL_CLOCK_UART1 | UART 1 clock
  SYSCTL_CLOCK_PWM0 | PWM0 clock
  SYSCTL_CLOCK_PWM1 | PWM1 clock
  SYSCTL_CLOCK_I2C0 | I2C0 clock
  SYSCTL_CLOCK_UART4 | UART 4 clock
  SYSCTL_CLOCK_RTC | RTC clock
  SYSCTL_CLOCK_SSP1 | SSP1 clock
  SYSCTL_CLOCK_EMC | EMC clock
  SYSCTL_CLOCK_ADC | ADC clock
  SYSCTL_CLOCK_CAN1 | CAN1 clock
  SYSCTL_CLOCK_CAN2 | CAN2 clock
  SYSCTL_CLOCK_GPIO | GPIO clock
  SYSCTL_CLOCK_SPIFI | SPIFI clock
  SYSCTL_CLOCK_MCPWM | MCPWM clock
  SYSCTL_CLOCK_QEI | QEI clock
  SYSCTL_CLOCK_I2C1 | I2C1 clock
  SYSCTL_CLOCK_SSP2 | SSP2 clock
  SYSCTL_CLOCK_SSP0 | SSP0 clock
  SYSCTL_CLOCK_TIMER2 | Timer 2 clock
  SYSCTL_CLOCK_TIMER3 | Timer 3 clock
  SYSCTL_CLOCK_UART2 | UART 2 clock
  SYSCTL_CLOCK_UART3 | UART 3 clock
  SYSCTL_CLOCK_I2C2 | I2C2 clock
  SYSCTL_CLOCK_I2S | I2S clock
  SYSCTL_CLOCK_SDC | SD Card interface clock
  SYSCTL_CLOCK_GPDMA | GP DMA clock
  SYSCTL_CLOCK_ENET | EMAC/Ethernet clock
  SYSCTL_CLOCK_USB | USB clock
  SYSCTL_CLOCK_RSVD32 |
  SYSCTL_CLOCK_RSVD33 |
  SYSCTL_CLOCK_RSVD34 |
  SYSCTL_CLOCK_RSVD35 |
  SYSCTL_CLOCK_SYS | System clock
  SYSCTL_CLOCK_ROM | ROM clock
  SYSCTL_CLOCK_RAM | RAM clock
  SYSCTL_CLOCK_FLASHREG | FLASH register interface clock
  SYSCTL_CLOCK_FLASH | FLASH array access clock
  SYSCTL_CLOCK_I2C | I2C clock
  SYSCTL_CLOCK_GPIO | GPIO clock
  SYSCTL_CLOCK_SWM | Switch matrix clock
  SYSCTL_CLOCK_SCT | State configurable timer clock
  SYSCTL_CLOCK_WKT | Self wake-up timer clock
  SYSCTL_CLOCK_MRT | Multi-rate timer clock
  SYSCTL_CLOCK_SPI0 | SPI0 clock
  SYSCTL_CLOCK_SPI1 | SPI01 clock
  SYSCTL_CLOCK_CRC | CRC clock
  SYSCTL_CLOCK_UART0 | UART0 clock
  SYSCTL_CLOCK_UART1 | UART1 clock
  SYSCTL_CLOCK_UART2 | UART2 clock
  SYSCTL_CLOCK_WWDT | Watchdog clock
  SYSCTL_CLOCK_IOCON | IOCON clock
  SYSCTL_CLOCK_ACOMP | Analog comparator clock

Definition at line 221 of file clock_17xx_40xx.h.

enum CHIP_SYSCTL_EMC_DIV_T

EMC clock divider values

Enumerator:

  SYSCTL_EMC_DIV1 |
  SYSCTL_EMC_DIV2 |

Definition at line 325 of file clock_17xx_40xx.h.

enum CHIP_SYSCTL_PLLCLKSRC_T

PLL source clocks

Enumerator:

  SYSCTL_PLLCLKSRC_IRC | Internal oscillator in
  SYSCTL_PLLCLKSRC_MAINOSC | Crystal (main) oscillator in
  SYSCTL_PLLCLKSRC_RESERVED1 | Reserved
  SYSCTL_PLLCLKSRC_RESERVED2 | Reserved
  SYSCTL_PLLCLKSRC_IRC | Internal oscillator in
  SYSCTL_PLLCLKSRC_SYSOSC | Crystal (main) oscillator in
  SYSCTL_PLLCLKSRC_RESERVED1 | Reserved
  SYSCTL_PLLCLKSRC_RESERVED2 | Reserved
  SYSCTL_PLLCLKSRC_IRC | PLL is sourced from the internal oscillator (IRC)
  SYSCTL_PLLCLKSRC_MAINOSC | PLL is sourced from the main oscillator
  SYSCTL_PLLCLKSRC_RESERVED1 |
  SYSCTL_PLLCLKSRC_RESERVED2 |
  SYSCTL_PLLCLKSRC_IRC | Internal oscillator
  SYSCTL_PLLCLKSRC_SYSOSC | Crystal (system) oscillator
  SYSCTL_PLLCLKSRC_RESERVED |
  SYSCTL_PLLCLKSRC_EXT_CLKIN | External clock input

Definition at line 453 of file clock_17xx_40xx.h.

enum CHIP_SYSCTL_SPIFICLKSRC_T

Clock sources for the SPIFI clock divider

Enumerator:

  SYSCTL_SPIFICLKSRC_SYSCLK | SYSCLK clock as SPIFI divider source
  SYSCTL_SPIFICLKSRC_MAINPLL | PLL0 clock as SPIFI divider source
  SYSCTL_SPIFICLKSRC_USBPLL | PLL1 clock as SPIFI divider source
  SYSCTL_SPIFICLKSRC_RESERVED |

Definition at line 593 of file clock_17xx_40xx.h.

enum CHIP_SYSCTL_USBCLKSRC_T

Clock sources for the USB divider. On 175x/6x devices, only the USB PLL1 can be used as an input for the USB divider

Enumerator:

  SYSCTL_USBCLKSRC_PLLOUT | USB PLL out
  SYSCTL_USBCLKSRC_MAINSYSCLK | Main system clock
  SYSCTL_USBCLKSRC_SYSCLK | SYSCLK clock as USB divider source
  SYSCTL_USBCLKSRC_MAINPLL | PLL0 clock as USB divider source
  SYSCTL_USBCLKSRC_USBPLL | PLL1 clock as USB divider source
  SYSCTL_USBCLKSRC_RESERVED |

Definition at line 407 of file clock_17xx_40xx.h.

## Function Documentation

STATIC INLINE void Chip_Clock_DisableCLKOUT | ( | void |  | ) |

Disables the clock on the CLKOUT pin.

Returns
  Nothing

Definition at line 698 of file clock_17xx_40xx.h.

void Chip_Clock_DisablePeriphClock | ( | CHIP_SYSCTL_CLOCK_T | clk | ) |

Disables power and clocking for a peripheral.

Parameters

  clk,: | Clock to disable

Returns
  Nothing

Note
  Only peripheral clocks that are defined in the PCONP registers of the clock and power controller can be enabled and disabled with this function. Some clocks need to be disabled elsewhere (ie, USB) and will return false to indicate it can't be disabled with this function.

Disables power and clocking for a peripheral.

Parameters

  clk | : Clock to disable

Returns
  Nothing

Definition at line 322 of file clock_11xx.h.

void Chip_Clock_DisablePLL | ( | CHIP_SYSCTL_PLL_T | pllNum,
|  | uint32_t | flags
| ) |  |

Disables or disconnects a PLL.

Parameters

  pllNum,: | PLL number
  flags,: | SYSCTL_PLL_ENABLE or SYSCTL_PLL_CONNECT

Returns
  Nothing

Note
  This will also perform a PLL feed sequence. Connect only applies to the LPC175x/6x devices.

Definition at line 61 of file clock_17xx_40xx.c.

STATIC INLINE void Chip_Clock_EnableCLKOUT | ( | void |  | ) |

Enables the clock on the CLKOUT pin.

Returns
  Nothing

Definition at line 689 of file clock_17xx_40xx.h.

void Chip_Clock_EnablePeriphClock | ( | CHIP_SYSCTL_CLOCK_T | clk | ) |

Enables power and clocking for a peripheral.

Parameters

  clk,: | Clock to enable

Returns
  Nothing

Note
  Only peripheral clocks that are defined in the PCONP registers of the clock and power controller can be enabled and disabled with this function. Some clocks need to be enabled elsewhere (ie, USB) and will return false to indicate it can't be enabled with this function.

Enables power and clocking for a peripheral.

Parameters

  clk | : Clock to enable

Returns
  Nothing

Definition at line 312 of file clock_11xx.h.

void Chip_Clock_EnablePLL | ( | CHIP_SYSCTL_PLL_T | pllNum,
|  | uint32_t | flags
| ) |  |

Enables or connects a PLL.

Parameters

  pllNum,: | PLL number
  flags,: | SYSCTL_PLL_ENABLE or SYSCTL_PLL_CONNECT

Returns
  Nothing

Note
  This will also perform a PLL feed sequence. Connect only applies to the LPC175x/6x devices.

Definition at line 51 of file clock_17xx_40xx.c.

STATIC INLINE void Chip_Clock_FeedPLL | ( | CHIP_SYSCTL_PLL_T | pllNum | ) |

Feeds a PLL.

Parameters

  pllNum,: | PLL number

Returns
  Nothing

Definition at line 212 of file clock_17xx_40xx.h.

uint32_t Chip_Clock_GetCPUClockDiv | ( | void |  | ) |

Gets the CPU clock divider.

Returns
  CPU clock divider, between 1 and divider max

Note
  The maximum divider for the 175x/6x is 256. The maximum divider for the 177x/8x and 407x/8x is 32. Note on 175x/6x devices, the divided CPU clock rate is used as the input to the peripheral clock dividers, while 177x/8x and 407x/8x devices use the undivided CPU clock rate.

Definition at line 206 of file clock_17xx_40xx.c.

CHIP_SYSCTL_CCLKSRC_T Chip_Clock_GetCPUClockSource | ( | void |  | ) |

Returns the current CPU clock source.

Returns
  CPU clock source

Note
  On 177x/8x and 407x/8x devices, this is also the peripheral clock source.

Definition at line 167 of file clock_17xx_40xx.c.

STATIC INLINE uint32_t Chip_Clock_GetEMCClockDiv | ( | void |  | ) |

Get EMC divider rate.

Returns
  divider value

Definition at line 349 of file clock_17xx_40xx.h.

STATIC INLINE uint32_t Chip_Clock_GetEMCClockRate | ( | void |  | ) |

Returns clock rate for EMC.

Returns
  Clock rate for the peripheral

Definition at line 811 of file clock_17xx_40xx.h.

STATIC INLINE uint32_t Chip_Clock_GetENETClockRate | ( | void |  | ) |

Returns clock rate for Ethernet.

Returns
  Clock rate for the peripheral

Definition at line 857 of file clock_17xx_40xx.h.

STATIC INLINE uint32_t Chip_Clock_GetGPDMAClockRate | ( | void |  | ) |

Returns clock rate for GPDMA.

Returns
  Clock rate for the peripheral

Definition at line 866 of file clock_17xx_40xx.h.

STATIC INLINE uint32_t Chip_Clock_GetIntOscRate | ( | void |  | ) |

Returns the internal oscillator (IRC) clock rate.

Returns
  internal oscillator (IRC) clock rate

Definition at line 728 of file clock_17xx_40xx.h.

STATIC INLINE uint32_t Chip_Clock_GetLCDClockDiv | ( | void |  | ) |

Get the LCD clock prescaler.

Returns
  Current divider value

Definition at line 648 of file clock_17xx_40xx.h.

uint32_t Chip_Clock_GetMainClockRate | ( | void |  | ) |

Return main clock rate.

Returns
  main clock rate

Definition at line 248 of file clock_11xx.c.

STATIC INLINE uint32_t Chip_Clock_GetMainOscRate | ( | void |  | ) |

Returns the main oscillator clock rate.

Returns
  main oscillator clock rate

Definition at line 719 of file clock_17xx_40xx.h.

STATIC INLINE uint32_t Chip_Clock_GetMainPllInClockRate | ( | void |  | ) |

Return Main PLL (PLL0) input clock rate.

Returns
  PLL0 input clock rate

Definition at line 754 of file clock_17xx_40xx.h.

uint32_t Chip_Clock_GetMainPllOutClockRate | ( | void |  | ) |

Return PLL0 (Main PLL) output clock rate.

Returns
  PLL0 output clock rate

Definition at line 335 of file clock_17xx_40xx.c.

STATIC INLINE CHIP_SYSCTL_PLLCLKSRC_T Chip_Clock_GetMainPllSource | ( | void |  | ) |

Returns the input clock source for SYSCLK.

Returns
  input clock source for SYSCLK

Definition at line 480 of file clock_17xx_40xx.h.

STATIC INLINE uint32_t Chip_Clock_GetPCLKDiv | ( | void |  | ) |

Gets the clock divider for all peripherals.

Returns
  Divider for all peripherals, 0 = disabled

Note
  All the peripherals in the device use the same clock divider. The divider is based on the CPU's clock rate. (LPC177X/8X and 407X/8X)

Definition at line 582 of file clock_17xx_40xx.h.

uint32_t Chip_Clock_GetPeripheralClockRate | ( | CHIP_SYSCTL_PCLK_T | clk | ) |

Returns clock rate for a peripheral (from peripheral clock)

Parameters

  clk,: | Clock to get rate of

Returns
  Clock rate for the peripheral

Note
  This covers most common peripheral clocks, but not every clock in the system. LPC177x/8x and LPC407x/8x devices use the same clock for all periphreals, while the LPC175x/6x have unique dividers (except to RTC ) that may alter the peripheral clock rate.

STATIC INLINE uint32_t Chip_Clock_GetPLLStatus | ( | CHIP_SYSCTL_PLL_T | pllNum | ) |

Returns PLL status.

Parameters

  pllNum,: | PLL number

Returns
  Current enabled flags, Or'ed SYSCTL_PLLSTS_* states

Note
  Note flag positions for PLL0 and PLL1 differ on the LPC175x/6x devices.

Definition at line 129 of file clock_17xx_40xx.h.

STATIC INLINE uint32_t Chip_Clock_GetRTCClockRate | ( | void |  | ) |

Returns clock rate for RTC.

Returns
  Clock rate for the peripheral

Definition at line 846 of file clock_17xx_40xx.h.

STATIC INLINE uint32_t Chip_Clock_GetRTCOscRate | ( | void |  | ) |

Returns the RTC oscillator clock rate.

Returns
  RTC oscillator clock rate

Definition at line 737 of file clock_17xx_40xx.h.

STATIC INLINE uint32_t Chip_Clock_GetSPIFIClockDiv | ( | void |  | ) |

Gets the SPIFI clock divider.

Returns
  SPIFI clock divider

Note
  Divider values are between 1 and 31, 0 is disabled

Definition at line 629 of file clock_17xx_40xx.h.

uint32_t Chip_Clock_GetSPIFIClockRate | ( | void |  | ) |

Returns the SPIFI clock rate.

Returns
  SPIFI clock clock rate

Definition at line 467 of file clock_17xx_40xx.c.

STATIC INLINE CHIP_SYSCTL_SPIFICLKSRC_T Chip_Clock_GetSPIFIClockSource | ( | void |  | ) |

Gets the SPIFI clock divider source.

Returns
  SPIFI clock divider source clock

Definition at line 611 of file clock_17xx_40xx.h.

uint32_t Chip_Clock_GetSYSCLKRate | ( | void |  | ) |

Returns the current SYSCLK clock rate.

Returns
  SYSCLK clock rate

Note
  SYSCLK is used for sourcing PLL0, SPIFI FLASH, the USB clock divider, and the CPU clock divider.

Definition at line 316 of file clock_17xx_40xx.c.

uint32_t Chip_Clock_GetSystemClockRate | ( | void |  | ) |

Return system clock rate.

Returns
  system clock rate

Definition at line 281 of file clock_11xx.c.

uint32_t Chip_Clock_GetUSBClockDiv | ( | void |  | ) |

Gets the USB clock divider.

Returns
  USB clock divider

Note
  Divider values are between 1 and 32 (16 max for 175x/6x)

Definition at line 243 of file clock_17xx_40xx.c.

uint32_t Chip_Clock_GetUSBClockRate | ( | void |  | ) |

Gets the USB clock (USB_CLK) rate.

Returns
  USB clock (USB_CLK) clock rate

Note
  The clock source and divider are used to generate the USB clock rate.

Definition at line 407 of file clock_17xx_40xx.c.

STATIC INLINE CHIP_SYSCTL_USBCLKSRC_T Chip_Clock_GetUSBClockSource | ( | void |  | ) |

Gets the USB clock divider source.

Returns
  USB clock divider source clock

Definition at line 428 of file clock_17xx_40xx.h.

STATIC INLINE uint32_t Chip_Clock_GetUSBPllInClockRate | ( | void |  | ) |

Return USB PLL input clock rate.

Returns
  USB PLL input clock rate

Definition at line 769 of file clock_17xx_40xx.h.

uint32_t Chip_Clock_GetUSBPllOutClockRate | ( | void |  | ) |

Return USB PLL output clock rate.

Returns
  USB PLL output clock rate

Definition at line 224 of file clock_13xx.c.

STATIC INLINE bool Chip_Clock_IsCLKOUTEnabled | ( | void |  | ) |

Returns the CLKOUT activity indication status.

Returns
  true if CLKOUT is enabled, false if disabled and stopped

Note
  CLKOUT activity indication. Reads as true when CLKOUT is enabled. Read as false when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped.

Definition at line 710 of file clock_17xx_40xx.h.

STATIC INLINE bool Chip_Clock_IsMainPLLEnabled | ( | void |  | ) |

Read PLL0 enable status.

Returns
  true of the PLL0 is enabled. false if not enabled

Definition at line 138 of file clock_17xx_40xx.h.

STATIC INLINE bool Chip_Clock_IsMainPLLLocked | ( | void |  | ) |

Read PLL0 lock status.

Returns
  true of the PLL0 is locked. false if not locked

Definition at line 164 of file clock_17xx_40xx.h.

bool Chip_Clock_IsPeripheralClockEnabled | ( | CHIP_SYSCTL_CLOCK_T | clk | ) |

Returns power enables state for a peripheral.

Parameters

  clk,: | Clock to check

Returns
  true if the clock is enabled, false if disabled

Definition at line 124 of file clock_17xx_40xx.c.

STATIC INLINE bool Chip_Clock_IsUSBPLLEnabled | ( | void |  | ) |

Read PLL1 enable status.

Returns
  true of the PLL1 is enabled. false if not enabled

Definition at line 151 of file clock_17xx_40xx.h.

STATIC INLINE bool Chip_Clock_IsUSBPLLLocked | ( | void |  | ) |

Read PLL1 lock status.

Returns
  true of the PLL1 is locked. false if not locked

Definition at line 177 of file clock_17xx_40xx.h.

void Chip_Clock_SetCLKOUTSource | ( | CHIP_SYSCTL_CLKOUTSRC_T | src,
|  | uint32_t | div
| ) |  |

Selects a source clock and divider rate for the CLKOUT pin.

Parameters

  src,: | source selected
  div,: | Divider for the clock source on CLKOUT, 1 to 16

Returns
  Nothing

Note
  This function will disable the CLKOUT signal if its enabled. Use Chip_Clock_CLKOUTEnable to re-enable CLKOUT after a call to this function.

Selects a source clock and divider rate for the CLKOUT pin.

Parameters

  src | : Clock source for CLKOUT
  div | : divider for CLKOUT clock

Returns
  Nothing

Note
  Use 0 to disable, or a divider value of 1 to 255. The CLKOUT clock rate is the clock source divided by the divider. This function will also toggle the clock source update register to update the clock source.

Definition at line 157 of file clock_11xx.c.

void Chip_Clock_SetCPUClockDiv | ( | uint32_t | div | ) |

Sets the CPU clock divider.

Parameters

  div,: | CPU clock divider, between 1 and divider max

Returns
  Nothing

Note
  The maximum divider for the 175x/6x is 256. The maximum divider for the 177x/8x and 407x/8x is 32. Note on 175x/6x devices, the divided CPU clock rate is used as the input to the peripheral clock dividers, while 177x/8x and 407x/8x devices use the undivided CPU clock rate.

Definition at line 192 of file clock_17xx_40xx.c.

void Chip_Clock_SetCPUClockSource | ( | CHIP_SYSCTL_CCLKSRC_T | src | ) |

Sets the current CPU clock source.

Parameters

  src | Source selected

Returns
  Nothing

Note
  When setting the clock source to the PLL, it should be enabled and locked.

Definition at line 143 of file clock_17xx_40xx.c.

STATIC INLINE void Chip_Clock_SetEMCClockDiv | ( | CHIP_SYSCTL_EMC_DIV_T | emcDiv | ) |

Selects a EMC divider rate.

Parameters

  emcDiv,: | Source clock for PLL

Returns
  Nothing

Note
  This function controls division of the clock before it is used by the EMC. The EMC uses the same base clock as the CPU and the APB peripherals. The EMC clock can tun at half or the same as the CPU clock. This is intended to be used primarily when the CPU is running faster than the external bus can support.

Definition at line 340 of file clock_17xx_40xx.h.

STATIC INLINE void Chip_Clock_SetLCDClockDiv | ( | uint32_t | div | ) |

Set the LCD clock prescaler.

Parameters

  div,: | Divider value, minimum of 1

Returns
  Nothing

Definition at line 639 of file clock_17xx_40xx.h.

STATIC INLINE void Chip_Clock_SetMainPllSource | ( | CHIP_SYSCTL_PLLCLKSRC_T | src | ) |

Selects a input clock source for SYSCLK.

Parameters

  src,: | input clock source for SYSCLK

Returns
  Nothing

Note
  SYSCLK is used for sourcing PLL0, SPIFI FLASH, the USB clock divider, and the CPU clock divider.

Definition at line 471 of file clock_17xx_40xx.h.

STATIC INLINE void Chip_Clock_SetPCLKDiv | ( | uint32_t | div | ) |

Sets a clock divider for all peripherals.

Parameters

  div,: | Divider for all peripherals, 0 = disable

Returns
  Nothing

Note
  All the peripherals in the device use the same clock divider. The divider is based on the CPU's clock rate. Use 0 to disable all peripheral clocks or a divider of 1 to 15. (LPC177X/8X and 407X/8X)

Definition at line 571 of file clock_17xx_40xx.h.

void Chip_Clock_SetSPIFIClockDiv | ( | uint32_t | div | ) |

Sets the SPIFI clock divider.

Parameters

  div,: | SPIFI clock divider, 0 to disable

Returns
  Nothing

Note
  Divider values are between 1 and 31

Definition at line 457 of file clock_17xx_40xx.c.

void Chip_Clock_SetSPIFIClockSource | ( | CHIP_SYSCTL_SPIFICLKSRC_T | src | ) |

Sets the SPIFI clock divider source.

Parameters

  src,: | SPIFI clock divider source clock

Returns
  Nothing

Definition at line 447 of file clock_17xx_40xx.c.

void Chip_Clock_SetupPLL | ( | CHIP_SYSCTL_PLL_T | pllNum,
|  | uint32_t | msel,
|  | uint32_t | psel
| ) |  |

Sets up a PLL.

Parameters

  pllNum,: | PLL number
  msel,: | PLL Multiplier value (Must be pre-decremented)
  psel,: | PLL Divider value (Must be pre-decremented)

Note
  See the User Manual for limitations on these values for stable PLL operation. Be careful with these values - they must be safe values for the msl, nsel, and psel registers so must be already decremented by 1 or the the correct value for psel (0 = div by 1, 1 = div by 2, etc.).

Returns
  Nothing

Definition at line 71 of file clock_17xx_40xx.c.

void Chip_Clock_SetUSBClockDiv | ( | uint32_t | div | ) |

Sets the USB clock divider.

Parameters

  div,: | USB clock divider to generate 48MHz from USB source clock

Returns
  Nothing

Note
  Divider values are between 1 and 32 (16 max for 175x/6x)

Definition at line 229 of file clock_17xx_40xx.c.

void Chip_Clock_SetUSBClockSource | ( | CHIP_SYSCTL_USBCLKSRC_T | src | ) |

Sets the USB clock divider source.

Parameters

  src,: | USB clock divider source clock

Returns
  Nothing

Note
  This function doesn't apply for LPC175x/6x devices. The divider must be be selected with the selected source to give a valid USB clock with a rate of 48MHz.

Definition at line 217 of file clock_17xx_40xx.c.