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cpu_c_m0.c
Go to the documentation of this file.
1 /*
2 *********************************************************************************************************
3 * uC/CPU
4 * CPU CONFIGURATION & PORT LAYER
5 *
6 * (c) Copyright 2004-2011; Micrium, Inc.; Weston, FL
7 *
8 * All rights reserved. Protected by international copyright laws.
9 *
10 * uC/CPU is provided in source form to registered licensees ONLY. It is
11 * illegal to distribute this source code to any third party unless you receive
12 * written permission by an authorized Micrium representative. Knowledge of
13 * the source code may NOT be used to develop a similar product.
14 *
15 * Please help us continue to provide the Embedded community with the finest
16 * software available. Your honesty is greatly appreciated.
17 *
18 * You can contact us at www.micrium.com.
19 *********************************************************************************************************
20 */
21
22 /*
23 *********************************************************************************************************
24 *
25 * CPU PORT FILE
26 *
27 * ARM-Cortex-M3
28 * RealView Development Suite
29 * RealView Microcontroller Development Kit (MDK)
30 * ARM Developer Suite (ADS)
31 * Keil uVision
32 *
33 * Filename : cpu_c.c
34 * Version : V1.28.00.00
35 * Programmer(s) : JJL
36 * BAN
37 * FT
38 *********************************************************************************************************
39 */
40
41
42 /*
43 *********************************************************************************************************
44 * INCLUDE FILES
45 *********************************************************************************************************
46 */
47
48 #include <cpu.h>
49 #include <cpu_core.h>
50
51 #include <lib_def.h>
52
53
54 /*$PAGE*/
55 /*
56 *********************************************************************************************************
57 * LOCAL DEFINES
58 *********************************************************************************************************
59 */
60
61 #define CPU_INT_SRC_POS_MAX (32)
62
63 #define CPU_BIT_BAND_SRAM_REG_LO 0x20000000
64 #define CPU_BIT_BAND_SRAM_REG_HI 0x200FFFFF
65 #define CPU_BIT_BAND_SRAM_BASE 0x22000000
66
67
68 #define CPU_BIT_BAND_PERIPH_REG_LO 0x40000000
69 #define CPU_BIT_BAND_PERIPH_REG_HI 0x400FFFFF
70 #define CPU_BIT_BAND_PERIPH_BASE 0x42000000
71
72
73 /*
74 *********************************************************************************************************
75 * LOCAL CONSTANTS
76 *********************************************************************************************************
77 */
78
79
80 /*
81 *********************************************************************************************************
82 * LOCAL DATA TYPES
83 *********************************************************************************************************
84 */
85
86
87 /*
88 *********************************************************************************************************
89 * LOCAL TABLES
90 *********************************************************************************************************
91 */
92
93
94 /*
95 *********************************************************************************************************
96 * LOCAL GLOBAL VARIABLES
97 *********************************************************************************************************
98 */
99
100
101 /*
102 *********************************************************************************************************
103 * LOCAL FUNCTION PROTOTYPES
104 *********************************************************************************************************
105 */
106
107
108 /*
109 *********************************************************************************************************
110 * LOCAL CONFIGURATION ERRORS
111 *********************************************************************************************************
112 */
113
114
115 /*$PAGE*/
116 /*
117 *********************************************************************************************************
118 * CPU_BitBandClr()
119 *
120 * Description : Clear bit in bit-band region.
121 *
122 * Argument(s) : addr Byte address in memory space.
123 *
124 * bit_nbr Bit number in byte.
125 *
126 * Return(s) : none.
127 *
128 * Caller(s) : Application.
129 *
130 * Note(s) : none.
131 *********************************************************************************************************
132 */
133
134 void CPU_BitBandClr (CPU_ADDR addr,
135 CPU_INT08U bit_nbr)
136 {
137 CPU_ADDR bit_word_off;
138 CPU_ADDR bit_word_addr;
139
140
141 if ((addr >= CPU_BIT_BAND_SRAM_REG_LO) &&
142 (addr <= CPU_BIT_BAND_SRAM_REG_HI)) {
143 bit_word_off = ((addr - CPU_BIT_BAND_SRAM_REG_LO ) * 32) + (bit_nbr * 4);
144 bit_word_addr = CPU_BIT_BAND_SRAM_BASE + bit_word_off;
145
146 *(volatile CPU_INT32U *)(bit_word_addr) = 0;
147
148 } else if ((addr >= CPU_BIT_BAND_PERIPH_REG_LO) &&
149 (addr <= CPU_BIT_BAND_PERIPH_REG_HI)) {
150 bit_word_off = ((addr - CPU_BIT_BAND_PERIPH_REG_LO) * 32) + (bit_nbr * 4);
151 bit_word_addr = CPU_BIT_BAND_PERIPH_BASE + bit_word_off;
152
153 *(volatile CPU_INT32U *)(bit_word_addr) = 0;
154 }
155 }
156
157
158 /*$PAGE*/
159 /*
160 *********************************************************************************************************
161 * CPU_BitBandSet()
162 *
163 * Description : Set bit in bit-band region.
164 *
165 * Argument(s) : addr Byte address in memory space.
166 *
167 * bit_nbr Bit number in byte.
168 *
169 * Return(s) : none.
170 *
171 * Caller(s) : Application.
172 *
173 * Note(s) : none.
174 *********************************************************************************************************
175 */
176
177 void CPU_BitBandSet (CPU_ADDR addr,
178 CPU_INT08U bit_nbr)
179 {
180 CPU_ADDR bit_word_off;
181 CPU_ADDR bit_word_addr;
182
183
184 if ((addr >= CPU_BIT_BAND_SRAM_REG_LO) &&
185 (addr <= CPU_BIT_BAND_SRAM_REG_HI)) {
186 bit_word_off = ((addr - CPU_BIT_BAND_SRAM_REG_LO ) * 32) + (bit_nbr * 4);
187 bit_word_addr = CPU_BIT_BAND_SRAM_BASE + bit_word_off;
188
189 *(volatile CPU_INT32U *)(bit_word_addr) = 1;
190
191 } else if ((addr >= CPU_BIT_BAND_PERIPH_REG_LO) &&
192 (addr <= CPU_BIT_BAND_PERIPH_REG_HI)) {
193 bit_word_off = ((addr - CPU_BIT_BAND_PERIPH_REG_LO) * 32) + (bit_nbr * 4);
194 bit_word_addr = CPU_BIT_BAND_PERIPH_BASE + bit_word_off;
195
196 *(volatile CPU_INT32U *)(bit_word_addr) = 1;
197 }
198 }
199
200
201 /*$PAGE*/
202 /*
203 *********************************************************************************************************
204 * CPU_IntSrcDis()
205 *
206 * Description : Disable an interrupt source.
207 *
208 * Argument(s) : pos Position of interrupt vector in interrupt table :
209 *
210 * 0 Invalid (see Note #1a).
211 * 1 Invalid (see Note #1b).
212 * 2 Non-maskable interrupt.
213 * 3 Hard Fault.
214 * 4 Memory Management.
215 * 5 Bus Fault.
216 * 6 Usage Fault.
217 * 7-10 Reserved.
218 * 11 SVCall
219 * 12 Debug monitor.
220 * 13 Reserved
221 * 14 PendSV.
222 * 15 SysTick.
223 * 16+ External Interrupt.
224 *
225 * Return(s) : none.
226 *
227 * Caller(s) : Application.
228 *
229 * Note(s) : (1) Several table positions do not contain interrupt sources :
230 *
231 * (a) Position 0 contains the stack pointer.
232 * (b) Positions 7-10, 13 are reserved.
233 *
234 * (2) Several interrupts cannot be disabled/enabled :
235 *
236 * (a) Reset.
237 * (b) NMI.
238 * (c) Hard fault.
239 * (d) SVCall.
240 * (e) Debug monitor.
241 * (f) PendSV.
242 *
243 * (3) The maximum Cortex-M3 table position is 256. A particular Cortex-M3 may have fewer
244 * than 240 external exceptions and, consequently, fewer than 256 table positions.
245 * This function assumes that the specified table position is valid if the interrupt
246 * controller type register's INTLINESNUM field is large enough so that the position
247 * COULD be valid.
248 *********************************************************************************************************
249 */
250 /*$PAGE*/
251 void CPU_IntSrcDis (CPU_INT08U pos)
252 {
253 CPU_INT08U group;
254 CPU_INT08U pos_max;
255 CPU_INT08U nbr;
256 CPU_SR_ALLOC();
257
258
259 switch (pos) {
260 case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
261 case CPU_INT_RSVD_07:
262 case CPU_INT_RSVD_08:
263 case CPU_INT_RSVD_09:
264 case CPU_INT_RSVD_10:
265 case CPU_INT_RSVD_13:
266 break;
267
268
269 /* ----------------- SYSTEM EXCEPTIONS ---------------- */
270 case CPU_INT_RESET: /* Reset (see Note #2). */
271 case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
272 case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
273 case CPU_INT_SVCALL: /* SVCall (see Note #2). */
274 case CPU_INT_DBGMON: /* Debug monitor (see Note #2). */
275 case CPU_INT_PENDSV: /* PendSV (see Note #2). */
276 break;
277
278 case CPU_INT_MEM: /* Memory management. */
279 CPU_CRITICAL_ENTER();
280 CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_MEMFAULTENA;
281 CPU_CRITICAL_EXIT();
282 break;
283
284 case CPU_INT_BUSFAULT: /* Bus fault. */
285 CPU_CRITICAL_ENTER();
286 CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_BUSFAULTENA;
287 CPU_CRITICAL_EXIT();
288 break;
289
290 case CPU_INT_USAGEFAULT: /* Usage fault. */
291 CPU_CRITICAL_ENTER();
292 CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_USGFAULTENA;
293 CPU_CRITICAL_EXIT();
294 break;
295
296 case CPU_INT_SYSTICK: /* SysTick. */
297 CPU_CRITICAL_ENTER();
298 CPU_REG_NVIC_ST_CTRL &= ~CPU_REG_NVIC_ST_CTRL_ENABLE;
299 CPU_CRITICAL_EXIT();
300 break;
301
302
303 /* ---------------- EXTERNAL INTERRUPT ---------------- */
304 default:
305 pos_max = CPU_INT_SRC_POS_MAX;
306 if (pos < pos_max) { /* See Note #3. */
307 group = (pos - 16) / 32;
308 nbr = (pos - 16) % 32;
309
310 CPU_CRITICAL_ENTER();
311 CPU_REG_NVIC_CLREN(group) = DEF_BIT(nbr);
312 CPU_CRITICAL_EXIT();
313 }
314 break;
315 }
316 }
317
318
319 /*$PAGE*/
320 /*
321 *********************************************************************************************************
322 * CPU_IntSrcEn()
323 *
324 * Description : Enable an interrupt source.
325 *
326 * Argument(s) : pos Position of interrupt vector in interrupt table (see 'CPU_IntSrcDis()').
327 *
328 * Return(s) : none.
329 *
330 * Caller(s) : Application.
331 *
332 * Note(s) : (1) See 'CPU_IntSrcDis() Note #1'.
333 *
334 * (2) See 'CPU_IntSrcDis() Note #2'.
335 *
336 * (3) See 'CPU_IntSrcDis() Note #3'.
337 *********************************************************************************************************
338 */
339
340 void CPU_IntSrcEn (CPU_INT08U pos)
341 {
342 CPU_INT08U group;
343 CPU_INT08U nbr;
344 CPU_INT08U pos_max;
345 CPU_SR_ALLOC();
346
347
348 switch (pos) {
349 case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
350 case CPU_INT_RSVD_07:
351 case CPU_INT_RSVD_08:
352 case CPU_INT_RSVD_09:
353 case CPU_INT_RSVD_10:
354 case CPU_INT_RSVD_13:
355 break;
356
357
358 /* ----------------- SYSTEM EXCEPTIONS ---------------- */
359 case CPU_INT_RESET: /* Reset (see Note #2). */
360 case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
361 case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
362 case CPU_INT_SVCALL: /* SVCall (see Note #2). */
363 case CPU_INT_DBGMON: /* Debug monitor (see Note #2). */
364 case CPU_INT_PENDSV: /* PendSV (see Note #2). */
365 break;
366
367 case CPU_INT_MEM: /* Memory management. */
368 CPU_CRITICAL_ENTER();
369 CPU_REG_NVIC_SHCSR |= CPU_REG_NVIC_SHCSR_MEMFAULTENA;
370 CPU_CRITICAL_EXIT();
371 break;
372
373 case CPU_INT_BUSFAULT: /* Bus fault. */
374 CPU_CRITICAL_ENTER();
375 CPU_REG_NVIC_SHCSR |= CPU_REG_NVIC_SHCSR_BUSFAULTENA;
376 CPU_CRITICAL_EXIT();
377 break;
378
379 case CPU_INT_USAGEFAULT: /* Usage fault. */
380 CPU_CRITICAL_ENTER();
381 CPU_REG_NVIC_SHCSR |= CPU_REG_NVIC_SHCSR_USGFAULTENA;
382 CPU_CRITICAL_EXIT();
383 break;
384
385 case CPU_INT_SYSTICK: /* SysTick. */
386 CPU_CRITICAL_ENTER();
387 CPU_REG_NVIC_ST_CTRL |= CPU_REG_NVIC_ST_CTRL_ENABLE;
388 CPU_CRITICAL_EXIT();
389 break;
390
391
392 /* ---------------- EXTERNAL INTERRUPT ---------------- */
393 default:
394 pos_max = CPU_INT_SRC_POS_MAX;
395 if (pos < pos_max) { /* See Note #3. */
396 group = (pos - 16) / 32;
397 nbr = (pos - 16) % 32;
398
399 CPU_CRITICAL_ENTER();
400 CPU_REG_NVIC_SETEN(group) = DEF_BIT(nbr);
401 CPU_CRITICAL_EXIT();
402 }
403 break;
404 }
405 }
406
407 /*$PAGE*/
408 /*
409 *********************************************************************************************************
410 * CPU_IntSrcPendClr()
411 *
412 * Description : Clear a pending interrupt.
413 *
414 * Argument(s) : pos Position of interrupt vector in interrupt table (see 'CPU_IntSrcDis()').
415 *
416 * Return(s) : none.
417 *
418 * Caller(s) : Application.
419 *
420 * Note(s) : (1) See 'CPU_IntSrcDis() Note #1'.
421 *
422 * (2) The pending status of several interrupts cannot be clear/set :
423 *
424 * (a) Reset.
425 * (b) NMI.
426 * (c) Hard fault.
427 * (d) Memory Managment.
428 * (e) Bus Fault.
429 * (f) Usage Fault.
430 * (g) SVCall.
431 * (h) Debug monitor.
432 * (i) PendSV.
433 * (j) Systick
434 *
435 * (3) See 'CPU_IntSrcDis() Note #3'.
436 *********************************************************************************************************
437 */
438
439 void CPU_IntSrcPendClr (CPU_INT08U pos)
440
441 {
442 CPU_INT08U group;
443 CPU_INT08U nbr;
444 CPU_INT08U pos_max;
445 CPU_SR_ALLOC();
446
447
448 switch (pos) {
449 case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
450 case CPU_INT_RSVD_07:
451 case CPU_INT_RSVD_08:
452 case CPU_INT_RSVD_09:
453 case CPU_INT_RSVD_10:
454 case CPU_INT_RSVD_13:
455 break;
456 /* ----------------- SYSTEM EXCEPTIONS ---------------- */
457 case CPU_INT_RESET: /* Reset (see Note #2). */
458 case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
459 case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
460 case CPU_INT_MEM: /* Memory management (see Note #2). */
461 case CPU_INT_SVCALL: /* SVCall (see Note #2). */
462 case CPU_INT_DBGMON: /* Debug monitor (see Note #2). */
463 case CPU_INT_PENDSV: /* PendSV (see Note #2). */
464 case CPU_INT_BUSFAULT: /* Bus fault. */
465 case CPU_INT_USAGEFAULT: /* Usage fault. */
466 case CPU_INT_SYSTICK: /* SysTick. */
467 break;
468 /* ---------------- EXTERNAL INTERRUPT ---------------- */
469 default:
470 pos_max = CPU_INT_SRC_POS_MAX;
471 if (pos < pos_max) { /* See Note #3. */
472 group = (pos - 16) / 32;
473 nbr = (pos - 16) % 32;
474
475 CPU_CRITICAL_ENTER();
476 CPU_REG_NVIC_CLRPEND(group) = DEF_BIT(nbr);
477 CPU_CRITICAL_EXIT();
478 }
479 break;
480 }
481 }
482
483
484 /*$PAGE*/
485 /*
486 *********************************************************************************************************
487 * CPU_IntSrcPrioSet()
488 *
489 * Description : Set priority of an interrupt source.
490 *
491 * Argument(s) : pos Position of interrupt vector in interrupt table (see 'CPU_IntSrcDis()').
492 *
493 * prio Priority. Use a lower priority number for a higher priority.
494 *
495 * Return(s) : none.
496 *
497 * Caller(s) : Application.
498 *
499 * Note(s) : (1) See 'CPU_IntSrcDis() Note #1'.
500 *
501 * (2) Several interrupts priorities CANNOT be set :
502 *
503 * (a) Reset (always -3).
504 * (b) NMI (always -2).
505 * (c) Hard fault (always -1).
506 *
507 * (3) See 'CPU_IntSrcDis() Note #3'.
508 *********************************************************************************************************
509 */
510
511 void CPU_IntSrcPrioSet (CPU_INT08U pos,
512 CPU_INT08U prio)
513 {
514 CPU_INT08U group;
515 CPU_INT08U nbr;
516 CPU_INT08U pos_max;
517 CPU_INT32U prio_32;
518 CPU_INT32U temp;
519 CPU_SR_ALLOC();
520
521
522 prio_32 = CPU_RevBits((CPU_INT08U)prio);
523 prio = (CPU_INT08U)(prio_32 >> (3 * DEF_OCTET_NBR_BITS));
524
525 switch (pos) {
526 case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
527 case CPU_INT_RSVD_07:
528 case CPU_INT_RSVD_08:
529 case CPU_INT_RSVD_09:
530 case CPU_INT_RSVD_10:
531 case CPU_INT_RSVD_13:
532 break;
533
534
535 /* ----------------- SYSTEM EXCEPTIONS ---------------- */
536 case CPU_INT_RESET: /* Reset (see Note #2). */
537 case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
538 case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
539 break;
540
541 case CPU_INT_MEM: /* Memory management. */
542 CPU_CRITICAL_ENTER();
543 temp = CPU_REG_NVIC_SHPRI1;
544 temp &= ~(DEF_OCTET_MASK << (0 * DEF_OCTET_NBR_BITS));
545 temp |= (prio << (0 * DEF_OCTET_NBR_BITS));
546 CPU_REG_NVIC_SHPRI1 = temp;
547 CPU_CRITICAL_EXIT();
548 break;
549
550 case CPU_INT_BUSFAULT: /* Bus fault. */
551 CPU_CRITICAL_ENTER();
552 temp = CPU_REG_NVIC_SHPRI1;
553 temp &= ~(DEF_OCTET_MASK << (1 * DEF_OCTET_NBR_BITS));
554 temp |= (prio << (1 * DEF_OCTET_NBR_BITS));
555 CPU_REG_NVIC_SHPRI1 = temp;
556 CPU_CRITICAL_EXIT();
557 break;
558
559 case CPU_INT_USAGEFAULT: /* Usage fault. */
560 CPU_CRITICAL_ENTER();
561 temp = CPU_REG_NVIC_SHPRI1;
562 temp &= ~(DEF_OCTET_MASK << (2 * DEF_OCTET_NBR_BITS));
563 temp |= (prio << (2 * DEF_OCTET_NBR_BITS));
564 CPU_REG_NVIC_SHPRI1 = temp;
565 CPU_CRITICAL_EXIT();
566 break;
567
568 case CPU_INT_SVCALL: /* SVCall. */
569 CPU_CRITICAL_ENTER();
570 temp = CPU_REG_NVIC_SHPRI2;
571 temp &= ~((CPU_INT32U)DEF_OCTET_MASK << (3 * DEF_OCTET_NBR_BITS));
572 temp |= (prio << (3 * DEF_OCTET_NBR_BITS));
573 CPU_REG_NVIC_SHPRI2 = temp;
574 CPU_CRITICAL_EXIT();
575 break;
576
577 case CPU_INT_DBGMON: /* Debug monitor. */
578 CPU_CRITICAL_ENTER();
579 temp = CPU_REG_NVIC_SHPRI3;
580 temp &= ~(DEF_OCTET_MASK << (0 * DEF_OCTET_NBR_BITS));
581 temp |= (prio << (0 * DEF_OCTET_NBR_BITS));
582 CPU_REG_NVIC_SHPRI3 = temp;
583 CPU_CRITICAL_EXIT();
584 break;
585
586 case CPU_INT_PENDSV: /* PendSV. */
587 CPU_CRITICAL_ENTER();
588 temp = CPU_REG_NVIC_SHPRI3;
589 temp &= ~(DEF_OCTET_MASK << (2 * DEF_OCTET_NBR_BITS));
590 temp |= (prio << (2 * DEF_OCTET_NBR_BITS));
591 CPU_REG_NVIC_SHPRI3 = temp;
592 CPU_CRITICAL_EXIT();
593 break;
594
595 case CPU_INT_SYSTICK: /* SysTick. */
596 CPU_CRITICAL_ENTER();
597 temp = CPU_REG_NVIC_SHPRI3;
598 temp &= ~((CPU_INT32U)DEF_OCTET_MASK << (3 * DEF_OCTET_NBR_BITS));
599 temp |= (prio << (3 * DEF_OCTET_NBR_BITS));
600 CPU_REG_NVIC_SHPRI3 = temp;
601 CPU_CRITICAL_EXIT();
602 break;
603
604
605 /* ---------------- EXTERNAL INTERRUPT ---------------- */
606 default:
607 pos_max = CPU_INT_SRC_POS_MAX;
608 if (pos < pos_max) { /* See Note #3. */
609 group = (pos - 16) / 4;
610 nbr = (pos - 16) % 4;
611
612 CPU_CRITICAL_ENTER();
613 temp = CPU_REG_NVIC_PRIO(group);
614 temp &= ~(DEF_OCTET_MASK << (nbr * DEF_OCTET_NBR_BITS));
615 temp |= (prio << (nbr * DEF_OCTET_NBR_BITS));
616 CPU_REG_NVIC_PRIO(group) = temp;
617 CPU_CRITICAL_EXIT();
618 }
619 break;
620 }
621 }
622
623
624 /*$PAGE*/
625 /*
626 *********************************************************************************************************
627 * CPU_IntSrcPrioGet()
628 *
629 * Description : Get priority of an interrupt source.
630 *
631 * Argument(s) : pos Position of interrupt vector in interrupt table (see 'CPU_IntSrcDis()').
632 *
633 * Return(s) : Priority of interrupt source. If the interrupt source specified is invalid, then
634 * DEF_INT_16S_MIN_VAL is returned.
635 *
636 * Caller(s) : Application.
637 *
638 * Note(s) : (1) See 'CPU_IntSrcDis() Note #1'.
639 *
640 * (2) See 'CPU_IntSrcPrioSet() Note #2'.
641 *
642 * (3) See 'CPU_IntSrcDis() Note #3'.
643 *********************************************************************************************************
644 */
645
646 CPU_INT16S CPU_IntSrcPrioGet (CPU_INT08U pos)
647 {
648 CPU_INT08U group;
649 CPU_INT08U nbr;
650 CPU_INT08U pos_max;
651 CPU_INT16S prio;
652 CPU_INT32U prio_32;
653 CPU_INT32U temp;
654 CPU_SR_ALLOC();
655
656
657 switch (pos) {
658 case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
659 case CPU_INT_RSVD_07:
660 case CPU_INT_RSVD_08:
661 case CPU_INT_RSVD_09:
662 case CPU_INT_RSVD_10:
663 case CPU_INT_RSVD_13:
664 prio = DEF_INT_16S_MIN_VAL;
665 break;
666
667
668 /* ----------------- SYSTEM EXCEPTIONS ---------------- */
669 case CPU_INT_RESET: /* Reset (see Note #2). */
670 prio = -3;
671 break;
672
673 case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
674 prio = -2;
675 break;
676
677 case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
678 prio = -1;
679 break;
680
681
682 case CPU_INT_MEM: /* Memory management. */
683 CPU_CRITICAL_ENTER();
684 temp = CPU_REG_NVIC_SHPRI1;
685 prio = (temp >> (0 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
686 CPU_CRITICAL_EXIT();
687 break;
688
689
690 case CPU_INT_BUSFAULT: /* Bus fault. */
691 CPU_CRITICAL_ENTER();
692 temp = CPU_REG_NVIC_SHPRI1;
693 prio = (temp >> (1 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
694 CPU_CRITICAL_EXIT();
695 break;
696
697
698 case CPU_INT_USAGEFAULT: /* Usage fault. */
699 CPU_CRITICAL_ENTER();
700 temp = CPU_REG_NVIC_SHPRI1;
701 prio = (temp >> (2 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
702 break;
703
704 case CPU_INT_SVCALL: /* SVCall. */
705 CPU_CRITICAL_ENTER();
706 temp = CPU_REG_NVIC_SHPRI2;
707 prio = (temp >> (3 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
708 CPU_CRITICAL_EXIT();
709 break;
710
711 case CPU_INT_DBGMON: /* Debug monitor. */
712 CPU_CRITICAL_ENTER();
713 temp = CPU_REG_NVIC_SHPRI3;
714 prio = (temp >> (0 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
715 CPU_CRITICAL_EXIT();
716 break;
717
718 case CPU_INT_PENDSV: /* PendSV. */
719 CPU_CRITICAL_ENTER();
720 temp = CPU_REG_NVIC_SHPRI3;
721 prio = (temp >> (2 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
722 CPU_CRITICAL_EXIT();
723 break;
724
725 case CPU_INT_SYSTICK: /* SysTick. */
726 CPU_CRITICAL_ENTER();
727 temp = CPU_REG_NVIC_SHPRI3;
728 prio = (temp >> (3 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
729 CPU_CRITICAL_EXIT();
730 break;
731
732
733 /* ---------------- EXTERNAL INTERRUPT ---------------- */
734 default:
735 pos_max = CPU_INT_SRC_POS_MAX;
736 if (pos < pos_max) { /* See Note #3. */
737 group = (pos - 16) / 4;
738 nbr = (pos - 16) % 4;
739
740 CPU_CRITICAL_ENTER();
741 temp = CPU_REG_NVIC_PRIO(group);
742 CPU_CRITICAL_EXIT();
743
744 prio = (temp >> (nbr * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
745 } else {
746 prio = DEF_INT_16S_MIN_VAL;
747 }
748 break;
749 }
750
751 if (prio >= 0) {
752 prio_32 = CPU_RevBits((CPU_INT32U)prio);
753 prio = (CPU_INT16S)(prio_32 >> (3 * DEF_OCTET_NBR_BITS));
754 }
755
756 return (prio);
757 }
758