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clock_13xx.c
Go to the documentation of this file.
1 /*
2 * @brief LPC13XX System clock control functions
3 *
4 * Copyright(C) NXP Semiconductors, 2012
5 * All rights reserved.
6 *
7 * Software that is described herein is for illustrative purposes only
8 * which provides customers with programming information regarding the
9 * LPC products. This software is supplied "AS IS" without any warranties of
10 * any kind, and NXP Semiconductors and its licensor disclaim any and
11 * all warranties, express or implied, including all implied warranties of
12 * merchantability, fitness for a particular purpose and non-infringement of
13 * intellectual property rights. NXP Semiconductors assumes no responsibility
14 * or liability for the use of the software, conveys no license or rights under any
15 * patent, copyright, mask work right, or any other intellectual property rights in
16 * or to any products. NXP Semiconductors reserves the right to make changes
17 * in the software without notification. NXP Semiconductors also makes no
18 * representation or warranty that such application will be suitable for the
19 * specified use without further testing or modification.
20 *
21 * Permission to use, copy, modify, and distribute this software and its
22 * documentation is hereby granted, under NXP Semiconductors' and its
23 * licensor's relevant copyrights in the software, without fee, provided that it
24 * is used in conjunction with NXP Semiconductors microcontrollers. This
25 * copyright, permission, and disclaimer notice must appear in all copies of
26 * this code.
27 */
28
29 #include "chip.h"
30
31 /*****************************************************************************
32 * Private types/enumerations/variables
33 ****************************************************************************/
34
35 /* Inprecise clock rates for the watchdog oscillator */
36 STATIC const uint32_t wdtOSCRate[WDTLFO_OSC_4_60 + 1] = {
37 0, /* WDT_OSC_ILLEGAL */
38 600000, /* WDT_OSC_0_60 */
39 1050000, /* WDT_OSC_1_05 */
40 1400000, /* WDT_OSC_1_40 */
41 1750000, /* WDT_OSC_1_75 */
42 2100000, /* WDT_OSC_2_10 */
43 2400000, /* WDT_OSC_2_40 */
44 2700000, /* WDT_OSC_2_70 */
45 3000000, /* WDT_OSC_3_00 */
46 3250000, /* WDT_OSC_3_25 */
47 3500000, /* WDT_OSC_3_50 */
48 3750000, /* WDT_OSC_3_75 */
49 4000000, /* WDT_OSC_4_00 */
50 4200000, /* WDT_OSC_4_20 */
51 4400000, /* WDT_OSC_4_40 */
52 4600000 /* WDT_OSC_4_60 */
53 };
54
55 /*****************************************************************************
56 * Public types/enumerations/variables
57 ****************************************************************************/
58
59 /*****************************************************************************
60 * Private functions
61 ****************************************************************************/
62
63 /* Compute a WDT or LFO rate */
64 STATIC uint32_t Chip_Clock_GetWDTLFORate(uint32_t reg)
65 {
66 uint32_t div;
67 CHIP_WDTLFO_OSC_T clk;
68
69 /* Get WDT oscillator settings */
70 clk = (CHIP_WDTLFO_OSC_T) ((reg >> 5) & 0xF);
71 div = reg & 0x1F;
72
73 /* Compute clock rate and divided by divde value */
74 return wdtOSCRate[clk] / ((div + 1) << 1);
75 }
76
77 /* Compute a PLL frequency */
78 STATIC uint32_t Chip_Clock_GetPllFreq(uint32_t pllReg, uint32_t inputRate)
79 {
80 uint32_t msel = ((pllReg & 0x1F) + 1);
81
82 return inputRate * msel;
83 }
84
85 /*****************************************************************************
86 * Public functions
87 ****************************************************************************/
88
89 /* Set System PLL clock source */
90 void Chip_Clock_SetSystemPllSource(CHIP_SYSCTL_PLLCLKSRC_T src)
91 {
92 LPC_SYSCTL->SYSPLLCLKSEL = (uint32_t) src;
93 #if defined(CHIP_LPC1343)
94 LPC_SYSCTL->SYSPLLCLKUEN = 0;
95 LPC_SYSCTL->SYSPLLCLKUEN = 1;
96 #endif
97 }
98
99 /* Bypass System Oscillator and set oscillator frequency range */
100 void Chip_Clock_SetPLLBypass(bool bypass, bool highfr)
101 {
102 uint32_t ctrl = 0;
103
104 if (bypass) {
105 ctrl |= (1 << 0);
106 }
107 if (highfr) {
108 ctrl |= (1 << 1);
109 }
110
111 LPC_SYSCTL->SYSOSCCTRL = ctrl;
112 }
113
114 /* Set USB PLL clock source */
115 void Chip_Clock_SetUSBPllSource(CHIP_SYSCTL_PLLCLKSRC_T src)
116 {
117 LPC_SYSCTL->USBPLLCLKSEL = (uint32_t) src;
118 #if defined(CHIP_LPC1343)
119 LPC_SYSCTL->USBPLLCLKUEN = 0;
120 LPC_SYSCTL->USBPLLCLKUEN = 1;
121 #endif
122 }
123
124 /* Set main system clock source */
125 void Chip_Clock_SetMainClockSource(CHIP_SYSCTL_MAINCLKSRC_T src)
126 {
127 LPC_SYSCTL->MAINCLKSEL = (uint32_t) src;
128 #if defined(CHIP_LPC1343)
129 LPC_SYSCTL->MAINCLKUEN = 0;
130 LPC_SYSCTL->MAINCLKUEN = 1;
131 #endif
132 }
133
134 /* Set USB clock source and divider */
135 void Chip_Clock_SetUSBClockSource(CHIP_SYSCTL_USBCLKSRC_T src, uint32_t div)
136 {
137 LPC_SYSCTL->USBCLKSEL = (uint32_t) src;
138 #if defined(CHIP_LPC1343)
139 LPC_SYSCTL->USBCLKUEN = 0;
140 LPC_SYSCTL->USBCLKUEN = 1;
141 #endif
142 LPC_SYSCTL->USBCLKDIV = div;
143 }
144
145 #if defined(CHIP_LPC1343)
146 /* Set WDT clock source and divider */
147 void Chip_Clock_SetWDTClockSource(CHIP_SYSCTL_WDTCLKSRC_T src, uint32_t div)
148 {
149 LPC_SYSCTL->WDTCLKSEL = (uint32_t) src;
150 LPC_SYSCTL->WDTCLKUEN = 0;
151 LPC_SYSCTL->WDTCLKUEN = 1;
152 LPC_SYSCTL->WDTCLKDIV = div;
153 }
154
155 #endif
156
157 /* Set CLKOUT clock source and divider */
158 void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div)
159 {
160 LPC_SYSCTL->CLKOUTSEL = (uint32_t) src;
161 #if defined(CHIP_LPC1343)
162 LPC_SYSCTL->CLKOUTUEN = 0;
163 LPC_SYSCTL->CLKOUTUEN = 1;
164 #endif
165 LPC_SYSCTL->CLKOUTDIV = div;
166 }
167
168 /* Return estimated watchdog oscillator rate */
169 uint32_t Chip_Clock_GetWDTOSCRate(void)
170 {
171 return Chip_Clock_GetWDTLFORate(LPC_SYSCTL->WDTOSCCTRL);
172 }
173
174 /* Return System PLL input clock rate */
175 uint32_t Chip_Clock_GetSystemPllInClockRate(void)
176 {
177 uint32_t clkRate;
178
179 switch ((CHIP_SYSCTL_PLLCLKSRC_T) (LPC_SYSCTL->SYSPLLCLKSEL & 0x3)) {
180 case SYSCTL_PLLCLKSRC_IRC:
181 clkRate = Chip_Clock_GetIntOscRate();
182 break;
183
184 case SYSCTL_PLLCLKSRC_SYSOSC:
185 clkRate = Chip_Clock_GetMainOscRate();
186 break;
187
188 default:
189 clkRate = 0;
190 }
191
192 return clkRate;
193 }
194
195 /* Return System PLL output clock rate */
196 uint32_t Chip_Clock_GetSystemPllOutClockRate(void)
197 {
198 return Chip_Clock_GetPllFreq(LPC_SYSCTL->SYSPLLCTRL,
199 Chip_Clock_GetSystemPllInClockRate());
200 }
201
202 /* Return USB PLL input clock rate */
203 uint32_t Chip_Clock_GetUSBPllInClockRate(void)
204 {
205 uint32_t clkRate;
206
207 switch ((CHIP_SYSCTL_PLLCLKSRC_T) (LPC_SYSCTL->USBPLLCLKSEL & 0x3)) {
208 case SYSCTL_PLLCLKSRC_IRC:
209 clkRate = Chip_Clock_GetIntOscRate();
210 break;
211
212 case SYSCTL_PLLCLKSRC_SYSOSC:
213 clkRate = Chip_Clock_GetMainOscRate();
214 break;
215
216 default:
217 clkRate = 0;
218 }
219
220 return clkRate;
221 }
222
223 /* Return USB PLL output clock rate */
224 uint32_t Chip_Clock_GetUSBPllOutClockRate(void)
225 {
226 return Chip_Clock_GetPllFreq(LPC_SYSCTL->USBPLLCTRL,
227 Chip_Clock_GetUSBPllInClockRate());
228 }
229
230 /* Return main clock rate */
231 uint32_t Chip_Clock_GetMainClockRate(void)
232 {
233 uint32_t clkRate = 0;
234
235 switch ((CHIP_SYSCTL_MAINCLKSRC_T) (LPC_SYSCTL->MAINCLKSEL & 0x3)) {
236 case SYSCTL_MAINCLKSRC_IRC:
237 clkRate = Chip_Clock_GetIntOscRate();
238 break;
239
240 case SYSCTL_MAINCLKSRC_PLLIN:
241 clkRate = Chip_Clock_GetSystemPllInClockRate();
242 break;
243
244 case SYSCTL_MAINCLKSRC_WDTOSC:
245 clkRate = Chip_Clock_GetWDTOSCRate();
246 break;
247
248 case SYSCTL_MAINCLKSRC_PLLOUT:
249 clkRate = Chip_Clock_GetSystemPllOutClockRate();
250 break;
251 }
252
253 return clkRate;
254 }
255
256 /* Return system clock rate */
257 uint32_t Chip_Clock_GetSystemClockRate(void)
258 {
259 /* No point in checking for divide by 0 */
260 return Chip_Clock_GetMainClockRate() / LPC_SYSCTL->SYSAHBCLKDIV;
261 }