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spi_001.h
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1 /*
2 * @brief SPI registers and control functions
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __SPI_001_H_
33 #define __SPI_001_H_
34
35 #include "sys_config.h"
36 #include "cmsis.h"
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
50 typedef struct {
51 __IO uint32_t CR;
52 __I uint32_t SR;
53 __IO uint32_t DR;
54 __IO uint32_t CCR;
55 __I uint32_t RESERVED0[3];
56 __IO uint32_t INT;
57 } IP_SPI_001_T;
58
59 /*
60 * Macro defines for SPI Control register
61 */
62 /* SPI CFG Register BitMask */
63 #define SPI_CR_BITMASK ((uint32_t) 0xFFC)
64
65 #define SPI_CR_BIT_EN ((uint32_t) (1 << 2))
66
67 #define SPI_CR_BITS_MASK ((uint32_t) 0xF00)
68
69 #define SPI_CR_BITS(n) ((uint32_t) ((n << 8) & 0xF00)) /* n is in range 8-16 */
70
71 #define SPI_CR_CPHA_FIRST ((uint32_t) (0)) /*Capture data on the first edge, Change data on the following edge*/
72 #define SPI_CR_CPHA_SECOND ((uint32_t) (1 << 3)) /*Change data on the first edge, Capture data on the following edge*/
73
74 #define SPI_CR_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/
75 #define SPI_CR_CPOL_HI ((uint32_t) (1 << 4)) /* The rest state of the clock (between frames) is high.*/
76
77 #define SPI_CR_SLAVE_EN ((uint32_t) 0)
78
79 #define SPI_CR_MASTER_EN ((uint32_t) (1 << 5))
80
81 #define SPI_CR_MSB_FIRST_EN ((uint32_t) 0) /*Data will be transmitted and received in standard order (MSB first).*/
82
83 #define SPI_CR_LSB_FIRST_EN ((uint32_t) (1 << 6)) /*Data will be transmitted and received in reverse order (LSB first).*/
84
85 #define SPI_CR_INT_EN ((uint32_t) (1 << 7))
86
87 /*
88 * Macro defines for SPI Status register
89 */
91 #define SPI_SR_BITMASK ((uint32_t) 0xF8)
92
93 #define SPI_SR_ABRT ((uint32_t) (1 << 3)) /* When 1, this bit indicates that a slave abort has occurred. */
94 /* Mode fault Flag */
95 #define SPI_SR_MODF ((uint32_t) (1 << 4)) /* when 1, this bit indicates that a Mode fault error has occurred. */
96
97 #define SPI_SR_ROVR ((uint32_t) (1 << 5)) /* When 1, this bit indicates that a read overrun has occurred. */
98
99 #define SPI_SR_WCOL ((uint32_t) (1 << 6)) /* When 1, this bit indicates that a write collision has occurred.. */
100
101 #define SPI_SR_SPIF ((uint32_t) (1 << 7)) /* When 1, this bit indicates when a SPI data transfer is complete.. */
102
103 #define SPI_SR_ERROR (SPI_SR_ABRT | SPI_SR_MODF | SPI_SR_ROVR | SPI_SR_WCOL)
104 /*
105 * Macro defines for SPI Test Control Register register
106 */
107 /*Enable SPI Test Mode */
108 #define SPI_TCR_TEST(n) ((uint32_t) ((n & 0x3F) << 1))
109
110 /*
111 * Macro defines for SPI Interrupt register
112 */
114 #define SPI_INT_SPIF ((uint32_t) (1 << 0))
115
120 #define SPI_DR_DATA(n) ((uint32_t) ((n) & 0xFFFF))
121
123 typedef enum IP_SPI_MODE {
124 SPI_MODE_MASTER = SPI_CR_MASTER_EN, /* Master Mode */
125 SPI_MODE_SLAVE = SPI_CR_SLAVE_EN, /* Slave Mode */
126 } IP_SPI_MODE_T;
127
129 typedef enum IP_SPI_CLOCK_MODE {
130 SPI_CLOCK_CPHA0_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_FIRST,
131 SPI_CLOCK_CPHA0_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_FIRST,
132 SPI_CLOCK_CPHA1_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_SECOND,
133 SPI_CLOCK_CPHA1_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_SECOND,
134 SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0,
135 SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0,
136 SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1,
137 SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1,
138 } IP_SPI_CLOCK_MODE_T;
139
141 typedef enum IP_SPI_DATA_ORDER {
142 SPI_DATA_MSB_FIRST = SPI_CR_MSB_FIRST_EN, /* Standard Order */
143 SPI_DATA_LSB_FIRST = SPI_CR_LSB_FIRST_EN, /* Reverse Order */
144 } IP_SPI_DATA_ORDER_T;
145
146 /*
147 * @brief Number of bits per frame
148 */
149 typedef enum IP_SPI_BITS {
150 SPI_BITS_8 = SPI_CR_BITS(8),
151 SPI_BITS_9 = SPI_CR_BITS(9),
152 SPI_BITS_10 = SPI_CR_BITS(10),
153 SPI_BITS_11 = SPI_CR_BITS(11),
154 SPI_BITS_12 = SPI_CR_BITS(12),
155 SPI_BITS_13 = SPI_CR_BITS(13),
156 SPI_BITS_14 = SPI_CR_BITS(14),
157 SPI_BITS_15 = SPI_CR_BITS(15),
158 SPI_BITS_16 = SPI_CR_BITS(16),
159 } IP_SPI_BITS_T;
160
167 STATIC INLINE uint32_t IP_SPI_GetStatus(IP_SPI_001_T *pSPI)
168 {
169 return pSPI->SR;
170 }
171
177 STATIC INLINE void IP_SPI_IntEnable(IP_SPI_001_T *pSPI)
178 {
179 pSPI->CR |= SPI_CR_INT_EN;
180 }
181
187 STATIC INLINE void IP_SPI_IntDisable(IP_SPI_001_T *pSPI)
188 {
189 pSPI->CR &= ~SPI_CR_INT_EN;
190 }
191
197 STATIC INLINE uint32_t IP_SPI_GetIntStatus(IP_SPI_001_T *pSPI)
198 {
199 return pSPI->INT;
200 }
201
208 STATIC INLINE void IP_SPI_ClearIntStatus(IP_SPI_001_T *pSPI, uint32_t mask)
209 {
210 pSPI->INT = mask;
211 }
212
219 STATIC INLINE void IP_SPI_SendFrame(IP_SPI_001_T *pSPI, uint16_t data)
220 {
221 pSPI->DR = SPI_DR_DATA(data);
222 }
223
229 STATIC INLINE uint16_t IP_SPI_ReceiveFrame(IP_SPI_001_T *pSPI)
230 {
231 return SPI_DR_DATA(pSPI->DR);
232 }
233
242 STATIC INLINE void IP_SPI_SetClockCounter(IP_SPI_001_T *pSPI, uint32_t counter)
243 {
244 pSPI->CCR = counter;
245 }
246
261 STATIC INLINE void IP_SPI_SetFormat(IP_SPI_001_T *pSPI, IP_SPI_BITS_T bits,
262 IP_SPI_CLOCK_MODE_T clockMode, IP_SPI_DATA_ORDER_T order)
263 {
264 pSPI->CR = (pSPI->CR & (~0xF1C)) | SPI_CR_BIT_EN | bits | clockMode | order;
265 }
266
272 STATIC INLINE IP_SPI_BITS_T IP_SPI_GetDataSize(IP_SPI_001_T *pSPI)
273 {
274 return (pSPI->CR & SPI_CR_BIT_EN) ? ((IP_SPI_BITS_T) (pSPI->CR & SPI_CR_BITS_MASK)) : SPI_BITS_8;
275 }
276
282 STATIC INLINE IP_SPI_CLOCK_MODE_T IP_SPI_GetClockMode(IP_SPI_001_T *pSPI)
283 {
284 return (IP_SPI_CLOCK_MODE_T) (pSPI->CR & (3 << 3));
285 }
286
293 STATIC INLINE void IP_SPI_SetMode(IP_SPI_001_T *pSPI, IP_SPI_MODE_T mode)
294 {
295 pSPI->CR = (pSPI->CR & (~(1 << 5))) | mode;
296 }
297
303 STATIC INLINE IP_SPI_MODE_T IP_SPI_GetMode(IP_SPI_001_T *pSPI)
304 {
305 return (IP_SPI_MODE_T) (pSPI->CR & (1 << 5));
306 }
307
312 #ifdef __cplusplus
313 }
314 #endif
315
316 #endif /* __SPI_001_H_ */