Endpoint_LPC18xx.h

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/*
 * @brief USB Endpoint definitions for the LPC18xx microcontrollers
 *
 * @note
 * Copyright(C) NXP Semiconductors, 2012
 * All rights reserved.
 *
 * @par
 * Software that is described herein is for illustrative purposes only
 * which provides customers with programming information regarding the
 * LPC products.  This software is supplied "AS IS" without any warranties of
 * any kind, and NXP Semiconductors and its licensor disclaim any and
 * all warranties, express or implied, including all implied warranties of
 * merchantability, fitness for a particular purpose and non-infringement of
 * intellectual property rights.  NXP Semiconductors assumes no responsibility
 * or liability for the use of the software, conveys no license or rights under any
 * patent, copyright, mask work right, or any other intellectual property rights in
 * or to any products. NXP Semiconductors reserves the right to make changes
 * in the software without notification. NXP Semiconductors also makes no
 * representation or warranty that such application will be suitable for the
 * specified use without further testing or modification.
 *
 * @par
 * Permission to use, copy, modify, and distribute this software and its
 * documentation is hereby granted, under NXP Semiconductors' and its
 * licensor's relevant copyrights in the software, without fee, provided that it
 * is used in conjunction with NXP Semiconductors microcontrollers.  This
 * copyright, permission, and disclaimer notice must appear in all copies of
 * this code.
 */

#ifndef __ENDPOINT_LPC18XX_H__
#define __ENDPOINT_LPC18XX_H__

 #include "../EndpointCommon.h"

/* Enable C linkage for C++ Compilers: */
  #if defined(__cplusplus)
extern "C" {
  #endif

/* Preprocessor Checks: */
  #if !defined(__INCLUDE_FROM_USB_DRIVER)
   #error Do not include this file directly. Include lpcroot/libraries/LPCUSBlib/Drivers/USB/USB.h instead.
  #endif

/* Private Interface - For use in library only: */
 #if !defined(__DOXYGEN__)
/* Macros: */
    #define ENDPOINT_DETAILS_MAXEP0             6
    #define ENDPOINT_DETAILS_MAXEP1             4

   #if defined(USB_DEVICE_ROM_DRIVER)
/*==========================================================================*/
/* USB ROM DRIVER DEFINITIONS */

/* A table of pointers to the chip's main ROM functions contained in ROM is located at the
   address contained at this location */
typedef struct _ROM {
 const unsigned p_otp;
 const unsigned p_aes;
 const unsigned p_pwd;
 const unsigned p_clk;
 const unsigned p_ipc;
 const unsigned p_spifi;
 const unsigned p_usbd;
}  ROM_FUNCTION_TABLE;

/* A table of pointers to the USBD functions contained in ROM is located at the
   address contained at this location */
    #define ROM_FUNCTION_TABLE_PTR_ADDR         (0x10400104UL)
    #define ROM_USBD_PTR (((ROM_FUNCTION_TABLE *) (ROM_FUNCTION_TABLE_PTR_ADDR))->p_usbd)

    #define ROMDRIVER_USB0_BASE LPC_USB0_BASE
    #define ROMDRIVER_USB1_BASE LPC_USB1_BASE
    #define ROMDRIVER_MEM_SIZE  0x1000
extern uint8_t usb_RomDriver_buffer[ROMDRIVER_MEM_SIZE];

    #define ROMDRIVER_MSC_MEM_SIZE  0x1000
extern uint8_t usb_RomDriver_MSC_buffer[ROMDRIVER_MSC_MEM_SIZE];

    #define ROMDRIVER_CDC_MEM_SIZE  0x800
extern uint8_t usb_RomDriver_CDC_buffer[ROMDRIVER_CDC_MEM_SIZE];
    #define ROMDRIVER_CDC_DATA_BUFFER_SIZE  640
    #if (USB_FORCED_FULLSPEED)
     #define CDC_MAX_BULK_EP_SIZE            64
    #else
     #define CDC_MAX_BULK_EP_SIZE            512
    #endif
extern uint8_t UsbdCdc_EPIN_buffer[CDC_MAX_BULK_EP_SIZE];
extern uint8_t UsbdCdc_EPOUT_buffer[CDC_MAX_BULK_EP_SIZE];

    #define ROMDRIVER_HID_MEM_SIZE  0x800
extern uint8_t usb_RomDriver_HID_buffer[ROMDRIVER_HID_MEM_SIZE];
/*==========================================================================*/
   #endif

/*==========================================================================*/
/* DEVICE REGISTER DEFINITIONS                                                                  */
/*==========================================================================*/
/*---------- USBCMD ----------*/
    #define USBCMD_D_RunStop                (1 << 0)  /* Run or Stop */
    #define USBCMD_D_Reset                  (1 << 1)  /* Host Controller Reset */
    #define USBCMD_D_SetupTripWire          (1 << 13)
    #define USBCMD_D_AddTDTripWire          (1 << 14)
    #define USBCMD_D_IntThreshold           (0xff << 16)

/*---------- USBSTS ----------*/
    #define USBSTS_D_UsbInt                     0x00000001UL  /* USB Interrupt */
    #define USBSTS_D_UsbErrorInt                0x00000002UL  /* USB Error Interrupt */
    #define USBSTS_D_PortChangeDetect           0x00000004UL  /* Port Change Detect */
    #define USBSTS_D_ResetReceived              (1 << 6)
    #define USBSTS_D_SofReceived                (1 << 7)
    #define USBSTS_D_SuspendInt                 (1 << 8)
    #define USBSTS_D_NAK                        (1 << 16)

/*---------- USBINTR ----------*/
    #define USBINTR_D_UsbIntEnable              (1 << 0)
    #define USBINTR_D_UsbErrorIntEnable         (1 << 1)
    #define USBINTR_D_PortChangeIntEnable       (1 << 2)
    #define USBINTR_D_UsbResetEnable            (1 << 6)
    #define USBINTR_D_SofReceivedEnable         (1 << 7)
    #define USBINTR_D_SuspendEnable             (1 << 8)
    #define USBINTR_D_NAKEnable                 (1 << 16)

/*---------- DEVICEADDR ----------*/
    #define DEVICEADDR_AddressAdvance           (1 << 24)
    #define DEVICEADDR_DeviceAddr               (0xff << 25)

/*---------- ENDPTNAK ----------*/
    #define ENDPTNAK_RX                         (0x3f)
    #define ENDPTNAK_TX                         (0x3f << 16)

/*---------- ENDPTNAKEN ----------*/
    #define ENDPTNAKEN_RX                       (0x3f)
    #define ENDPTNAKEN_TX                       (0x3f << 16)

/*---------- PORTSC ----------*/
    #define PORTSC_D_CurrentConnectStatus           0x00000001UL  /* Current Connect Status */
    #define PORTSC_D_ForcePortResume                0x00000040UL  /* Force Port Resume */
    #define PORTSC_D_PortSuspend                    0x00000080UL  /* Port Suspend */
    #define PORTSC_D_PortReset                  0x00000100UL  /* Port Reset */
    #define PORTSC_D_HighSpeedStatus                0x00000200UL  /* Line Status */
    #define PORTSC_D_PortIndicatorControl           0x0000C000UL  /* Port Indicator Control */
    #define PORTSC_D_PortTestControl                0x000F0000UL  /* Port Test Control */
    #define PORTSC_D_PhyClockDisable                0x00800000UL  /* PHY Clock Disable - EHCI derivation */
    #define PORTSC_D_PortForceFullspeedConnect  0x01000000UL  /* Force Device on Fullspeed mode (disable chirp sequences) - EHCI derivation */
    #define PORTSC_D_PortSpeed                  0x0C000000UL  /* Device Speed - EHCI derivation */

/*---------- USBMODE_D ----------*/
/*---------- ENDPSETUPSTAT ----------*/

/*---------- ENDPTPRIME ----------*/
    #define ENDPTPRIME_RX                       (0x3f)
    #define ENDPTPRIME_TX                       (0x3f << 16)

/*---------- ENDPTFLUSH ----------*/
    #define ENDPTFLUSH_RX                       (0x3f)
    #define ENDPTFLUSH_TX                       (0x3f << 16)

/*---------- ENDPTSTAT ----------*/
    #define ENDPTSTAT_RX                        (0x3f)
    #define ENDPTSTAT_TX                        (0x3f << 16)

/*---------- ENDPTCOMPLETE ----------*/
    #define ENDPTCOMPLETE_RX                        (0x3f)
    #define ENDPTCOMPLETE_TX                        (0x3f << 16)

/*---------- ENDPTCTRL ----------*/
    #define ENDPTCTRL_RxStall                   (1)
    #define ENDPTCTRL_RxType                    (3 << 2)
    #define ENDPTCTRL_RxToggleInhibit           (1 << 5)
    #define ENDPTCTRL_RxToggleReset             (1 << 6)
    #define ENDPTCTRL_RxEnable                  (1 << 7)

    #define ENDPTCTRL_TxStall                   (1 << 16)
    #define ENDPTCTRL_TxType                    (3 << 18)
    #define ENDPTCTRL_TxToggleInhibit           (1 << 21)
    #define ENDPTCTRL_TxToggleReset             (1 << 22)
    #define ENDPTCTRL_TxEnable                  (1 << 23)
    #define ENDPTCTRL_REG(corenum, LogicalAddr)  ( ((__IO uint32_t *) &(USB_REG(corenum)->ENDPTCTRL[0]))[ \
                LogicalAddr] )
    #define EP_Physical2Logical(n)      ((n) / 2)
/* Total physical endpoints*/
    #define USED_PHYSICAL_ENDPOINTS0      ENDPOINT_DETAILS_MAXEP0 * 2 /* This macro effect memory size of the DCD */
    #define USED_PHYSICAL_ENDPOINTS1      ENDPOINT_DETAILS_MAXEP1 * 2 /* This macro effect memory size of the DCD */
    #define USED_PHYSICAL_ENDPOINTS(corenum)  ((corenum) ? USED_PHYSICAL_ENDPOINTS1 : USED_PHYSICAL_ENDPOINTS0) /* This macro effect memory size of the DCD */
    #define EP_Physical2BitPosition(n) ( EP_Physical2Logical(n) + ((n) % 2 ? 16 : 0 ) )
//    #define LINK_TERMINATE      1

/*---------- Device TD ----------*/
typedef struct {
 /*---------- Word 1 ----------*/
 uint32_t NextTD;

 /*---------- Word 2 ----------*/
 uint32_t : 3;
 __IO uint32_t TransactionErr : 1;
 uint32_t : 1;
 __IO uint32_t BufferErr : 1;
 __IO uint32_t Halted : 1;
 __IO uint32_t Active : 1;
 uint32_t : 2;
 uint32_t MultiplierOverride : 2;
 uint32_t : 3;
 __IO uint32_t IntOnComplete : 1;
 __IO uint32_t TotalBytes : 15;
 uint32_t : 0;     /* force next member alinged on the next word */

 /*---------- Word 3 - 7 ----------*/
 uint32_t BufferPage[5];

 uint32_t reserved;
} DeviceTransferDescriptor, *PDeviceTransferDescriptor;

/*---------- Device Qhd ----------*/
typedef struct {
 /*---------- Word 1: Capability/Characteristics ----------*/
 uint32_t : 15;
 __IO uint32_t IntOnSetup : 1;
 uint32_t MaxPacketSize : 11;
 uint32_t : 2;
 __IO uint32_t ZeroLengthTermination : 1;
 uint32_t Mult : 2;
 uint32_t : 0;

 /*---------- Word 2 ----------*/
 uint32_t currentTD;

 /*---------- Word 3 - 10 ----------*/
 __IO DeviceTransferDescriptor overlay;

 /*---------- Word 11-12 ----------*/
 __IO uint8_t SetupPackage[8];

 uint16_t TransferCount;
 __IO uint16_t IsOutReceived;    // === TODO: IsOutReceived should be refractor to QueueHead Status ===
 uint16_t reserved[6];
} DeviceQueueHead, *PDeviceQueueHead;

extern volatile DeviceQueueHead * const dQueueHead[];
extern DeviceTransferDescriptor * const dTransferDescriptor[];

void DcdDataTransfer(uint8_t corenum, uint8_t EPNum, uint8_t *pData, uint32_t cnt);

void Endpoint_Streaming(uint8_t corenum, uint8_t *buffer, uint16_t packetsize,
      uint16_t totalpackets, uint16_t dummypackets);

/* Inline Functions: */

/* Function Prototypes: */
void Endpoint_ClearEndpoints(uint8_t corenum);

bool Endpoint_ConfigureEndpoint_Prv(uint8_t corenum,
         const uint8_t Number,
         const uint8_t UECFG0XData,
         const uint8_t UECFG1XData);

 #endif

/* Inline Functions: */
/*static inline */ bool Endpoint_ConfigureEndpoint(uint8_t corenum,
              const uint8_t Number,
               const uint8_t Type,
               const uint8_t Direction,
               const uint16_t Size,
               const uint8_t Banks) /*ATTR_ALWAYS_INLINE*/;

//          static inline bool Endpoint_ConfigureEndpoint(const uint8_t Number,
//                                                        const uint8_t Type,
//                                                        const uint8_t Direction,
//                                                        const uint16_t Size,
//                                                        const uint8_t Banks)
//          {
//              endpointhandle[Number] = HAL17XX_ConfigureEndpoint(Number,Type,Direction,Size,Banks);
//              return true;
//          }

static inline void Endpoint_ResetEndpoint(const uint8_t EndpointNumber) ATTR_ALWAYS_INLINE;

static inline void Endpoint_ResetEndpoint(const uint8_t EndpointNumber)
{}

static inline void Endpoint_EnableEndpoint(void) ATTR_ALWAYS_INLINE;

static inline void Endpoint_EnableEndpoint(void)
{}

static inline void Endpoint_DisableEndpoint(void) ATTR_ALWAYS_INLINE;

static inline void Endpoint_DisableEndpoint(void)
{}

static inline bool Endpoint_IsEnabled(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;

static inline bool Endpoint_IsEnabled(void)
{
 return true;
}

static inline uint8_t Endpoint_GetBusyBanks(void) ATTR_ALWAYS_INLINE ATTR_WARN_UNUSED_RESULT;

static inline uint8_t Endpoint_GetBusyBanks(void)
{
 return 0;
}

static inline void Endpoint_AbortPendingIN(void)
{}

static inline bool Endpoint_IsConfigured(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;

static inline bool Endpoint_IsConfigured(void)
{
 //    return ((UESTA0X & (1 << CFGOK)) ? true : false);
 return true;
}

static inline uint8_t Endpoint_GetEndpointInterrupts(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;

static inline uint8_t Endpoint_GetEndpointInterrupts(void)
{
 return 0;    // TODO not yet implemented
}

static inline bool Endpoint_HasEndpointInterrupted(const uint8_t EndpointNumber) ATTR_WARN_UNUSED_RESULT
ATTR_ALWAYS_INLINE;

static inline bool Endpoint_HasEndpointInterrupted(const uint8_t EndpointNumber)
{
 return (Endpoint_GetEndpointInterrupts() & (1 << EndpointNumber)) ? true : false;
}

static inline uint16_t Endpoint_BytesInEndpoint(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;

static inline uint16_t Endpoint_BytesInEndpoint(uint8_t corenum)
{
 // return usb_data_buffer_index;   // TODO not implemented yet
 // uint8_t PhyEP = (endpointselected==ENDPOINT_CONTROLEP ? 1: endpointhandle[endpointselected]);
 if (endpointselected[corenum] == ENDPOINT_CONTROLEP) {
  return usb_data_buffer_size[corenum];
 }
 else {
  return usb_data_buffer_OUT_size[corenum];
 }
}

static inline bool Endpoint_IsINReady(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;

static inline bool Endpoint_IsINReady(uint8_t corenum)
{
 uint8_t PhyEP = (endpointselected[corenum] == ENDPOINT_CONTROLEP ? 1 : endpointhandle(corenum)[endpointselected[corenum]]);
 return (dQueueHead[corenum][PhyEP].overlay.NextTD & LINK_TERMINATE) &&
     (dQueueHead[corenum][PhyEP].overlay.Active == 0);
}

static inline bool Endpoint_IsOUTReceived(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;

static inline bool Endpoint_IsOUTReceived(uint8_t corenum)
{
 //              return (dQueueHead[ endpointhandle[endpointselected] ].overlay.NextTD == LINK_TERMINATE &&
 //                      dQueueHead[ endpointhandle[endpointselected] ].overlay.Active == 0 );
 return dQueueHead[corenum][endpointhandle(corenum)[endpointselected[corenum]]].IsOutReceived ? true : false;    // TODO refractor IsOutReceived
}

static inline bool Endpoint_IsSETUPReceived(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;

static inline bool Endpoint_IsSETUPReceived(uint8_t corenum)
{
 return USB_REG(corenum)->ENDPTSETUPSTAT ? true : false;
}

static inline void Endpoint_ClearSETUP(uint8_t corenum) ATTR_ALWAYS_INLINE;

static inline void Endpoint_ClearSETUP(uint8_t corenum)
{
 IP_USBHS_001_T * USB_Reg = USB_REG(corenum);
 USB_Reg->ENDPTSETUPSTAT = USB_Reg->ENDPTSETUPSTAT;
 usb_data_buffer_index[corenum] = 0;
 USB_Reg->ENDPTNAKEN |= (1 << 0);
}

static inline void Endpoint_ClearIN(uint8_t corenum) ATTR_ALWAYS_INLINE;

static inline void Endpoint_ClearIN(uint8_t corenum)
{
 uint8_t PhyEP = endpointselected[corenum] == ENDPOINT_CONTROLEP ? 1 : (endpointhandle(corenum)[endpointselected[corenum]]);
 if (endpointselected[corenum] == ENDPOINT_CONTROLEP) {
  DcdDataTransfer(corenum, PhyEP, (uint8_t *)usb_data_buffer[corenum], usb_data_buffer_index[corenum]);
  usb_data_buffer_index[corenum] = 0;
 }
 else {
  DcdDataTransfer(corenum, PhyEP, usb_data_buffer_IN[corenum], usb_data_buffer_IN_index[corenum]);
  usb_data_buffer_IN_index[corenum] = 0;
 }
}

static inline void Endpoint_ClearOUT(uint8_t corenum) ATTR_ALWAYS_INLINE;

static inline void Endpoint_ClearOUT(uint8_t corenum)
{
 if (endpointselected[corenum] == ENDPOINT_CONTROLEP) {
  usb_data_buffer_index[corenum] = 0;
  dQueueHead[corenum][endpointhandle(corenum)[endpointselected[corenum]]].IsOutReceived = 0;
 }
 else {
  usb_data_buffer_OUT_index[corenum] = 0;
  dQueueHead[corenum][endpointhandle(corenum)[endpointselected[corenum]]].IsOutReceived = 0;
  USB_REG(corenum)->ENDPTNAKEN |= (1 << endpointselected[corenum]);
 }

}

static inline void Endpoint_StallTransaction(uint8_t corenum) ATTR_ALWAYS_INLINE;

static inline void Endpoint_StallTransaction(uint8_t corenum)
{
 ENDPTCTRL_REG(corenum, EP_Physical2Logical(endpointhandle(corenum)[endpointselected[corenum]]) ) |= ENDPTCTRL_RxStall | ENDPTCTRL_TxStall;
}

static inline void Endpoint_ClearStall(uint8_t corenum) ATTR_ALWAYS_INLINE;

static inline void Endpoint_ClearStall(uint8_t corenum)
{
 // === TODO: Only clear stall correct endpoint ===
 ENDPTCTRL_REG(corenum, EP_Physical2Logical(endpointhandle(corenum)[endpointselected[corenum]]) ) &= ~(ENDPTCTRL_RxStall | ENDPTCTRL_TxStall);
}

static inline bool Endpoint_IsStalled(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;

static inline bool Endpoint_IsStalled(uint8_t corenum)
{
 return ENDPTCTRL_REG(corenum, EP_Physical2Logical(endpointhandle(corenum)[endpointselected[corenum]]) ) &
     (ENDPTCTRL_RxStall | ENDPTCTRL_TxStall);
}

static inline void Endpoint_ResetDataToggle(uint8_t corenum) ATTR_ALWAYS_INLINE;

static inline void Endpoint_ResetDataToggle(uint8_t corenum)
{
 ENDPTCTRL_REG(corenum, EP_Physical2Logical(endpointhandle(corenum)[endpointselected[corenum]]) ) |= ENDPTCTRL_RxToggleReset |
                    ENDPTCTRL_TxToggleReset;
}

/* External Variables: */
   #if (!defined(FIXED_CONTROL_ENDPOINT_SIZE) || defined(__DOXYGEN__))
extern uint8_t USB_Device_ControlEndpointSize;
   #else
    #define USB_Device_ControlEndpointSize FIXED_CONTROL_ENDPOINT_SIZE
   #endif

/* Function Prototypes: */
void Endpoint_ClearStatusStage(uint8_t corenum);

uint8_t Endpoint_WaitUntilReady(void);

/* Disable C linkage for C++ Compilers: */
  #if defined(__cplusplus)
}
  #endif

#endif