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cpu.h
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1 /*
2 *********************************************************************************************************
3 * uC/CPU
4 * CPU CONFIGURATION & PORT LAYER
5 *
6 * (c) Copyright 2004-2011; Micrium, Inc.; Weston, FL
7 *
8 * All rights reserved. Protected by international copyright laws.
9 *
10 * uC/CPU is provided in source form to registered licensees ONLY. It is
11 * illegal to distribute this source code to any third party unless you receive
12 * written permission by an authorized Micrium representative. Knowledge of
13 * the source code may NOT be used to develop a similar product.
14 *
15 * Please help us continue to provide the Embedded community with the finest
16 * software available. Your honesty is greatly appreciated.
17 *
18 * You can contact us at www.micrium.com.
19 *********************************************************************************************************
20 */
21 
22 /*
23 *********************************************************************************************************
24 *
25 * CPU PORT FILE
26 *
27 * ARM-Cortex-M3
28 * RealView Development Suite
29 * RealView Microcontroller Development Kit (MDK)
30 * ARM Developer Suite (ADS)
31 * Keil uVision
32 *
33 * Filename : cpu.h
34 * Version : V1.28.00.00
35 * Programmer(s) : JJL
36 * BAN
37 *********************************************************************************************************
38 */
39 
40 
41 /*
42 *********************************************************************************************************
43 * MODULE
44 *********************************************************************************************************
45 */
46 
47 #ifndef CPU_MODULE_PRESENT
48 #define CPU_MODULE_PRESENT
49 
50 
51 /*
52 *********************************************************************************************************
53 * CPU INCLUDE FILES
54 *
55 * Note(s) : (1) The following CPU files are located in the following directories :
56 *
57 * (a) <Your Product Application>\cpu_cfg.h
58 *
59 * (b) <CPU-Compiler Directory>\cpu_def.h
60 *
61 * (c) <CPU-Compiler Directory><cpu><compiler>\cpu*.*
62 *
63 * where
64 * <Your Product Application> directory path for Your Product's Application
65 * <CPU-Compiler Directory> directory path for common CPU-compiler software
66 * <cpu> directory name for specific CPU
67 * <compiler> directory name for specific compiler
68 *
69 * (2) Compiler MUST be configured to include the '<CPU-Compiler Directory>\' directory the
70 * specific CPU-compiler directory, & '<Your Product Application>\' as additional include
71 * path directories.
72 *
73 * (3) Since NO custom library modules are included, 'cpu.h' may ONLY use configurations from
74 * CPU configuration file 'cpu_cfg.h' that do NOT reference any custom library definitions.
75 *
76 * In other words, 'cpu.h' may use 'cpu_cfg.h' configurations that are #define'd to numeric
77 * constants or to NULL (i.e. NULL-valued #define's); but may NOT use configurations to
78 * custom library #define's (e.g. DEF_DISABLED or DEF_ENABLED).
79 *********************************************************************************************************
80 */
81 
82 #include <cpu_def.h>
83 #include <cpu_cfg.h> /* See Note #3. */
84 
85 
86 /*$PAGE*/
87 /*
88 *********************************************************************************************************
89 * CONFIGURE STANDARD DATA TYPES
90 *
91 * Note(s) : (1) Configure standard data types according to CPU-/compiler-specifications.
92 *
93 * (2) (a) (1) 'CPU_FNCT_VOID' data type defined to replace the commonly-used function pointer
94 * data type of a pointer to a function which returns void & has no arguments.
95 *
96 * (2) Example function pointer usage :
97 *
98 * CPU_FNCT_VOID FnctName;
99 *
100 * FnctName();
101 *
102 * (b) (1) 'CPU_FNCT_PTR' data type defined to replace the commonly-used function pointer
103 * data type of a pointer to a function which returns void & has a single void
104 * pointer argument.
105 *
106 * (2) Example function pointer usage :
107 *
108 * CPU_FNCT_PTR FnctName;
109 * void *p_obj
110 *
111 * FnctName(p_obj);
112 *********************************************************************************************************
113 */
114 
115 typedef void CPU_VOID;
116 typedef char CPU_CHAR; /* 8-bit character */
117 typedef unsigned char CPU_BOOLEAN; /* 8-bit boolean or logical */
118 typedef unsigned char CPU_INT08U; /* 8-bit unsigned integer */
119 typedef signed char CPU_INT08S; /* 8-bit signed integer */
120 typedef unsigned short CPU_INT16U; /* 16-bit unsigned integer */
121 typedef signed short CPU_INT16S; /* 16-bit signed integer */
122 typedef unsigned int CPU_INT32U; /* 32-bit unsigned integer */
123 typedef signed int CPU_INT32S; /* 32-bit signed integer */
124 typedef unsigned long long CPU_INT64U; /* 64-bit unsigned integer */
125 typedef signed long long CPU_INT64S; /* 64-bit signed integer */
126 
127 typedef float CPU_FP32; /* 32-bit floating point */
128 typedef double CPU_FP64; /* 64-bit floating point */
129 
130 
131 typedef volatile CPU_INT08U CPU_REG08; /* 8-bit register */
132 typedef volatile CPU_INT16U CPU_REG16; /* 16-bit register */
133 typedef volatile CPU_INT32U CPU_REG32; /* 32-bit register */
134 typedef volatile CPU_INT64U CPU_REG64; /* 64-bit register */
135 
136 
137 typedef void (*CPU_FNCT_VOID)(void); /* See Note #2a. */
138 typedef void (*CPU_FNCT_PTR )(void *p_obj); /* See Note #2b. */
139 
140 
141 /*$PAGE*/
142 /*
143 *********************************************************************************************************
144 * CPU WORD CONFIGURATION
145 *
146 * Note(s) : (1) Configure CPU_CFG_ADDR_SIZE & CPU_CFG_DATA_SIZE with CPU's word sizes :
147 *
148 * CPU_WORD_SIZE_08 8-bit word size
149 * CPU_WORD_SIZE_16 16-bit word size
150 * CPU_WORD_SIZE_32 32-bit word size
151 * CPU_WORD_SIZE_64 64-bit word size See Note #1a
152 *
153 * (a) 64-bit word size NOT currently supported.
154 *
155 * (2) Configure CPU_CFG_ENDIAN_TYPE with CPU's data-word-memory order :
156 *
157 * (a) CPU_ENDIAN_TYPE_BIG Big- endian word order (CPU words' most significant
158 * octet @ lowest memory address)
159 * (b) CPU_ENDIAN_TYPE_LITTLE Little-endian word order (CPU words' least significant
160 * octet @ lowest memory address)
161 *********************************************************************************************************
162 */
163 
164  /* Define CPU word sizes (see Note #1) : */
165 #define CPU_CFG_ADDR_SIZE CPU_WORD_SIZE_32 /* Defines CPU address word size (in octets). */
166 #define CPU_CFG_DATA_SIZE CPU_WORD_SIZE_32 /* Defines CPU data word size (in octets). */
167 
168 #define CPU_CFG_ENDIAN_TYPE CPU_ENDIAN_TYPE_LITTLE /* Defines CPU data word-memory order (see Note #2). */
169 
170 
171 /*
172 *********************************************************************************************************
173 * CONFIGURE CPU ADDRESS & DATA TYPES
174 *********************************************************************************************************
175 */
176 
177  /* CPU address type based on address bus size. */
178 #if (CPU_CFG_ADDR_SIZE == CPU_WORD_SIZE_32)
179 typedef CPU_INT32U CPU_ADDR;
180 #elif (CPU_CFG_ADDR_SIZE == CPU_WORD_SIZE_16)
181 typedef CPU_INT16U CPU_ADDR;
182 #else
183 typedef CPU_INT08U CPU_ADDR;
184 #endif
185 
186  /* CPU data type based on data bus size. */
187 #if (CPU_CFG_DATA_SIZE == CPU_WORD_SIZE_32)
188 typedef CPU_INT32U CPU_DATA;
189 #elif (CPU_CFG_DATA_SIZE == CPU_WORD_SIZE_16)
190 typedef CPU_INT16U CPU_DATA;
191 #else
192 typedef CPU_INT08U CPU_DATA;
193 #endif
194 
195 
196 typedef CPU_DATA CPU_ALIGN; /* Defines CPU data-word-alignment size. */
197 typedef CPU_ADDR CPU_SIZE_T; /* Defines CPU standard 'size_t' size. */
198 
199 
200 /*
201 *********************************************************************************************************
202 * CPU STACK CONFIGURATION
203 *
204 * Note(s) : (1) Configure CPU_CFG_STK_GROWTH in 'cpu.h' with CPU's stack growth order :
205 *
206 * (a) CPU_STK_GROWTH_LO_TO_HI CPU stack pointer increments to the next higher stack
207 * memory address after data is pushed onto the stack
208 * (b) CPU_STK_GROWTH_HI_TO_LO CPU stack pointer decrements to the next lower stack
209 * memory address after data is pushed onto the stack
210 *********************************************************************************************************
211 */
212 
213 #define CPU_CFG_STK_GROWTH CPU_STK_GROWTH_HI_TO_LO /* Defines CPU stack growth order (see Note #1). */
214 
215 typedef CPU_INT32U CPU_STK; /* Defines CPU stack word size (in octets). */
216 typedef CPU_ADDR CPU_STK_SIZE; /* Defines CPU stack size (in number of CPU_STKs). */
217 
218 
219 /*$PAGE*/
220 /*
221 *********************************************************************************************************
222 * CRITICAL SECTION CONFIGURATION
223 *
224 * Note(s) : (1) Configure CPU_CFG_CRITICAL_METHOD with CPU's/compiler's critical section method :
225 *
226 * Enter/Exit critical sections by ...
227 *
228 * CPU_CRITICAL_METHOD_INT_DIS_EN Disable/Enable interrupts
229 * CPU_CRITICAL_METHOD_STATUS_STK Push/Pop interrupt status onto stack
230 * CPU_CRITICAL_METHOD_STATUS_LOCAL Save/Restore interrupt status to local variable
231 *
232 * (a) CPU_CRITICAL_METHOD_INT_DIS_EN is NOT a preferred method since it does NOT support
233 * multiple levels of interrupts. However, with some CPUs/compilers, this is the only
234 * available method.
235 *
236 * (b) CPU_CRITICAL_METHOD_STATUS_STK is one preferred method since it supports multiple
237 * levels of interrupts. However, this method assumes that the compiler provides C-level
238 * &/or assembly-level functionality for the following :
239 *
240 * ENTER CRITICAL SECTION :
241 * (1) Push/save interrupt status onto a local stack
242 * (2) Disable interrupts
243 *
244 * EXIT CRITICAL SECTION :
245 * (3) Pop/restore interrupt status from a local stack
246 *
247 * (c) CPU_CRITICAL_METHOD_STATUS_LOCAL is one preferred method since it supports multiple
248 * levels of interrupts. However, this method assumes that the compiler provides C-level
249 * &/or assembly-level functionality for the following :
250 *
251 * ENTER CRITICAL SECTION :
252 * (1) Save interrupt status into a local variable
253 * (2) Disable interrupts
254 *
255 * EXIT CRITICAL SECTION :
256 * (3) Restore interrupt status from a local variable
257 *
258 * (2) Critical section macro's most likely require inline assembly. If the compiler does NOT
259 * allow inline assembly in C source files, critical section macro's MUST call an assembly
260 * subroutine defined in a 'cpu_a.asm' file located in the following software directory :
261 *
262 * <CPU-Compiler Directory><cpu><compiler>\
263 *
264 * where
265 * <CPU-Compiler Directory> directory path for common CPU-compiler software
266 * <cpu> directory name for specific CPU
267 * <compiler> directory name for specific compiler
268 *
269 * (3) (a) To save/restore interrupt status, a local variable 'cpu_sr' of type 'CPU_SR' MAY need
270 * to be declared (e.g. if 'CPU_CRITICAL_METHOD_STATUS_LOCAL' method is configured).
271 *
272 * (1) 'cpu_sr' local variable SHOULD be declared via the CPU_SR_ALLOC() macro which, if
273 * used, MUST be declared following ALL other local variables.
274 *
275 * Example :
276 *
277 * void Fnct (void)
278 * {
279 * CPU_INT08U val_08;
280 * CPU_INT16U val_16;
281 * CPU_INT32U val_32;
282 * CPU_SR_ALLOC(); MUST be declared after ALL other local variables
283 * :
284 * :
285 * }
286 *
287 * (b) Configure 'CPU_SR' data type with the appropriate-sized CPU data type large enough to
288 * completely store the CPU's/compiler's status word.
289 *********************************************************************************************************
290 */
291 /*$PAGE*/
292  /* Configure CPU critical method (see Note #1) : */
293 #define CPU_CFG_CRITICAL_METHOD CPU_CRITICAL_METHOD_STATUS_LOCAL
294 
295 typedef CPU_INT32U CPU_SR; /* Defines CPU status register size (see Note #3b). */
296 
297  /* Allocates CPU status register word (see Note #3a). */
298 #if (CPU_CFG_CRITICAL_METHOD == CPU_CRITICAL_METHOD_STATUS_LOCAL)
299 #define CPU_SR_ALLOC() CPU_SR cpu_sr = (CPU_SR)0
300 #else
301 #define CPU_SR_ALLOC()
302 #endif
303 
304 
305 
306 #define CPU_INT_DIS() do { cpu_sr = CPU_SR_Save(); } while (0) /* Save CPU status word & disable interrupts.*/
307 #define CPU_INT_EN() do { CPU_SR_Restore(cpu_sr); } while (0) /* Restore CPU status word. */
308 
309 
310 #ifdef CPU_CFG_INT_DIS_MEAS_EN
311  /* Disable interrupts, ... */
312  /* & start interrupts disabled time measurement.*/
313 #define CPU_CRITICAL_ENTER() do { CPU_INT_DIS(); \
314  CPU_IntDisMeasStart(); } while (0)
315  /* Stop & measure interrupts disabled time, */
316  /* ... & re-enable interrupts. */
317 #define CPU_CRITICAL_EXIT() do { CPU_IntDisMeasStop(); \
318  CPU_INT_EN(); } while (0)
319 
320 #else
321 
322 #define CPU_CRITICAL_ENTER() do { CPU_INT_DIS(); } while (0) /* Disable interrupts. */
323 #define CPU_CRITICAL_EXIT() do { CPU_INT_EN(); } while (0) /* Re-enable interrupts. */
324 
325 #endif
326 
327 
328 /*$PAGE*/
329 /*
330 *********************************************************************************************************
331 * FUNCTION PROTOTYPES
332 *
333 * Note(s) : (1) CPU_CntLeadZeros() prototyped/defined respectively in :
334 *
335 * (a) 'cpu.h'/'cpu_a.asm', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT #define'd in 'cpu.h'/
336 * 'cpu_cfg.h' to enable assembly-version function
337 *
338 * (b) 'cpu_core.h'/'cpu_core.c', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT NOT #define'd in 'cpu.h'/
339 * 'cpu_cfg.h' to enable C-source-version function otherwise
340 *
341 * See also 'cpu_core.h FUNCTION PROTOTYPES Note #2'.
342 *********************************************************************************************************
343 */
344 
345 void CPU_IntDis (void);
346 void CPU_IntEn (void);
347 
348 void CPU_IntSrcDis (CPU_INT08U pos);
349 void CPU_IntSrcEn (CPU_INT08U pos);
350 void CPU_IntSrcPendClr(CPU_INT08U pos);
351 CPU_INT16S CPU_IntSrcPrioGet(CPU_INT08U pos);
352 void CPU_IntSrcPrioSet(CPU_INT08U pos,
353  CPU_INT08U prio);
354 
355 
356 CPU_SR CPU_SR_Save (void);
357 void CPU_SR_Restore (CPU_SR cpu_sr);
358 
359 
360 #define CPU_CFG_LEAD_ZEROS_ASM_PRESENT /* See Note #1. */
361 
362 CPU_DATA CPU_CntLeadZeros (CPU_DATA val);
363 CPU_DATA CPU_RevBits (CPU_DATA val);
364 
365 
366 void CPU_WaitForInt (void);
367 void CPU_WaitForExcept(void);
368 
369 
370 void CPU_BitBandClr (CPU_ADDR addr,
371  CPU_INT08U bit_nbr);
372 void CPU_BitBandSet (CPU_ADDR addr,
373  CPU_INT08U bit_nbr);
374 
375 
376 /*$PAGE*/
377 /*
378 *********************************************************************************************************
379 * INTERRUPT SOURCES
380 *********************************************************************************************************
381 */
382 
383 #define CPU_INT_STK_PTR 0u
384 #define CPU_INT_RESET 1u
385 #define CPU_INT_NMI 2u
386 #define CPU_INT_HFAULT 3u
387 #define CPU_INT_MEM 4u
388 #define CPU_INT_BUSFAULT 5u
389 #define CPU_INT_USAGEFAULT 6u
390 #define CPU_INT_RSVD_07 7u
391 #define CPU_INT_RSVD_08 8u
392 #define CPU_INT_RSVD_09 9u
393 #define CPU_INT_RSVD_10 10u
394 #define CPU_INT_SVCALL 11u
395 #define CPU_INT_DBGMON 12u
396 #define CPU_INT_RSVD_13 13u
397 #define CPU_INT_PENDSV 14u
398 #define CPU_INT_SYSTICK 15u
399 #define CPU_INT_EXT0 16u
400 
401 
402 /*
403 *********************************************************************************************************
404 * CPU REGISTERS
405 *********************************************************************************************************
406 */
407 
408 #define CPU_REG_NVIC_NVIC (*((CPU_REG32 *)(0xE000E004))) /* Int Ctrl'er Type Reg. */
409 #define CPU_REG_NVIC_ST_CTRL (*((CPU_REG32 *)(0xE000E010))) /* SysTick Ctrl & Status Reg. */
410 #define CPU_REG_NVIC_ST_RELOAD (*((CPU_REG32 *)(0xE000E014))) /* SysTick Reload Value Reg. */
411 #define CPU_REG_NVIC_ST_CURRENT (*((CPU_REG32 *)(0xE000E018))) /* SysTick Current Value Reg. */
412 #define CPU_REG_NVIC_ST_CAL (*((CPU_REG32 *)(0xE000E01C))) /* SysTick Calibration Value Reg. */
413 
414 #define CPU_REG_NVIC_SETEN(n) (*((CPU_REG32 *)(0xE000E100 + (n) * 4u))) /* IRQ Set En Reg. */
415 #define CPU_REG_NVIC_CLREN(n) (*((CPU_REG32 *)(0xE000E180 + (n) * 4u))) /* IRQ Clr En Reg. */
416 #define CPU_REG_NVIC_SETPEND(n) (*((CPU_REG32 *)(0xE000E200 + (n) * 4u))) /* IRQ Set Pending Reg. */
417 #define CPU_REG_NVIC_CLRPEND(n) (*((CPU_REG32 *)(0xE000E280 + (n) * 4u))) /* IRQ Clr Pending Reg. */
418 #define CPU_REG_NVIC_ACTIVE(n) (*((CPU_REG32 *)(0xE000E300 + (n) * 4u))) /* IRQ Active Reg. */
419 #define CPU_REG_NVIC_PRIO(n) (*((CPU_REG32 *)(0xE000E400 + (n) * 4u))) /* IRQ Prio Reg. */
420 
421 #define CPU_REG_NVIC_CPUID (*((CPU_REG32 *)(0xE000ED00))) /* CPUID Base Reg. */
422 #define CPU_REG_NVIC_ICSR (*((CPU_REG32 *)(0xE000ED04))) /* Int Ctrl State Reg. */
423 #define CPU_REG_NVIC_VTOR (*((CPU_REG32 *)(0xE000ED08))) /* Vect Tbl Offset Reg. */
424 #define CPU_REG_NVIC_AIRCR (*((CPU_REG32 *)(0xE000ED0C))) /* App Int/Reset Ctrl Reg. */
425 #define CPU_REG_NVIC_SCR (*((CPU_REG32 *)(0xE000ED10))) /* System Ctrl Reg. */
426 #define CPU_REG_NVIC_CCR (*((CPU_REG32 *)(0xE000ED14))) /* Cfg Ctrl Reg. */
427 #define CPU_REG_NVIC_SHPRI1 (*((CPU_REG32 *)(0xE000ED18))) /* System Handlers 4 to 7 Prio. */
428 #define CPU_REG_NVIC_SHPRI2 (*((CPU_REG32 *)(0xE000ED1C))) /* System Handlers 8 to 11 Prio. */
429 #define CPU_REG_NVIC_SHPRI3 (*((CPU_REG32 *)(0xE000ED20))) /* System Handlers 12 to 15 Prio. */
430 #define CPU_REG_NVIC_SHCSR (*((CPU_REG32 *)(0xE000ED24))) /* System Handler Ctrl & State Reg. */
431 #define CPU_REG_NVIC_CFSR (*((CPU_REG32 *)(0xE000ED28))) /* Configurable Fault Status Reg. */
432 #define CPU_REG_NVIC_HFSR (*((CPU_REG32 *)(0xE000ED2C))) /* Hard Fault Status Reg. */
433 #define CPU_REG_NVIC_DFSR (*((CPU_REG32 *)(0xE000ED30))) /* Debug Fault Status Reg. */
434 #define CPU_REG_NVIC_MMFAR (*((CPU_REG32 *)(0xE000ED34))) /* Mem Manage Addr Reg. */
435 #define CPU_REG_NVIC_BFAR (*((CPU_REG32 *)(0xE000ED38))) /* Bus Fault Addr Reg. */
436 #define CPU_REG_NVIC_AFSR (*((CPU_REG32 *)(0xE000ED3C))) /* Aux Fault Status Reg. */
437 
438 #define CPU_REG_NVIC_PFR0 (*((CPU_REG32 *)(0xE000ED40))) /* Processor Feature Reg 0. */
439 #define CPU_REG_NVIC_PFR1 (*((CPU_REG32 *)(0xE000ED44))) /* Processor Feature Reg 1. */
440 #define CPU_REG_NVIC_DFR0 (*((CPU_REG32 *)(0xE000ED48))) /* Debug Feature Reg 0. */
441 #define CPU_REG_NVIC_AFR0 (*((CPU_REG32 *)(0xE000ED4C))) /* Aux Feature Reg 0. */
442 #define CPU_REG_NVIC_MMFR0 (*((CPU_REG32 *)(0xE000ED50))) /* Memory Model Feature Reg 0. */
443 #define CPU_REG_NVIC_MMFR1 (*((CPU_REG32 *)(0xE000ED54))) /* Memory Model Feature Reg 1. */
444 #define CPU_REG_NVIC_MMFR2 (*((CPU_REG32 *)(0xE000ED58))) /* Memory Model Feature Reg 2. */
445 #define CPU_REG_NVIC_MMFR3 (*((CPU_REG32 *)(0xE000ED5C))) /* Memory Model Feature Reg 3. */
446 #define CPU_REG_NVIC_ISAFR0 (*((CPU_REG32 *)(0xE000ED60))) /* ISA Feature Reg 0. */
447 #define CPU_REG_NVIC_ISAFR1 (*((CPU_REG32 *)(0xE000ED64))) /* ISA Feature Reg 1. */
448 #define CPU_REG_NVIC_ISAFR2 (*((CPU_REG32 *)(0xE000ED68))) /* ISA Feature Reg 2. */
449 #define CPU_REG_NVIC_ISAFR3 (*((CPU_REG32 *)(0xE000ED6C))) /* ISA Feature Reg 3. */
450 #define CPU_REG_NVIC_ISAFR4 (*((CPU_REG32 *)(0xE000ED70))) /* ISA Feature Reg 4. */
451 #define CPU_REG_NVIC_SW_TRIG (*((CPU_REG32 *)(0xE000EF00))) /* Software Trigger Int Reg. */
452 
453 #define CPU_REG_MPU_TYPE (*((CPU_REG32 *)(0xE000ED90))) /* MPU Type Reg. */
454 #define CPU_REG_MPU_CTRL (*((CPU_REG32 *)(0xE000ED94))) /* MPU Ctrl Reg. */
455 #define CPU_REG_MPU_REG_NBR (*((CPU_REG32 *)(0xE000ED98))) /* MPU Region Nbr Reg. */
456 #define CPU_REG_MPU_REG_BASE (*((CPU_REG32 *)(0xE000ED9C))) /* MPU Region Base Addr Reg. */
457 #define CPU_REG_MPU_REG_ATTR (*((CPU_REG32 *)(0xE000EDA0))) /* MPU Region Attrib & Size Reg. */
458 
459 #define CPU_REG_DBG_CTRL (*((CPU_REG32 *)(0xE000EDF0))) /* Debug Halting Ctrl & Status Reg. */
460 #define CPU_REG_DBG_SELECT (*((CPU_REG32 *)(0xE000EDF4))) /* Debug Core Reg Selector Reg. */
461 #define CPU_REG_DBG_DATA (*((CPU_REG32 *)(0xE000EDF8))) /* Debug Core Reg Data Reg. */
462 #define CPU_REG_DBG_INT (*((CPU_REG32 *)(0xE000EDFC))) /* Debug Except & Monitor Ctrl Reg. */
463 
464 
465 /*$PAGE*/
466 /*
467 *********************************************************************************************************
468 * CPU REGISTER BITS
469 *********************************************************************************************************
470 */
471 
472  /* ---------- SYSTICK CTRL & STATUS REG BITS ---------- */
473 #define CPU_REG_NVIC_ST_CTRL_COUNTFLAG 0x00010000
474 #define CPU_REG_NVIC_ST_CTRL_CLKSOURCE 0x00000004
475 #define CPU_REG_NVIC_ST_CTRL_TICKINT 0x00000002
476 #define CPU_REG_NVIC_ST_CTRL_ENABLE 0x00000001
477 
478 
479  /* -------- SYSTICK CALIBRATION VALUE REG BITS -------- */
480 #define CPU_REG_NVIC_ST_CAL_NOREF 0x80000000
481 #define CPU_REG_NVIC_ST_CAL_SKEW 0x40000000
482 
483  /* -------------- INT CTRL STATE REG BITS ------------- */
484 #define CPU_REG_NVIC_ICSR_NMIPENDSET 0x80000000
485 #define CPU_REG_NVIC_ICSR_PENDSVSET 0x10000000
486 #define CPU_REG_NVIC_ICSR_PENDSVCLR 0x08000000
487 #define CPU_REG_NVIC_ICSR_PENDSTSET 0x04000000
488 #define CPU_REG_NVIC_ICSR_PENDSTCLR 0x02000000
489 #define CPU_REG_NVIC_ICSR_ISRPREEMPT 0x00800000
490 #define CPU_REG_NVIC_ICSR_ISRPENDING 0x00400000
491 #define CPU_REG_NVIC_ICSR_RETTOBASE 0x00000800
492 
493  /* ------------- VECT TBL OFFSET REG BITS ------------- */
494 #define CPU_REG_NVIC_VTOR_TBLBASE 0x20000000
495 
496  /* ------------ APP INT/RESET CTRL REG BITS ----------- */
497 #define CPU_REG_NVIC_AIRCR_ENDIANNESS 0x00008000
498 #define CPU_REG_NVIC_AIRCR_SYSRESETREQ 0x00000004
499 #define CPU_REG_NVIC_AIRCR_VECTCLRACTIVE 0x00000002
500 #define CPU_REG_NVIC_AIRCR_VECTRESET 0x00000001
501 
502  /* --------------- SYSTEM CTRL REG BITS --------------- */
503 #define CPU_REG_NVIC_SCR_SEVONPEND 0x00000010
504 #define CPU_REG_NVIC_SCR_SLEEPDEEP 0x00000004
505 #define CPU_REG_NVIC_SCR_SLEEPONEXIT 0x00000002
506 
507  /* ----------------- CFG CTRL REG BITS ---------------- */
508 #define CPU_REG_NVIC_CCR_STKALIGN 0x00000200
509 #define CPU_REG_NVIC_CCR_BFHFNMIGN 0x00000100
510 #define CPU_REG_NVIC_CCR_DIV_0_TRP 0x00000010
511 #define CPU_REG_NVIC_CCR_UNALIGN_TRP 0x00000008
512 #define CPU_REG_NVIC_CCR_USERSETMPEND 0x00000002
513 #define CPU_REG_NVIC_CCR_NONBASETHRDENA 0x00000001
514 
515  /* ------- SYSTEM HANDLER CTRL & STATE REG BITS ------- */
516 #define CPU_REG_NVIC_SHCSR_USGFAULTENA 0x00040000
517 #define CPU_REG_NVIC_SHCSR_BUSFAULTENA 0x00020000
518 #define CPU_REG_NVIC_SHCSR_MEMFAULTENA 0x00010000
519 #define CPU_REG_NVIC_SHCSR_SVCALLPENDED 0x00008000
520 #define CPU_REG_NVIC_SHCSR_BUSFAULTPENDED 0x00004000
521 #define CPU_REG_NVIC_SHCSR_MEMFAULTPENDED 0x00002000
522 #define CPU_REG_NVIC_SHCSR_USGFAULTPENDED 0x00001000
523 #define CPU_REG_NVIC_SHCSR_SYSTICKACT 0x00000800
524 #define CPU_REG_NVIC_SHCSR_PENDSVACT 0x00000400
525 #define CPU_REG_NVIC_SHCSR_MONITORACT 0x00000100
526 #define CPU_REG_NVIC_SHCSR_SVCALLACT 0x00000080
527 #define CPU_REG_NVIC_SHCSR_USGFAULTACT 0x00000008
528 #define CPU_REG_NVIC_SHCSR_BUSFAULTACT 0x00000002
529 #define CPU_REG_NVIC_SHCSR_MEMFAULTACT 0x00000001
530 
531  /* -------- CONFIGURABLE FAULT STATUS REG BITS -------- */
532 #define CPU_REG_NVIC_CFSR_DIVBYZERO 0x02000000
533 #define CPU_REG_NVIC_CFSR_UNALIGNED 0x01000000
534 #define CPU_REG_NVIC_CFSR_NOCP 0x00080000
535 #define CPU_REG_NVIC_CFSR_INVPC 0x00040000
536 #define CPU_REG_NVIC_CFSR_INVSTATE 0x00020000
537 #define CPU_REG_NVIC_CFSR_UNDEFINSTR 0x00010000
538 #define CPU_REG_NVIC_CFSR_BFARVALID 0x00008000
539 #define CPU_REG_NVIC_CFSR_STKERR 0x00001000
540 #define CPU_REG_NVIC_CFSR_UNSTKERR 0x00000800
541 #define CPU_REG_NVIC_CFSR_IMPRECISERR 0x00000400
542 #define CPU_REG_NVIC_CFSR_PRECISERR 0x00000200
543 #define CPU_REG_NVIC_CFSR_IBUSERR 0x00000100
544 #define CPU_REG_NVIC_CFSR_MMARVALID 0x00000080
545 #define CPU_REG_NVIC_CFSR_MSTKERR 0x00000010
546 #define CPU_REG_NVIC_CFSR_MUNSTKERR 0x00000008
547 #define CPU_REG_NVIC_CFSR_DACCVIOL 0x00000002
548 #define CPU_REG_NVIC_CFSR_IACCVIOL 0x00000001
549 
550  /* ------------ HARD FAULT STATUS REG BITS ------------ */
551 #define CPU_REG_NVIC_HFSR_DEBUGEVT 0x80000000
552 #define CPU_REG_NVIC_HFSR_FORCED 0x40000000
553 #define CPU_REG_NVIC_HFSR_VECTTBL 0x00000002
554 
555  /* ------------ DEBUG FAULT STATUS REG BITS ----------- */
556 #define CPU_REG_NVIC_DFSR_EXTERNAL 0x00000010
557 #define CPU_REG_NVIC_DFSR_VCATCH 0x00000008
558 #define CPU_REG_NVIC_DFSR_DWTTRAP 0x00000004
559 #define CPU_REG_NVIC_DFSR_BKPT 0x00000002
560 #define CPU_REG_NVIC_DFSR_HALTED 0x00000001
561 
562 
563 /*
564 *********************************************************************************************************
565 * CPU REGISTER MASK
566 *********************************************************************************************************
567 */
568 
569 #define CPU_MSK_NVIC_ICSR_VECT_ACTIVE 0x000001FF
570 
571 
572 /*$PAGE*/
573 /*
574 *********************************************************************************************************
575 * CONFIGURATION ERRORS
576 *********************************************************************************************************
577 */
578 
579 #ifndef CPU_CFG_ADDR_SIZE
580 #error "CPU_CFG_ADDR_SIZE not #define'd in 'cpu.h' "
581 #error " [MUST be CPU_WORD_SIZE_08 8-bit alignment]"
582 #error " [ || CPU_WORD_SIZE_16 16-bit alignment]"
583 #error " [ || CPU_WORD_SIZE_32 32-bit alignment]"
584 
585 #elif ((CPU_CFG_ADDR_SIZE != CPU_WORD_SIZE_08) && \
586  (CPU_CFG_ADDR_SIZE != CPU_WORD_SIZE_16) && \
587  (CPU_CFG_ADDR_SIZE != CPU_WORD_SIZE_32))
588 #error "CPU_CFG_ADDR_SIZE illegally #define'd in 'cpu.h' "
589 #error " [MUST be CPU_WORD_SIZE_08 8-bit alignment]"
590 #error " [ || CPU_WORD_SIZE_16 16-bit alignment]"
591 #error " [ || CPU_WORD_SIZE_32 32-bit alignment]"
592 #endif
593 
594 
595 #ifndef CPU_CFG_DATA_SIZE
596 #error "CPU_CFG_DATA_SIZE not #define'd in 'cpu.h' "
597 #error " [MUST be CPU_WORD_SIZE_08 8-bit alignment]"
598 #error " [ || CPU_WORD_SIZE_16 16-bit alignment]"
599 #error " [ || CPU_WORD_SIZE_32 32-bit alignment]"
600 
601 #elif ((CPU_CFG_DATA_SIZE != CPU_WORD_SIZE_08) && \
602  (CPU_CFG_DATA_SIZE != CPU_WORD_SIZE_16) && \
603  (CPU_CFG_DATA_SIZE != CPU_WORD_SIZE_32))
604 #error "CPU_CFG_DATA_SIZE illegally #define'd in 'cpu.h' "
605 #error " [MUST be CPU_WORD_SIZE_08 8-bit alignment]"
606 #error " [ || CPU_WORD_SIZE_16 16-bit alignment]"
607 #error " [ || CPU_WORD_SIZE_32 32-bit alignment]"
608 #endif
609 
610 
611 
612 
613 #ifndef CPU_CFG_ENDIAN_TYPE
614 #error "CPU_CFG_ENDIAN_TYPE not #define'd in 'cpu.h' "
615 #error " [MUST be CPU_ENDIAN_TYPE_BIG ]"
616 #error " [ || CPU_ENDIAN_TYPE_LITTLE]"
617 
618 #elif ((CPU_CFG_ENDIAN_TYPE != CPU_ENDIAN_TYPE_BIG ) && \
619  (CPU_CFG_ENDIAN_TYPE != CPU_ENDIAN_TYPE_LITTLE))
620 #error "CPU_CFG_ENDIAN_TYPE illegally #define'd in 'cpu.h' "
621 #error " [MUST be CPU_ENDIAN_TYPE_BIG ]"
622 #error " [ || CPU_ENDIAN_TYPE_LITTLE]"
623 #endif
624 
625 
626 
627 
628 #ifndef CPU_CFG_STK_GROWTH
629 #error "CPU_CFG_STK_GROWTH not #define'd in 'cpu.h' "
630 #error " [MUST be CPU_STK_GROWTH_LO_TO_HI]"
631 #error " [ || CPU_STK_GROWTH_HI_TO_LO]"
632 
633 #elif ((CPU_CFG_STK_GROWTH != CPU_STK_GROWTH_LO_TO_HI) && \
634  (CPU_CFG_STK_GROWTH != CPU_STK_GROWTH_HI_TO_LO))
635 #error "CPU_CFG_STK_GROWTH illegally #define'd in 'cpu.h' "
636 #error " [MUST be CPU_STK_GROWTH_LO_TO_HI]"
637 #error " [ || CPU_STK_GROWTH_HI_TO_LO]"
638 #endif
639 
640 
641 
642 
643 #ifndef CPU_CFG_CRITICAL_METHOD
644 #error "CPU_CFG_CRITICAL_METHOD not #define'd in 'cpu.h' "
645 #error " [MUST be CPU_CRITICAL_METHOD_INT_DIS_EN ]"
646 #error " [ || CPU_CRITICAL_METHOD_STATUS_STK ]"
647 #error " [ || CPU_CRITICAL_METHOD_STATUS_LOCAL]"
648 
649 #elif ((CPU_CFG_CRITICAL_METHOD != CPU_CRITICAL_METHOD_INT_DIS_EN ) && \
650  (CPU_CFG_CRITICAL_METHOD != CPU_CRITICAL_METHOD_STATUS_STK ) && \
651  (CPU_CFG_CRITICAL_METHOD != CPU_CRITICAL_METHOD_STATUS_LOCAL))
652 #error "CPU_CFG_CRITICAL_METHOD illegally #define'd in 'cpu.h' "
653 #error " [MUST be CPU_CRITICAL_METHOD_INT_DIS_EN ]"
654 #error " [ || CPU_CRITICAL_METHOD_STATUS_STK ]"
655 #error " [ || CPU_CRITICAL_METHOD_STATUS_LOCAL]"
656 #endif
657 
658 
659 /*$PAGE*/
660 /*
661 *********************************************************************************************************
662 * MODULE END
663 *********************************************************************************************************
664 */
665 
666 #endif /* End of CPU module include. */
667