can_001.h

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/*
 * @brief CAN registers and control functions
 *
 * @note
 * Copyright(C) NXP Semiconductors, 2012
 * All rights reserved.
 *
 * @par
 * Software that is described herein is for illustrative purposes only
 * which provides customers with programming information regarding the
 * LPC products.  This software is supplied "AS IS" without any warranties of
 * any kind, and NXP Semiconductors and its licensor disclaim any and
 * all warranties, express or implied, including all implied warranties of
 * merchantability, fitness for a particular purpose and non-infringement of
 * intellectual property rights.  NXP Semiconductors assumes no responsibility
 * or liability for the use of the software, conveys no license or rights under any
 * patent, copyright, mask work right, or any other intellectual property rights in
 * or to any products. NXP Semiconductors reserves the right to make changes
 * in the software without notification. NXP Semiconductors also makes no
 * representation or warranty that such application will be suitable for the
 * specified use without further testing or modification.
 *
 * @par
 * Permission to use, copy, modify, and distribute this software and its
 * documentation is hereby granted, under NXP Semiconductors' and its
 * licensor's relevant copyrights in the software, without fee, provided that it
 * is used in conjunction with NXP Semiconductors microcontrollers.  This
 * copyright, permission, and disclaimer notice must appear in all copies of
 * this code.
 */

#ifndef __CAN_001_H_
#define __CAN_001_H_

#include "sys_config.h"
#include "cmsis.h"

#ifdef __cplusplus
extern "C" {
#endif

#define CANAF_RAM_ENTRY_NUM        512

typedef enum IP_CAN_AF_RAM_SECTION {
 CANAF_RAM_FULLCAN_SEC, 
 CANAF_RAM_SFF_SEC,  
 CANAF_RAM_SFF_GRP_SEC, 
 CANAF_RAM_EFF_SEC,  
 CANAF_RAM_EFF_GRP_SEC, 
 CANAF_RAM_SECTION_NUM,
} IP_CAN_AF_RAM_SECTION_T;

typedef struct       
{
 __IO uint32_t MASK[CANAF_RAM_ENTRY_NUM]; 
} IP_CAN_001_AF_RAM_T;

typedef struct       
{
 __IO uint32_t AFMR;      
 __IO uint32_t ENDADDR[CANAF_RAM_SECTION_NUM];    
 __I  uint32_t LUTERRAD;     
 __I  uint32_t LUTERR;     
 __IO uint32_t FCANIE;     
 __IO uint32_t FCANIC[2];    
} IP_CAN_001_AF_T;

typedef struct       
{
 __I  uint32_t TXSR;      
 __I  uint32_t RXSR;      
 __I  uint32_t MSR;      
} IP_CAN_001_CR_T;

typedef struct       
{
 __IO uint32_t TFI;     
 __IO uint32_t TID;     
 __IO uint32_t TD[2];    
} IP_CAN_001_TX_T;

typedef struct    
{
 __IO uint32_t RFS;  
 __IO uint32_t RID;  
 __IO uint32_t RD[2]; 
} IP_CAN_001_RX_T;

typedef struct       
{
 __IO uint32_t MOD;     
 __O  uint32_t CMR;     
 __IO uint32_t GSR;     
 __I  uint32_t ICR;     
 __IO uint32_t IER;     
 __IO uint32_t BTR;     
 __IO uint32_t EWL;     
 __I  uint32_t SR;     
 __IO IP_CAN_001_RX_T RX;   
 __IO IP_CAN_001_TX_T TX[3];  
} IP_CAN_001_T;

#define CAN_MOD_BITMASK     (0xBF)

#define CAN_MOD_OPERATION   ((uint32_t) 0)

#define CAN_MOD_RM          ((uint32_t) (1 << 0))

#define CAN_MOD_LOM         ((uint32_t) (1 << 1))

#define CAN_MOD_STM         ((uint32_t) (1 << 2))

#define CAN_MOD_TPM         ((uint32_t) (1 << 3))

#define CAN_MOD_SM          ((uint32_t) (1 << 4))

#define CAN_MOD_RPM         ((uint32_t) (1 << 5))

#define CAN_MOD_TM          ((uint32_t) (1 << 7))

#define CAN_CMR_BITMASK     (0xFF)

#define CAN_CMR_TR          ((uint32_t) (1))

#define CAN_CMR_AT          ((uint32_t) (1 << 1))

#define CAN_CMR_RRB         ((uint32_t) (1 << 2))

#define CAN_CMR_CDO         ((uint32_t) (1 << 3))

#define CAN_CMR_SRR         ((uint32_t) (1 << 4))

#define CAN_CMR_STB(n)       ((uint32_t) (1 << (n + 5)))

#define CAN_GSR_BITMASK     (0xFFFF00FF)

#define CAN_GSR_RBS         ((uint32_t) (1))

#define CAN_GSR_DOS         ((uint32_t) (1 << 1))

#define CAN_GSR_TBS         ((uint32_t) (1 << 2))

#define CAN_GSR_TCS         ((uint32_t) (1 << 3))

#define CAN_GSR_RS          ((uint32_t) (1 << 4))

#define CAN_GSR_TS          ((uint32_t) (1 << 5))

#define CAN_GSR_ES          ((uint32_t) (1 << 6))

#define CAN_GSR_BS          ((uint32_t) (1 << 7))

#define CAN_GSR_RXERR(n)    ((uint32_t) ((n >> 16) & 0xFF)

#define CAN_GSR_TXERR(n)    ((uint32_t) ((n >> 24) & 0xFF)

#define CAN_ICR_BITMASK     (0xFFFF07FF)

#define CAN_ICR_RI          ((uint32_t) (1))

#define CAN_ICR_TI1         ((uint32_t) (1 << 1))

#define CAN_ICR_EI          ((uint32_t) (1 << 2))

#define CAN_ICR_DOI         ((uint32_t) (1 << 3))

#define CAN_ICR_WUI         ((uint32_t) (1 << 4))

#define CAN_ICR_EPI         ((uint32_t) (1 << 5))

#define CAN_ICR_ALI         ((uint32_t) (1 << 6))

#define CAN_ICR_BEI         ((uint32_t) (1 << 7))

#define CAN_ICR_IDI         ((uint32_t) (1 << 8))

#define CAN_ICR_TI2         ((uint32_t) (1 << 9))

#define CAN_ICR_TI3         ((uint32_t) (1 << 10))

#define CAN_ICR_ERRBIT_VAL(n)   ((uint32_t) (((n) >> 16) & 0x1F))

#define CAN_ICR_ERR_SOF             (3)

#define CAN_ICR_ERR_ID28_ID21       (2)

#define CAN_ICR_ERR_ID20_ID18       (6)

#define CAN_ICR_ERR_SRTR        (4)

#define CAN_ICR_ERR_IDE     (5)

#define CAN_ICR_ERR_ID17_ID13       (7)

#define CAN_ICR_ERR_ID12_ID5        (0x0F)

#define CAN_ICR_ERR_ID4_ID0     (0x0E)

#define CAN_ICR_ERR_RTR     (0x0C)

#define CAN_ICR_ERR_ReservedBit_1       (0x0D)

#define CAN_ICR_ERR_ReservedBit_0       (0x09)

#define CAN_ICR_ERR_DLC     (0x0B)

#define CAN_ICR_ERR_DATA_FIELD      (0x0A)

#define CAN_ICR_ERR_CRC_SEQ     (0x08)

#define CAN_ICR_ERR_CRC_DELIMITER       (0x18)

#define CAN_ICR_ERR_ACK     (0x19)

#define CAN_ICR_ERR_ACK_DELIMITER       (0x1B)

#define CAN_ICR_ERR_EOF     (0x1A)

#define CAN_ICR_ERR_INTERMISSION        (0x12)

#define CAN_ICR_ERRDIR_RECEIVE      ((uint32_t) (1 << 21))

#define CAN_ICR_ERRC_VAL(n)     ((uint32_t) (((n) >> 22) & 0x3))
#define CAN_ICR_BIT_ERROR       (0)
#define CAN_ICR_FORM_ERROR      (1)
#define CAN_ICR_STUFF_ERROR     (2)
#define CAN_ICR_OTHER_ERROR     (3)

#define CAN_ICR_ALCBIT_VAL(n)       ((uint32_t) (((n) >> 24) & 0xFF))

#define CAN_IER_BITMASK     (0x7FF)

#define CAN_IER_RIE         ((uint32_t) (1))

#define CAN_IER_TIE1        ((uint32_t) (1 << 1))

#define CAN_IER_EIE         ((uint32_t) (1 << 2))

#define CAN_IER_DOIE        ((uint32_t) (1 << 3))

#define CAN_IER_WUIE        ((uint32_t) (1 << 4))

#define CAN_IER_EPIE        ((uint32_t) (1 << 5))

#define CAN_IER_ALIE        ((uint32_t) (1 << 6))

#define CAN_IER_BEIE        ((uint32_t) (1 << 7))

#define CAN_IER_IDIE        ((uint32_t) (1 << 8))

#define CAN_IER_TIE2        ((uint32_t) (1 << 9))

#define CAN_IER_TIE3        ((uint32_t) (1 << 10))

#define CAN_BTR_BITMASK     (0xFFC3FF)

#define CAN_BTR_BRP(n)      ((uint32_t) ((n) & 0x3FF))

#define CAN_BTR_SJW(n)      ((uint32_t) (((n) & 0x3) << 14))

#define CAN_BTR_TESG1(n)    ((uint32_t) (((n) & 0xF) << 16))

#define CAN_BTR_TESG2(n)    ((uint32_t) (((n) & 0xF) << 20))

#define CAN_BTR_SAM         ((uint32_t) (1 << 23))

#define CAN_EWL_BITMASK     (0xFF)

#define CAN_EWL_VAL(n)      ((uint32_t) ((n) & 0xFF))

#define CAN_SR_BITMASK     (0xFFFFFF)

#define CAN_SR_RBS(n)     ((uint32_t) (1 << ((n) * 8)))

#define CAN_SR_DOS(n)     ((uint32_t) (1 << (1 + (n) * 8)))

#define CAN_SR_TBS(n)     ((uint32_t) (1 << (2 + (n) * 8)))

#define CAN_SR_TCS(n)     ((uint32_t) (1 << (3 + (n) * 8)))

#define CAN_SR_RS(n)      ((uint32_t) (1 << (4 + (n) * 8)))

#define CAN_SR_TS(n)      ((uint32_t) (1 << (5 + (n) * 8)))

#define CAN_SR_ES(n)      ((uint32_t) (1 << (6 + (n) * 8)))

#define CAN_SR_BS(n)      ((uint32_t) (1 << (7 + (n) * 8)))

#define CAN_RFS_BITMASK     (0xC00F07FF)

#define CAN_RFS_ID_INDEX(n) ((uint32_t) ((n) & 0x3FF))

#define CAN_RFS_BP          ((uint32_t) (1 << 10))

#define CAN_RFS_DLC(n)      ((uint32_t) ((n >> 16) & 0x0F))

#define CAN_RFS_RTR         ((uint32_t) (1 << 30))

#define CAN_RFS_FF          ((uint32_t) ((uint32_t) 1 << 31))

#define CAN_RID_ID_11(n)        ((uint32_t) ((n) & 0x7FF))

#define CAN_RID_ID_29(n)        ((uint32_t) ((n) & 0x1FFFFFFF))

#define CAN_TFI_BITMASK     (0xC00F00FF)

#define CAN_TFI_PRIO(n)         ((uint32_t) ((n) & 0xFF))

#define CAN_TFI_DLC(n)          ((uint32_t) (((n) & 0xF) << 16))

#define CAN_TFI_RTR             ((uint32_t) (1 << 30))

#define CAN_TFI_FF              ((uint32_t) ((uint32_t) 1 << 31))

#define CAN_TID_ID11(n)         ((uint32_t) ((n) & 0x7FF))

#define CAN_TID_ID29(n)         ((uint32_t) ((n) & 0x1FFFFFFF))

#define CAN_TSR_BITMASK     (0x30303)

#define CAN_TSR_TS(n)         ((uint32_t) (1 << (n + 0)))

#define CAN_TSR_TBS(n)        ((uint32_t) (1 << (n + 8)))

#define CAN_TSR_TCS(n)        ((uint32_t) (1 << (n + 16)))

#define CAN_RSR_BITMASK     (0x30303)

#define CAN_RSR_RS(n)         ((uint32_t) (1 << (n + 0)))

#define CAN_RSR_RBS(n)        ((uint32_t) (1 << (n + 8)))

#define CAN_RSR_DOS(n)        ((uint32_t) (1 << (n + 16)))

#define CAN_MSR_BITMASK     (0x303)

#define CAN_MSR_E(n)      ((uint32_t) (1 << (n + 0)))

#define CAN_MSR_BS(n)     ((uint32_t) (1 << (n + 8)))

#define CANAF_AFMR_OPERATION     ((uint32_t) (0))

#define CANAF_AFMR_ACCOFF     ((uint32_t) (1))

#define CANAF_AFMR_ACCBP      ((uint32_t) (1 << 1))

#define CANAF_AFMR_EFCAN      ((uint32_t) (1 << 2))

#define CANAF_ENDADDR(n)       ((uint32_t) (((n) & 0x3FF) << 2))
#define CANAF_ENDADDR_VAL(n)   ((uint32_t) ((n >> 2) & 0x3FF))

#define CANAF_LUTERRAD(n)     ((uint32_t) (((n) & 0x1FF) << 2))

#define CANAF_LUTERR      ((uint32_t) (1))

#define CANAF_FCANIE_BITMASK     (0x01)

#define CANAF_FCANIE      ((uint32_t) (1))

#define CANAF_FULLCAN_MSG_FF_POS    (31)

#define CANAF_FULLCAN_MSG_RTR_POS   (30)

#define CANAF_FULLCAN_MSG_LOST_POS  (26)

#define CANAF_FULLCAN_MSG_SEM_POS   (24)

#define CANAF_FULLCAN_MSG_SEM_BITMASK   (0x03)

#define CANAF_FULLCAN_MSG_DLC_POS   (16)

#define CANAF_FULLCAN_MSG_DLC_BITMASK   (0x0F)

#define CANAF_FULLCAN_MSG_SCC_POS   (13)

#define CANAF_FULLCAN_MSG_SCC_BITMASK   (0x07)

#define CANAF_FULLCAN_MSG_ID11_POS  (0)

#define CANAF_FULLCAN_MSG_ID11_BITMASK  (0x7FF)

#define CANAF_FULCAN_MSG_AF_UPDATING        (0x01)

#define CANAF_FULCAN_MSG_AF_FINISHED        (0x03)

#define CANAF_FULCAN_MSG_CPU_READING        (0x0)

#define CANAF_FCAN_IC_INTPND(n)   ((n >= 32) ? ((uint32_t) (1 << (n - 32))) : ((uint32_t) (1 << n)))

#define CAN_STD_ENTRY_CTRL_NO_POS       (13 )

#define CAN_STD_ENTRY_CTRL_NO_MASK      (0x07)

#define CAN_STD_ENTRY_DISABLE_POS       (12 )

#define CAN_STD_ENTRY_DISABLE_MASK      (0x01)

#define CAN_STD_ENTRY_IE_POS            (11 )

#define CAN_STD_ENTRY_IE_MASK           (0x01)

#define CAN_STD_ENTRY_ID_POS            (0  )

#define CAN_STD_ENTRY_ID_MASK           (0x7FF)

#define CAN_EXT_ENTRY_CTRL_NO_POS       (29 )

#define CAN_EXT_ENTRY_CTRL_NO_MASK      (0x07)

#define CAN_EXT_ENTRY_ID_POS            (0  )

#define CAN_EXT_ENTRY_ID_MASK           (0x1FFFFFFF)

#define CAN_REMOTE_MSG         ((uint32_t) (1 << 0))

#define CAN_EXTEND_ID_USAGE     ((uint32_t) (1 << 30))

#define CAN_MSG_MAX_DATA_LEN       (8)

typedef enum IP_CAN_BUFFER_ID {
 CAN_BUFFER_1 = 0, 
 CAN_BUFFER_2,  
 CAN_BUFFER_3,  
 CAN_BUFFER_LAST, 
} IP_CAN_BUFFER_ID_T;

typedef struct      
{
 uint32_t ID;     
 uint32_t Type;     
 uint32_t DLC;     
 uint8_t  Data[CAN_MSG_MAX_DATA_LEN];
} IP_CAN_MSG_T;

typedef struct      
{
 uint16_t BRP;     
 uint8_t SJW;     
 uint8_t TESG1;     
 uint8_t TESG2;     
 uint8_t SAM;     
} IP_CAN_BUS_TIMING_T;

typedef struct {
 uint8_t CtrlNo;    
 uint8_t Disable;   
 uint16_t ID_11;    
} IP_CAN_STD_ID_Entry_T;

typedef struct {
 IP_CAN_STD_ID_Entry_T LowerID; 
 IP_CAN_STD_ID_Entry_T UpperID; 
} IP_CAN_STD_ID_RANGE_Entry_T;

typedef struct {
 uint8_t CtrlNo;   
 uint32_t ID_29;   
} IP_CAN_EXT_ID_Entry_T;

typedef struct {
 IP_CAN_EXT_ID_Entry_T LowerID; 
 IP_CAN_EXT_ID_Entry_T UpperID; 
} IP_CAN_EXT_ID_RANGE_Entry_T;

typedef struct {
 IP_CAN_STD_ID_Entry_T *FullCANSec;  
 uint16_t FullCANEntryNum;     
 IP_CAN_STD_ID_Entry_T *SffSec;   
 uint16_t SffEntryNum;      
 IP_CAN_STD_ID_RANGE_Entry_T *SffGrpSec; 
 uint16_t SffGrpEntryNum;     
 IP_CAN_EXT_ID_Entry_T *EffSec;   
 uint16_t EffEntryNum;      
 IP_CAN_EXT_ID_RANGE_Entry_T *EffGrpSec; 
 uint16_t EffGrpEntryNum;     
} IP_CAN_AF_LUT_T;

STATIC INLINE void IP_CAN_DeInit(IP_CAN_001_T *pCAN)
{}

STATIC INLINE uint32_t IP_CAN_GetMode(IP_CAN_001_T *pCAN)
{
 return pCAN->MOD & CAN_MOD_BITMASK;
}

STATIC INLINE void IP_CAN_SetCmd(IP_CAN_001_T *pCAN, uint32_t command)
{
 pCAN->CMR = command;
}

STATIC INLINE void IP_CAN_SetEWL(IP_CAN_001_T *pCAN, uint32_t ewl)
{
 pCAN->EWL = ewl & CAN_EWL_BITMASK;
}

STATIC INLINE uint8_t IP_CAN_GetEWL(IP_CAN_001_T *pCAN)
{
 return CAN_EWL_VAL(pCAN->EWL);
}

STATIC INLINE uint32_t IP_CAN_GetGlobalStatus(IP_CAN_001_T *pCAN)
{
 return pCAN->GSR;
}

STATIC INLINE uint32_t IP_CAN_GetStatus(IP_CAN_001_T *pCAN)
{
 return pCAN->SR;
}

STATIC INLINE void IP_CAN_IntEnable(IP_CAN_001_T *pCAN, uint32_t IntMask) {
 pCAN->IER |= IntMask;
}

STATIC INLINE void IP_CAN_IntDisable(IP_CAN_001_T *pCAN, uint32_t IntMask) {
 pCAN->IER &= (~IntMask) & CAN_IER_BITMASK;
}

STATIC INLINE uint32_t IP_CAN_GetIntStatus(IP_CAN_001_T *pCAN)
{
 return pCAN->ICR;
}

STATIC INLINE void IP_CAN_AF_SetMode(IP_CAN_001_AF_T *pCanAF, uint32_t AFMode)
{
 pCanAF->AFMR = AFMode;
}

STATIC INLINE uint32_t IP_CAN_AF_GetMode(IP_CAN_001_AF_T *pCanAF)
{
 return pCanAF->AFMR;
}

void IP_CAN_Init(IP_CAN_001_T *pCAN);

void IP_CAN_SetMode(IP_CAN_001_T *pCAN, uint32_t Mode, FunctionalState NewState);

void IP_CAN_SetBusTiming(IP_CAN_001_T *pCAN, IP_CAN_BUS_TIMING_T *pBusTiming);

Status IP_CAN_Receive(IP_CAN_001_T *pCAN, IP_CAN_MSG_T *pMsg);

Status IP_CAN_Send(IP_CAN_001_T *pCAN, IP_CAN_BUFFER_ID_T TxBufID, IP_CAN_MSG_T *pMsg);

void IP_CAN_AF_Init(IP_CAN_001_AF_T *pCanAF, IP_CAN_001_AF_RAM_T *pCanAFRam);

void IP_CAN_FullCANIntConfig(IP_CAN_001_AF_T *pCanAF, FunctionalState NewState);

uint32_t IP_CAN_GetFullCANIntStatus(IP_CAN_001_AF_T *pCanAF, uint8_t ObjID);

Status IP_CAN_FullCANReceive(IP_CAN_001_AF_T *pCanAF, IP_CAN_001_AF_RAM_T *pCanAFRam,
        uint8_t ObjID, IP_CAN_MSG_T *pMsg, uint8_t *pSCC);

void IP_CAN_ClearAFLUT(IP_CAN_001_AF_T *pCanAF, IP_CAN_001_AF_RAM_T *pCanAFRam);

Status IP_CAN_SetAFLUT(IP_CAN_001_AF_T *pCanAF, IP_CAN_001_AF_RAM_T *pCanAFRam, IP_CAN_AF_LUT_T *pAFSections);

Status IP_CAN_InsertFullCANEntry(IP_CAN_001_AF_T *pCanAF,
         IP_CAN_001_AF_RAM_T *pCanAFRam,
         IP_CAN_STD_ID_Entry_T *pEntry);

Status IP_CAN_InsertIndividualSTDEntry(IP_CAN_001_AF_T *pCanAF,
            IP_CAN_001_AF_RAM_T *pCanAFRam,
            IP_CAN_STD_ID_Entry_T *pEntry);

Status IP_CAN_InsertGroupSTDEntry(IP_CAN_001_AF_T *pCanAF,
          IP_CAN_001_AF_RAM_T *pCanAFRam,
          IP_CAN_STD_ID_RANGE_Entry_T *pEntry);

Status IP_CAN_InsertIndividualEXTEntry(IP_CAN_001_AF_T *pCanAF,
            IP_CAN_001_AF_RAM_T *pCanAFRam,
            IP_CAN_EXT_ID_Entry_T *pEntry);

Status IP_CAN_InsertGroupEXTEntry(IP_CAN_001_AF_T *pCanAF,
          IP_CAN_001_AF_RAM_T *pCanAFRam,
          IP_CAN_EXT_ID_RANGE_Entry_T *pEntry);

Status IP_CAN_RemoveFullCANEntry(IP_CAN_001_AF_T *pCanAF,
         IP_CAN_001_AF_RAM_T *pCanAFRam,
         int16_t Position);

Status IP_CAN_RemoveIndividualSTDEntry(IP_CAN_001_AF_T *pCanAF,
            IP_CAN_001_AF_RAM_T *pCanAFRam,
            int16_t Position);

Status IP_CAN_RemoveGroupSTDEntry(IP_CAN_001_AF_T *pCanAF,
          IP_CAN_001_AF_RAM_T *pCanAFRam,
          int16_t Position);

Status IP_CAN_RemoveIndividualEXTEntry(IP_CAN_001_AF_T *pCanAF,
            IP_CAN_001_AF_RAM_T *pCanAFRam,
            int16_t Position);

Status IP_CAN_RemoveGroupEXTEntry(IP_CAN_001_AF_T *pCanAF,
          IP_CAN_001_AF_RAM_T *pCanAFRam,
          int16_t Position);

uint16_t IP_CAN_GetEntriesNum(IP_CAN_001_AF_T *pCanAF,
         IP_CAN_001_AF_RAM_T *pCanAFRam,
         IP_CAN_AF_RAM_SECTION_T SectionID);

Status IP_CAN_ReadFullCANEntry(IP_CAN_001_AF_T *pCanAF,
          IP_CAN_001_AF_RAM_T *pCanAFRam,
          uint16_t Position,
          IP_CAN_STD_ID_Entry_T *pEntry);

Status IP_CAN_ReadIndividualSTDEntry(IP_CAN_001_AF_T *pCanAF,
          IP_CAN_001_AF_RAM_T *pCanAFRam,
          uint16_t Position,
          IP_CAN_STD_ID_Entry_T *pEntry);

Status IP_CAN_ReadGroupSTDEntry(IP_CAN_001_AF_T *pCanAF,
        IP_CAN_001_AF_RAM_T *pCanAFRam,
        uint16_t Position,
        IP_CAN_STD_ID_RANGE_Entry_T *pEntry);

Status IP_CAN_ReadIndividualEXTEntry(IP_CAN_001_AF_T *pCanAF,
          IP_CAN_001_AF_RAM_T *pCanAFRam,
          uint16_t Position,
          IP_CAN_EXT_ID_Entry_T *pEntry);

Status IP_CAN_ReadGroupEXTEntry(IP_CAN_001_AF_T *pCanAF,
        IP_CAN_001_AF_RAM_T *pCanAFRam,
        uint16_t Position,
        IP_CAN_EXT_ID_RANGE_Entry_T *pEntry);

#ifdef __cplusplus
}
#endif

#endif /* __CAN_001_H_ */