cmsis.h

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/*
 * @brief Basic CMSIS include file
 *
 * @note
 * Copyright(C) NXP Semiconductors, 2012
 * All rights reserved.
 *
 * @par
 * Software that is described herein is for illustrative purposes only
 * which provides customers with programming information regarding the
 * LPC products.  This software is supplied "AS IS" without any warranties of
 * any kind, and NXP Semiconductors and its licensor disclaim any and
 * all warranties, express or implied, including all implied warranties of
 * merchantability, fitness for a particular purpose and non-infringement of
 * intellectual property rights.  NXP Semiconductors assumes no responsibility
 * or liability for the use of the software, conveys no license or rights under any
 * patent, copyright, mask work right, or any other intellectual property rights in
 * or to any products. NXP Semiconductors reserves the right to make changes
 * in the software without notification. NXP Semiconductors also makes no
 * representation or warranty that such application will be suitable for the
 * specified use without further testing or modification.
 *
 * @par
 * Permission to use, copy, modify, and distribute this software and its
 * documentation is hereby granted, under NXP Semiconductors' and its
 * licensor's relevant copyrights in the software, without fee, provided that it
 * is used in conjunction with NXP Semiconductors microcontrollers.  This
 * copyright, permission, and disclaimer notice must appear in all copies of
 * this code.
 */

#ifndef __CMSIS_H_
#define __CMSIS_H_

#include "lpc_types.h"
#include "sys_config.h"

#ifdef __cplusplus
extern "C" {
#endif

#if defined(__ARMCC_VERSION)
// Kill warning "#pragma push with no matching #pragma pop"
  #pragma diag_suppress 2525
  #pragma push
  #pragma anon_unions
#elif defined(__CWCC__)
  #pragma push
  #pragma cpp_extensions on
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
//  #pragma push // FIXME not usable for IAR
  #pragma language=extended
#else
  #error Not supported compiler type
#endif

#if defined(CORE_M4)

#define __CM4_REV              0x0000  
#define __MPU_PRESENT             1   
#define __NVIC_PRIO_BITS          5   
#define __Vendor_SysTickConfig    0   
#ifndef __FPU_PRESENT
#define __FPU_PRESENT             1   
#endif

typedef enum {
 /* -------------------------  Cortex-M4 Processor Exceptions Numbers  ----------------------------- */
 Reset_IRQn                    = -15,  
 NonMaskableInt_IRQn           = -14,  
 HardFault_IRQn                = -13,  
 MemoryManagement_IRQn         = -12,  
 BusFault_IRQn                 = -11,  
 UsageFault_IRQn               = -10,  
 SVCall_IRQn                   = -5,   
 DebugMonitor_IRQn             = -4,   
 PendSV_IRQn                   = -2,   
 SysTick_IRQn                  = -1,   
 /* ---------------------------  LPC40xx Specific Interrupt Numbers  ------------------------------- */
 WDT_IRQn                      = 0,   
 TIMER0_IRQn                   = 1,   
 TIMER1_IRQn                   = 2,   
 TIMER2_IRQn                   = 3,   
 TIMER3_IRQn                   = 4,   
 UART0_IRQn                    = 5,   
 UART1_IRQn                    = 6,   
 UART2_IRQn                    = 7,   
 UART3_IRQn                    = 8,   
 PWM1_IRQn                     = 9,   
 I2C0_IRQn                     = 10,   
 I2C1_IRQn                     = 11,   
 I2C2_IRQn                     = 12,   
 SPI_IRQn                      = 13,   
 SSP0_IRQn                     = 14,   
 SSP1_IRQn                     = 15,   
 PLL0_IRQn                     = 16,   
 RTC_IRQn                      = 17,   
 EINT0_IRQn                    = 18,   
 EINT1_IRQn                    = 19,   
 EINT2_IRQn                    = 20,   
 EINT3_IRQn                    = 21,   
 ADC_IRQn                      = 22,   
 BOD_IRQn                      = 23,   
 USB_IRQn                      = 24,   
 CAN_IRQn                      = 25,   
 DMA_IRQn                      = 26,   
 I2S_IRQn                      = 27,   
 ETHERNET_IRQn                 = 28,   
 SDC_IRQn                      = 29,   
 MCPWM_IRQn                    = 30,   
 QEI_IRQn                      = 31,   
 PLL1_IRQn                     = 32,   
 USBActivity_IRQn              = 33,   
 CANActivity_IRQn              = 34,   
 UART4_IRQn                    = 35,   
 SSP2_IRQn                     = 36,   
 LCD_IRQn                      = 37,   
 GPIO_IRQn                     = 38,   
 PWM0_IRQn                     = 39,   
 EEPROM_IRQn                   = 40,   
} IRQn_Type;

#include "core_cm4.h"      
#elif defined(CORE_M3)

#define __MPU_PRESENT             1   
#define __NVIC_PRIO_BITS          5   
#define __Vendor_SysTickConfig    0   
#define __FPU_PRESENT             0   
typedef enum {
 /* -------------------------  Cortex-M3 Processor Exceptions Numbers  ----------------------------- */
 Reset_IRQn                    = -15,  
 NonMaskableInt_IRQn           = -14,  
 HardFault_IRQn                = -13,  
 MemoryManagement_IRQn         = -12,  
 BusFault_IRQn                 = -11,  
 UsageFault_IRQn               = -10,  
 SVCall_IRQn                   = -5,   
 DebugMonitor_IRQn             = -4,   
 PendSV_IRQn                   = -2,   
 SysTick_IRQn                  = -1,   
 /* ---------------------------  LPC17xx Specific Interrupt Numbers  ------------------------------- */
 WDT_IRQn                      = 0,   
 TIMER0_IRQn                   = 1,   
 TIMER1_IRQn                   = 2,   
 TIMER2_IRQn                   = 3,   
 TIMER3_IRQn                   = 4,   
 UART0_IRQn                    = 5,   
 UART1_IRQn                    = 6,   
 UART2_IRQn                    = 7,   
 UART3_IRQn                    = 8,   
 PWM1_IRQn                     = 9,   
 I2C0_IRQn                     = 10,   
 I2C1_IRQn                     = 11,   
 I2C2_IRQn                     = 12,   
#if defined(CHIP_LPC175X_6X)
 SPI_IRQn                      = 13,   
#else
 Reserved0_IRQn                = 13,   
#endif 
 SSP0_IRQn                     = 14,   
 SSP1_IRQn                     = 15,   
 PLL0_IRQn                     = 16,   
 RTC_IRQn                      = 17,   
 EINT0_IRQn                    = 18,   
 EINT1_IRQn                    = 19,   
 EINT2_IRQn                    = 20,   
 EINT3_IRQn                    = 21,   
 ADC_IRQn                      = 22,   
 BOD_IRQn                      = 23,   
 USB_IRQn                      = 24,   
 CAN_IRQn                      = 25,   
 DMA_IRQn                      = 26,   
 I2S_IRQn                      = 27,   
 ETHERNET_IRQn                 = 28,   
#if defined(CHIP_LPC175X_6X)
 RITIMER_IRQn                  = 29,   
#else
 SDC_IRQn                      = 29,   
#endif
 MCPWM_IRQn                    = 30,   
 QEI_IRQn                      = 31,   
 PLL1_IRQn                     = 32,   
 USBActivity_IRQn              = 33,   
 CANActivity_IRQn              = 34,   
#if defined(CHIP_LPC177X_8X)
 UART4_IRQn                    = 35,   
 SSP2_IRQn                     = 36,   
 LCD_IRQn                      = 37,   
 GPIO_IRQn                     = 38,   
 PWM0_IRQn                     = 39,   
 EEPROM_IRQn                   = 40,   
#endif
} IRQn_Type;

#include "core_cm3.h"      
#else
#error Please #define CORE_M3 or CORE_M4
#endif

#ifdef __cplusplus
}
#endif

#endif /* __CMSIS_H_ */