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crc_001.h
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1 /*
2  * @brief Cyclic Redundancy Check (CRC) registers and driver functions
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2012
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #ifndef __CRC_001_H_
33 #define __CRC_001_H_
34 
35 #include "sys_config.h"
36 #include "cmsis.h"
37 
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41 
50 typedef struct {
51  __IO uint32_t MODE;
52  __IO uint32_t SEED;
53  union {
54  __I uint32_t SUM;
56  __O uint16_t WRDATA16;
57  __O uint8_t WRDATA8;
58  };
59 
60 } IP_CRC_001_T;
61 
65 #define CRC_MODE_POLY_BITMASK ((0x03))
66 #define CRC_MODE_POLY_CCITT (0x00)
67 #define CRC_MODE_POLY_CRC16 (0x01)
68 #define CRC_MODE_POLY_CRC32 (0x02)
69 #define CRC_MODE_WRDATA_BITMASK (0x03 << 2)
70 #define CRC_MODE_WRDATA_BIT_RVS (1 << 2)
71 #define CRC_MODE_WRDATA_CMPL (1 << 3)
72 #define CRC_MODE_SUM_BITMASK (0x03 << 4)
73 #define CRC_MODE_SUM_BIT_RVS (1 << 4)
74 #define CRC_MODE_SUM_CMPL (1 << 5)
76 #define MODE_CFG_CCITT (0x00)
77 #define MODE_CFG_CRC16 (0x15)
78 #define MODE_CFG_CRC32 (0x36)
80 #define CRC_SEED_CCITT (0x0000FFFF)
81 #define CRC_SEED_CRC16 (0x00000000)
82 #define CRC_SEED_CRC32 (0xFFFFFFFF)
84 /*
85  * @brief CRC polynomial
86  */
87 typedef enum IP_CRC_001_POLY {
93 
100 
107 
118  uint32_t flags)
119 {
120  pCRC->MODE = (uint32_t) poly | flags;
121 }
122 
130 
137 {
138  return pCRC->MODE;
139 }
140 
148 {
149  pCRC->MODE = mode;
150 }
151 
159 {
160  pCRC->SEED = Seed;
161 }
162 
169 {
170  return pCRC->SEED;
171 }
172 
179 STATIC INLINE void IP_CRC_Write8(IP_CRC_001_T *pCRC, uint8_t data)
180 {
181  pCRC->WRDATA8 = data;
182 }
183 
190 STATIC INLINE void IP_CRC_Write16(IP_CRC_001_T *pCRC, uint16_t data)
191 {
192  pCRC->WRDATA16 = (uint32_t) data;
193 }
194 
202 {
203  pCRC->WRDATA32 = data;
204 }
205 
212 {
213  return pCRC->SUM;
214 }
215 
223 uint32_t IP_CRC_CRC8(IP_CRC_001_T *pCRC, const uint8_t *data, uint32_t bytes);
224 
232 uint32_t IP_CRC_CRC16(IP_CRC_001_T *pCRC, const uint16_t *data, uint32_t hwords);
233 
242 
247 #ifdef __cplusplus
248 }
249 #endif
250 
251 #endif /* __CRC_001_H_ */