creg_18xx_43xx.h

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/*
 * @brief LPC18XX/43XX CREG control functions
 *
 * @note
 * Copyright(C) NXP Semiconductors, 2012
 * All rights reserved.
 *
 * @par
 * Software that is described herein is for illustrative purposes only
 * which provides customers with programming information regarding the
 * LPC products.  This software is supplied "AS IS" without any warranties of
 * any kind, and NXP Semiconductors and its licensor disclaim any and
 * all warranties, express or implied, including all implied warranties of
 * merchantability, fitness for a particular purpose and non-infringement of
 * intellectual property rights.  NXP Semiconductors assumes no responsibility
 * or liability for the use of the software, conveys no license or rights under any
 * patent, copyright, mask work right, or any other intellectual property rights in
 * or to any products. NXP Semiconductors reserves the right to make changes
 * in the software without notification. NXP Semiconductors also makes no
 * representation or warranty that such application will be suitable for the
 * specified use without further testing or modification.
 *
 * @par
 * Permission to use, copy, modify, and distribute this software and its
 * documentation is hereby granted, under NXP Semiconductors' and its
 * licensor's relevant copyrights in the software, without fee, provided that it
 * is used in conjunction with NXP Semiconductors microcontrollers.  This
 * copyright, permission, and disclaimer notice must appear in all copies of
 * this code.
 */

#ifndef __CREG_18XX_43XX_H_
#define __CREG_18XX_43XX_H_

#ifdef __cplusplus
extern "C" {
#endif

typedef struct {      
 __I  uint32_t  RESERVED0;
 __IO uint32_t  CREG0;    
 __I  uint32_t  RESERVED1[62];
 __IO uint32_t  MXMEMMAP;   
#if defined(CHIP_LPC18XX)
 __I  uint32_t  RESERVED2[5];
#else
 __I  uint32_t  RESERVED2;
 __I  uint32_t  CREG1;    
 __I  uint32_t  CREG2;    
 __I  uint32_t  CREG3;    
 __I  uint32_t  CREG4;    
#endif
 __IO uint32_t  CREG5;    
 __IO uint32_t  DMAMUX;    
 __IO uint32_t  FLASHCFGA;   
 __IO uint32_t  FLASHCFGB;   
 __IO uint32_t  ETBCFG;    
 __IO uint32_t  CREG6;    
#if defined(CHIP_LPC18XX)
 __I  uint32_t  RESERVED4[52];
#else
 __IO uint32_t  M4TXEVENT;   
 __I  uint32_t  RESERVED4[51];
#endif
 __I  uint32_t  CHIPID;    
#if defined(CHIP_LPC18XX)
 __I  uint32_t  RESERVED5[191];
#else
 __I  uint32_t  RESERVED5[127];
 __IO uint32_t  M0TXEVENT;   
 __IO uint32_t  M0APPMEMMAP;   
 __I  uint32_t  RESERVED6[62];
#endif
 __IO uint32_t  USB0FLADJ;   
 __I  uint32_t  RESERVED7[63];
 __IO uint32_t  USB1FLADJ;   
} LPC_CREG_T;

STATIC INLINE uint32_t Chip_CREG_OnChipFlashIsPresent(void)
{
 return LPC_CREG->CHIPID != 0x3284E02B;
}

STATIC INLINE void Chip_CREG_SetFlashAcceleration(uint32_t Hz)
{
 uint32_t FAValue = Hz / 21510000;

 LPC_CREG->FLASHCFGA = (LPC_CREG->FLASHCFGA & (~(0xF << 12))) | (FAValue << 12);
 LPC_CREG->FLASHCFGB = (LPC_CREG->FLASHCFGB & (~(0xF << 12))) | (FAValue << 12);
}

STATIC INLINE void Chip_CREG_EnableUSB0Phy(bool Enable)
{
 if (Enable) {
  LPC_CREG->CREG0 &= ~(1 << 5);
 }
 else {
  LPC_CREG->CREG0 |= (1 << 5);
 }
}

STATIC INLINE void Chip_CREG_ConfigureBODaR(uint32_t BODVL, uint32_t BORVL)
{
 LPC_CREG->CREG0 = (LPC_CREG->CREG0 & ~((3 << 8) | (3 << 10))) | (BODVL << 8) | (BORVL << 10);
}

#if (defined(CHIP_LPC43XX) && defined(LPC_CREG))

STATIC INLINE void Chip_CREG_SetM0AppMemMap(uint32_t memaddr)
{
 LPC_CREG->M0APPMEMMAP = memaddr & ~0xFFF;
}

STATIC INLINE void Chip_CREG_ClearM4Event(void)
{
 LPC_CREG->M4TXEVENT = 0;
}

STATIC INLINE void Chip_CREG_ClearM0Event(void)
{
 LPC_CREG->M0TXEVENT = 0;
}

#endif

#ifdef __cplusplus
}
#endif

#endif /* __CREG_18XX_43XX_H_ */