Detailed Description

Modules
	CHIP: LPC11xx Clock Control driver options

Macros
#define	SYSCTL_IRC_FREQ (12000000)

Enumerations
enum	CHIP_SYSCTL_PLLCLKSRC_T { SYSCTL_PLLCLKSRC_IRC = 0, SYSCTL_PLLCLKSRC_MAINOSC, SYSCTL_PLLCLKSRC_RESERVED1, SYSCTL_PLLCLKSRC_RESERVED2, SYSCTL_PLLCLKSRC_IRC = 0, SYSCTL_PLLCLKSRC_SYSOSC, SYSCTL_PLLCLKSRC_RESERVED1, SYSCTL_PLLCLKSRC_RESERVED2, SYSCTL_PLLCLKSRC_IRC, SYSCTL_PLLCLKSRC_MAINOSC, SYSCTL_PLLCLKSRC_RESERVED1, SYSCTL_PLLCLKSRC_RESERVED2, SYSCTL_PLLCLKSRC_IRC = 0, SYSCTL_PLLCLKSRC_SYSOSC, SYSCTL_PLLCLKSRC_RESERVED, SYSCTL_PLLCLKSRC_EXT_CLKIN }

enum	CHIP_WDTLFO_OSC_T { WDTLFO_OSC_ILLEGAL, WDTLFO_OSC_0_60, WDTLFO_OSC_1_05, WDTLFO_OSC_1_40, WDTLFO_OSC_1_75, WDTLFO_OSC_2_10, WDTLFO_OSC_2_40, WDTLFO_OSC_2_70, WDTLFO_OSC_3_00, WDTLFO_OSC_3_25, WDTLFO_OSC_3_50, WDTLFO_OSC_3_75, WDTLFO_OSC_4_00, WDTLFO_OSC_4_20, WDTLFO_OSC_4_40, WDTLFO_OSC_4_60, WDTLFO_OSC_ILLEGAL, WDTLFO_OSC_0_60, WDTLFO_OSC_1_05, WDTLFO_OSC_1_40, WDTLFO_OSC_1_75, WDTLFO_OSC_2_10, WDTLFO_OSC_2_40, WDTLFO_OSC_2_70, WDTLFO_OSC_3_00, WDTLFO_OSC_3_25, WDTLFO_OSC_3_50, WDTLFO_OSC_3_75, WDTLFO_OSC_4_00, WDTLFO_OSC_4_20, WDTLFO_OSC_4_40, WDTLFO_OSC_4_60, WDTLFO_OSC_ILLEGAL, WDTLFO_OSC_0_60, WDTLFO_OSC_1_05, WDTLFO_OSC_1_40, WDTLFO_OSC_1_75, WDTLFO_OSC_2_10, WDTLFO_OSC_2_40, WDTLFO_OSC_2_70, WDTLFO_OSC_3_00, WDTLFO_OSC_3_25, WDTLFO_OSC_3_50, WDTLFO_OSC_3_75, WDTLFO_OSC_4_00, WDTLFO_OSC_4_20, WDTLFO_OSC_4_40, WDTLFO_OSC_4_60 }

enum	CHIP_SYSCTL_MAINCLKSRC_T { SYSCTL_MAINCLKSRC_IRC = 0, SYSCTL_MAINCLKSRC_PLLIN, SYSCTL_MAINCLKSRC_LFOSC, SYSCTL_MAINCLKSRC_WDTOSC = SYSCTL_MAINCLKSRC_LFOSC, SYSCTL_MAINCLKSRC_PLLOUT, SYSCTL_MAINCLKSRC_IRC = 0, SYSCTL_MAINCLKSRC_PLLIN, SYSCTL_MAINCLKSRC_WDTOSC, SYSCTL_MAINCLKSRC_PLLOUT, SYSCTL_MAINCLKSRC_IRC = 0, SYSCTL_MAINCLKSRC_PLLIN, SYSCTL_MAINCLKSRC_WDTOSC, SYSCTL_MAINCLKSRC_PLLOUT }

enum	CHIP_SYSCTL_CLOCK_T { SYSCTL_CLOCK_SYS = 0, SYSCTL_CLOCK_ROM, SYSCTL_CLOCK_RAM, SYSCTL_CLOCK_FLASHREG, SYSCTL_CLOCK_FLASHARRAY, SYSCTL_CLOCK_I2C, SYSCTL_CLOCK_GPIO, SYSCTL_CLOCK_CT16B0, SYSCTL_CLOCK_CT16B1, SYSCTL_CLOCK_CT32B0, SYSCTL_CLOCK_CT32B1, SYSCTL_CLOCK_SSP0, SYSCTL_CLOCK_UART0, SYSCTL_CLOCK_ADC, SYSCTL_CLOCK_RESERVED14, SYSCTL_CLOCK_WDT, SYSCTL_CLOCK_IOCON, SYSCTL_CLOCK_RESERVED17, SYSCTL_CLOCK_SSP1, SYSCTL_CLOCK_PINT, SYSCTL_CLOCK_RESERVED20, SYSCTL_CLOCK_RESERVED21, SYSCTL_CLOCK_RESERVED22, SYSCTL_CLOCK_P0INT, SYSCTL_CLOCK_GROUP0INT = SYSCTL_CLOCK_P0INT, SYSCTL_CLOCK_P1INT, SYSCTL_CLOCK_GROUP1INT = SYSCTL_CLOCK_P1INT, SYSCTL_CLOCK_RESERVED25, SYSCTL_CLOCK_RESERVED26, SYSCTL_CLOCK_RESERVED27, SYSCTL_CLOCK_SYS = 0, SYSCTL_CLOCK_ROM, SYSCTL_CLOCK_RAM, SYSCTL_CLOCK_FLASHREG, SYSCTL_CLOCK_FLASHARRAY, SYSCTL_CLOCK_I2C, SYSCTL_CLOCK_GPIO, SYSCTL_CLOCK_CT16B0, SYSCTL_CLOCK_CT16B1, SYSCTL_CLOCK_CT32B0, SYSCTL_CLOCK_CT32B1, SYSCTL_CLOCK_SSP0, SYSCTL_CLOCK_UART0, SYSCTL_CLOCK_ADC, SYSCTL_CLOCK_USB, SYSCTL_CLOCK_WDT, SYSCTL_CLOCK_IOCON, SYSCTL_CLOCK_RESERVED17, SYSCTL_CLOCK_SSP1, SYSCTL_CLOCK_LCD, SYSCTL_CLOCK_TIMER0, SYSCTL_CLOCK_TIMER1, SYSCTL_CLOCK_UART0, SYSCTL_CLOCK_UART1, SYSCTL_CLOCK_PWM0, SYSCTL_CLOCK_PWM1, SYSCTL_CLOCK_I2C0, SYSCTL_CLOCK_UART4, SYSCTL_CLOCK_RTC, SYSCTL_CLOCK_SSP1, SYSCTL_CLOCK_EMC, SYSCTL_CLOCK_ADC, SYSCTL_CLOCK_CAN1, SYSCTL_CLOCK_CAN2, SYSCTL_CLOCK_GPIO, SYSCTL_CLOCK_SPIFI, SYSCTL_CLOCK_MCPWM, SYSCTL_CLOCK_QEI, SYSCTL_CLOCK_I2C1, SYSCTL_CLOCK_SSP2, SYSCTL_CLOCK_SSP0, SYSCTL_CLOCK_TIMER2, SYSCTL_CLOCK_TIMER3, SYSCTL_CLOCK_UART2, SYSCTL_CLOCK_UART3, SYSCTL_CLOCK_I2C2, SYSCTL_CLOCK_I2S, SYSCTL_CLOCK_SDC, SYSCTL_CLOCK_GPDMA, SYSCTL_CLOCK_ENET, SYSCTL_CLOCK_USB, SYSCTL_CLOCK_RSVD32, SYSCTL_CLOCK_RSVD33, SYSCTL_CLOCK_RSVD34, SYSCTL_CLOCK_RSVD35, SYSCTL_CLOCK_SYS = 0, SYSCTL_CLOCK_ROM, SYSCTL_CLOCK_RAM, SYSCTL_CLOCK_FLASHREG, SYSCTL_CLOCK_FLASH, SYSCTL_CLOCK_I2C, SYSCTL_CLOCK_GPIO, SYSCTL_CLOCK_SWM, SYSCTL_CLOCK_SCT, SYSCTL_CLOCK_WKT, SYSCTL_CLOCK_MRT, SYSCTL_CLOCK_SPI0, SYSCTL_CLOCK_SPI1, SYSCTL_CLOCK_CRC, SYSCTL_CLOCK_UART0, SYSCTL_CLOCK_UART1, SYSCTL_CLOCK_UART2, SYSCTL_CLOCK_WWDT, SYSCTL_CLOCK_IOCON, SYSCTL_CLOCK_ACOMP }

enum	CHIP_SYSCTL_CLKOUTSRC_T { SYSCTL_CLKOUTSRC_IRC = 0, SYSCTL_CLKOUTSRC_MAINOSC, SYSCTL_CLKOUTSRC_WDTOSC, SYSCTL_CLKOUTSRC_LFOSC = SYSCTL_CLKOUTSRC_WDTOSC, SYSCTL_CLKOUTSRC_MAINSYSCLK, SYSCTL_CLKOUTSRC_IRC = 0, SYSCTL_CLKOUTSRC_SYSOSC, SYSCTL_CLKOUTSRC_WDTOSC, SYSCTL_CLKOUTSRC_MAINSYSCLK, SYSCTL_CLKOUTSRC_CPU, SYSCTL_CLKOUTSRC_MAINOSC, SYSCTL_CLKOUTSRC_IRC, SYSCTL_CLKOUTSRC_USB, SYSCTL_CLKOUTSRC_RTC, SYSCTL_CLKOUTSRC_SPIFI, SYSCTL_CLKOUTSRC_WATCHDOGOSC, SYSCTL_CLKOUTSRC_RESERVED3, SYSCTL_CLKOUTSRC_IRC = 0, SYSCTL_CLKOUTSRC_SYSOSC, SYSCTL_CLKOUTSRC_WDTOSC, SYSCTL_CLKOUTSRC_MAINSYSCLK }

Functions
STATIC INLINE void	Chip_Clock_SetupSystemPLL (uint8_t msel, uint8_t psel)
	Set System PLL divider values.

STATIC INLINE bool	Chip_Clock_IsSystemPLLLocked (void)
	Read System PLL lock status.

void	Chip_Clock_SetSystemPllSource (CHIP_SYSCTL_PLLCLKSRC_T src)
	Set System PLL clock source.

void	Chip_Clock_SetPLLBypass (bool bypass, bool highfr)
	Bypass System Oscillator and set oscillator frequency range.

STATIC INLINE void	Chip_Clock_SetWDTOSC (CHIP_WDTLFO_OSC_T wdtclk, uint8_t div)
	Setup Watchdog oscillator rate and divider.

void	Chip_Clock_SetMainClockSource (CHIP_SYSCTL_MAINCLKSRC_T src)
	Set main system clock source.

STATIC INLINE CHIP_SYSCTL_MAINCLKSRC_T	Chip_Clock_GetMainClockSource (void)
	Returns the main clock source.

STATIC INLINE void	Chip_Clock_SetSysClockDiv (uint32_t div)
	Set system clock divider.

STATIC INLINE void	Chip_Clock_EnablePeriphClock (CHIP_SYSCTL_CLOCK_T clk)
	Enable a system or peripheral clock.

STATIC INLINE void	Chip_Clock_DisablePeriphClock (CHIP_SYSCTL_CLOCK_T clk)
	Disable a system or peripheral clock.

STATIC INLINE void	Chip_Clock_SetSSP0ClockDiv (uint32_t div)
	Set SSP0 divider.

STATIC INLINE uint32_t	Chip_Clock_GetSSP0ClockDiv (void)
	Return SSP0 divider.

STATIC INLINE void	Chip_Clock_SetUARTClockDiv (uint32_t div)
	Set UART divider clock.

STATIC INLINE uint32_t	Chip_Clock_GetUARTClockDiv (void)
	Return UART divider.

void	Chip_Clock_SetCLKOUTSource (CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div)
	Set CLKOUT clock source and divider.

STATIC INLINE uint32_t	Chip_Clock_GetMainOscRate (void)
	Returns the main oscillator clock rate.

STATIC INLINE uint32_t	Chip_Clock_GetIntOscRate (void)
	Returns the internal oscillator (IRC) clock rate.

uint32_t	Chip_Clock_GetWDTOSCRate (void)
	Return estimated watchdog oscillator rate.

uint32_t	Chip_Clock_GetSystemPllInClockRate (void)
	Return System PLL input clock rate.

uint32_t	Chip_Clock_GetSystemPllOutClockRate (void)
	Return System PLL output clock rate.

uint32_t	Chip_Clock_GetMainClockRate (void)
	Return main clock rate.

uint32_t	Chip_Clock_GetSystemClockRate (void)
	Return system clock rate.

Macro Definition Documentation

#define SYSCTL_IRC_FREQ (12000000)

Internal oscillator frequency

Definition at line 62 of file clock_11xx.h.

Enumeration Type Documentation

enum CHIP_SYSCTL_CLKOUTSRC_T

Clock sources for CLKOUT

Enumerator:

SYSCTL_CLKOUTSRC_IRC	Internal oscillator for CLKOUT
SYSCTL_CLKOUTSRC_MAINOSC	Main oscillator for CLKOUT
SYSCTL_CLKOUTSRC_WDTOSC	Watchdog oscillator for CLKOUT
SYSCTL_CLKOUTSRC_LFOSC	LF oscillator rate (LPC11A/Exx only) for CLKOUT
SYSCTL_CLKOUTSRC_MAINSYSCLK	Main system clock for CLKOUT
SYSCTL_CLKOUTSRC_IRC	Internal oscillator for CLKOUT
SYSCTL_CLKOUTSRC_SYSOSC	Main oscillator for CLKOUT
SYSCTL_CLKOUTSRC_WDTOSC	Watchdog oscillator for CLKOUT
SYSCTL_CLKOUTSRC_MAINSYSCLK	Main system clock for CLKOUT
SYSCTL_CLKOUTSRC_CPU	CPU clock as CLKOUT source
SYSCTL_CLKOUTSRC_MAINOSC	Main oscillator clock as CLKOUT source
SYSCTL_CLKOUTSRC_IRC	IRC oscillator clock as CLKOUT source
SYSCTL_CLKOUTSRC_USB	USB clock as CLKOUT source
SYSCTL_CLKOUTSRC_RTC	RTC clock as CLKOUT source
SYSCTL_CLKOUTSRC_SPIFI	SPIFI clock as CLKOUT source
SYSCTL_CLKOUTSRC_WATCHDOGOSC	Watchdog oscillator as CLKOUT source
SYSCTL_CLKOUTSRC_RESERVED3
SYSCTL_CLKOUTSRC_IRC	Internal oscillator for CLKOUT
SYSCTL_CLKOUTSRC_SYSOSC	System oscillator for CLKOUT
SYSCTL_CLKOUTSRC_WDTOSC	Watchdog oscillator for CLKOUT
SYSCTL_CLKOUTSRC_MAINSYSCLK	Main system clock for CLKOUT

Definition at line 447 of file clock_11xx.h.

enum CHIP_SYSCTL_CLOCK_T

System and peripheral clocks

Enumerator:

SYSCTL_CLOCK_SYS	0: System clock
SYSCTL_CLOCK_ROM	1: ROM clock
SYSCTL_CLOCK_RAM	2: RAM clock
SYSCTL_CLOCK_FLASHREG	3: FLASH register interface clock
SYSCTL_CLOCK_FLASHARRAY	4: FLASH array access clock
SYSCTL_CLOCK_I2C	5: I2C clock, not on LPC110x
SYSCTL_CLOCK_GPIO	6: GPIO clock
SYSCTL_CLOCK_CT16B0	7: 16-bit Counter/timer 0 clock
SYSCTL_CLOCK_CT16B1	8: 16-bit Counter/timer 1 clock
SYSCTL_CLOCK_CT32B0	9: 32-bit Counter/timer 0 clock
SYSCTL_CLOCK_CT32B1	10: 32-bit Counter/timer 1 clock
SYSCTL_CLOCK_SSP0	11: SSP0 clock
SYSCTL_CLOCK_UART0	12: UART0 clock
SYSCTL_CLOCK_ADC	13: ADC clock
SYSCTL_CLOCK_RESERVED14	14: Reserved
SYSCTL_CLOCK_WDT	15: Watchdog timer clock
SYSCTL_CLOCK_IOCON	16: IOCON block clock
SYSCTL_CLOCK_RESERVED17	17: Reserved
SYSCTL_CLOCK_SSP1	18: SSP1 clock, LPC11A/C/E/Uxx only
SYSCTL_CLOCK_PINT	19: GPIO Pin int register interface clock, LPC11A/E/Uxx only
SYSCTL_CLOCK_RESERVED20	20: Reserved
SYSCTL_CLOCK_RESERVED21	21: Reserved
SYSCTL_CLOCK_RESERVED22	22: Reserved
SYSCTL_CLOCK_P0INT	23: GPIO GROUP1 interrupt register clock, LPC11Axx only
SYSCTL_CLOCK_GROUP0INT	23: GPIO GROUP0 interrupt register interface clock, LPC11E/Uxx only
SYSCTL_CLOCK_P1INT	24: GPIO GROUP1 interrupt register clock, LPC11Axx only
SYSCTL_CLOCK_GROUP1INT	24: GPIO GROUP1 interrupt register interface clock, LPC11E/Uxx only
SYSCTL_CLOCK_RESERVED25	25: Reserved
SYSCTL_CLOCK_RESERVED26	26: Reserved
SYSCTL_CLOCK_RESERVED27	27: Reserved
SYSCTL_CLOCK_SYS	0: System clock
SYSCTL_CLOCK_ROM	1: ROM clock
SYSCTL_CLOCK_RAM	2: RAM clock
SYSCTL_CLOCK_FLASHREG	3: FLASH register interface clock
SYSCTL_CLOCK_FLASHARRAY	4: FLASH array access clock
SYSCTL_CLOCK_I2C	5: I2C clock
SYSCTL_CLOCK_GPIO	6: GPIO clock
SYSCTL_CLOCK_CT16B0	7: 16-bit Counter/timer 0 clock
SYSCTL_CLOCK_CT16B1	8: 16-bit Counter/timer 1 clock
SYSCTL_CLOCK_CT32B0	9: 32-bit Counter/timer 0 clock
SYSCTL_CLOCK_CT32B1	10: 32-bit Counter/timer 1 clock
SYSCTL_CLOCK_SSP0	11: SSP0 clock
SYSCTL_CLOCK_UART0	12: UART0 clock
SYSCTL_CLOCK_ADC	13: ADC clock
SYSCTL_CLOCK_USB	14: USBREG clock
SYSCTL_CLOCK_WDT	15: Watchdog timer clock
SYSCTL_CLOCK_IOCON	16: IOCON block clock
SYSCTL_CLOCK_RESERVED17	17: Reserved
SYSCTL_CLOCK_SSP1	18: SSP1 clock
SYSCTL_CLOCK_LCD	LCD clock
SYSCTL_CLOCK_TIMER0	Timer 0 clock
SYSCTL_CLOCK_TIMER1	Timer 1 clock
SYSCTL_CLOCK_UART0	UART 0 clock
SYSCTL_CLOCK_UART1	UART 1 clock
SYSCTL_CLOCK_PWM0	PWM0 clock
SYSCTL_CLOCK_PWM1	PWM1 clock
SYSCTL_CLOCK_I2C0	I2C0 clock
SYSCTL_CLOCK_UART4	UART 4 clock
SYSCTL_CLOCK_RTC	RTC clock
SYSCTL_CLOCK_SSP1	SSP1 clock
SYSCTL_CLOCK_EMC	EMC clock
SYSCTL_CLOCK_ADC	ADC clock
SYSCTL_CLOCK_CAN1	CAN1 clock
SYSCTL_CLOCK_CAN2	CAN2 clock
SYSCTL_CLOCK_GPIO	GPIO clock
SYSCTL_CLOCK_SPIFI	SPIFI clock
SYSCTL_CLOCK_MCPWM	MCPWM clock
SYSCTL_CLOCK_QEI	QEI clock
SYSCTL_CLOCK_I2C1	I2C1 clock
SYSCTL_CLOCK_SSP2	SSP2 clock
SYSCTL_CLOCK_SSP0	SSP0 clock
SYSCTL_CLOCK_TIMER2	Timer 2 clock
SYSCTL_CLOCK_TIMER3	Timer 3 clock
SYSCTL_CLOCK_UART2	UART 2 clock
SYSCTL_CLOCK_UART3	UART 3 clock
SYSCTL_CLOCK_I2C2	I2C2 clock
SYSCTL_CLOCK_I2S	I2S clock
SYSCTL_CLOCK_SDC	SD Card interface clock
SYSCTL_CLOCK_GPDMA	GP DMA clock
SYSCTL_CLOCK_ENET	EMAC/Ethernet clock
SYSCTL_CLOCK_USB	USB clock
SYSCTL_CLOCK_RSVD32
SYSCTL_CLOCK_RSVD33
SYSCTL_CLOCK_RSVD34
SYSCTL_CLOCK_RSVD35
SYSCTL_CLOCK_SYS	System clock
SYSCTL_CLOCK_ROM	ROM clock
SYSCTL_CLOCK_RAM	RAM clock
SYSCTL_CLOCK_FLASHREG	FLASH register interface clock
SYSCTL_CLOCK_FLASH	FLASH array access clock
SYSCTL_CLOCK_I2C	I2C clock
SYSCTL_CLOCK_GPIO	GPIO clock
SYSCTL_CLOCK_SWM	Switch matrix clock
SYSCTL_CLOCK_SCT	State configurable timer clock
SYSCTL_CLOCK_WKT	Self wake-up timer clock
SYSCTL_CLOCK_MRT	Multi-rate timer clock
SYSCTL_CLOCK_SPI0	SPI0 clock
SYSCTL_CLOCK_SPI1	SPI01 clock
SYSCTL_CLOCK_CRC	CRC clock
SYSCTL_CLOCK_UART0	UART0 clock
SYSCTL_CLOCK_UART1	UART1 clock
SYSCTL_CLOCK_UART2	UART2 clock
SYSCTL_CLOCK_WWDT	Watchdog clock
SYSCTL_CLOCK_IOCON	IOCON clock
SYSCTL_CLOCK_ACOMP	Analog comparator clock

Definition at line 245 of file clock_11xx.h.

enum CHIP_SYSCTL_MAINCLKSRC_T

Clock sources for main system clock

Enumerator:

SYSCTL_MAINCLKSRC_IRC	Internal oscillator
SYSCTL_MAINCLKSRC_PLLIN	System PLL input
SYSCTL_MAINCLKSRC_LFOSC	LF oscillator rate (11Axx only)
SYSCTL_MAINCLKSRC_WDTOSC	Watchdog oscillator rate
SYSCTL_MAINCLKSRC_PLLOUT	System PLL output
SYSCTL_MAINCLKSRC_IRC	Internal oscillator
SYSCTL_MAINCLKSRC_PLLIN	System PLL input
SYSCTL_MAINCLKSRC_WDTOSC	Watchdog oscillator rate
SYSCTL_MAINCLKSRC_PLLOUT	System PLL output
SYSCTL_MAINCLKSRC_IRC	Internal oscillator
SYSCTL_MAINCLKSRC_PLLIN	System PLL input
SYSCTL_MAINCLKSRC_WDTOSC	Watchdog oscillator rate
SYSCTL_MAINCLKSRC_PLLOUT	System PLL output

Definition at line 204 of file clock_11xx.h.

enum CHIP_SYSCTL_PLLCLKSRC_T

Clock sources for system and USB PLLs

Enumerator:

SYSCTL_PLLCLKSRC_IRC	Internal oscillator in
SYSCTL_PLLCLKSRC_MAINOSC	Crystal (main) oscillator in
SYSCTL_PLLCLKSRC_RESERVED1	Reserved
SYSCTL_PLLCLKSRC_RESERVED2	Reserved
SYSCTL_PLLCLKSRC_IRC	Internal oscillator in
SYSCTL_PLLCLKSRC_SYSOSC	Crystal (main) oscillator in
SYSCTL_PLLCLKSRC_RESERVED1	Reserved
SYSCTL_PLLCLKSRC_RESERVED2	Reserved
SYSCTL_PLLCLKSRC_IRC	PLL is sourced from the internal oscillator (IRC)
SYSCTL_PLLCLKSRC_MAINOSC	PLL is sourced from the main oscillator
SYSCTL_PLLCLKSRC_RESERVED1
SYSCTL_PLLCLKSRC_RESERVED2
SYSCTL_PLLCLKSRC_IRC	Internal oscillator
SYSCTL_PLLCLKSRC_SYSOSC	Crystal (system) oscillator
SYSCTL_PLLCLKSRC_RESERVED
SYSCTL_PLLCLKSRC_EXT_CLKIN	External clock input

Definition at line 88 of file clock_11xx.h.

enum CHIP_WDTLFO_OSC_T

Watchdog and low frequency oscillator frequencies plus or minus 40%

Enumerator:

WDTLFO_OSC_ILLEGAL
WDTLFO_OSC_0_60	0.6 MHz watchdog/LFO rate
WDTLFO_OSC_1_05	1.05 MHz watchdog/LFO rate
WDTLFO_OSC_1_40	1.4 MHz watchdog/LFO rate
WDTLFO_OSC_1_75	1.75 MHz watchdog/LFO rate
WDTLFO_OSC_2_10	2.1 MHz watchdog/LFO rate
WDTLFO_OSC_2_40	2.4 MHz watchdog/LFO rate
WDTLFO_OSC_2_70	2.7 MHz watchdog/LFO rate
WDTLFO_OSC_3_00	3.0 MHz watchdog/LFO rate
WDTLFO_OSC_3_25	3.25 MHz watchdog/LFO rate
WDTLFO_OSC_3_50	3.5 MHz watchdog/LFO rate
WDTLFO_OSC_3_75	3.75 MHz watchdog/LFO rate
WDTLFO_OSC_4_00	4.0 MHz watchdog/LFO rate
WDTLFO_OSC_4_20	4.2 MHz watchdog/LFO rate
WDTLFO_OSC_4_40	4.4 MHz watchdog/LFO rate
WDTLFO_OSC_4_60	4.6 MHz watchdog/LFO rate
WDTLFO_OSC_ILLEGAL
WDTLFO_OSC_0_60	0.6 MHz watchdog/LFO rate
WDTLFO_OSC_1_05	1.05 MHz watchdog/LFO rate
WDTLFO_OSC_1_40	1.4 MHz watchdog/LFO rate
WDTLFO_OSC_1_75	1.75 MHz watchdog/LFO rate
WDTLFO_OSC_2_10	2.1 MHz watchdog/LFO rate
WDTLFO_OSC_2_40	2.4 MHz watchdog/LFO rate
WDTLFO_OSC_2_70	2.7 MHz watchdog/LFO rate
WDTLFO_OSC_3_00	3.0 MHz watchdog/LFO rate
WDTLFO_OSC_3_25	3.25 MHz watchdog/LFO rate
WDTLFO_OSC_3_50	3.5 MHz watchdog/LFO rate
WDTLFO_OSC_3_75	3.75 MHz watchdog/LFO rate
WDTLFO_OSC_4_00	4.0 MHz watchdog/LFO rate
WDTLFO_OSC_4_20	4.2 MHz watchdog/LFO rate
WDTLFO_OSC_4_40	4.4 MHz watchdog/LFO rate
WDTLFO_OSC_4_60	4.6 MHz watchdog/LFO rate
WDTLFO_OSC_ILLEGAL
WDTLFO_OSC_0_60	0.6 MHz watchdog/LFO rate
WDTLFO_OSC_1_05	1.05 MHz watchdog/LFO rate
WDTLFO_OSC_1_40	1.4 MHz watchdog/LFO rate
WDTLFO_OSC_1_75	1.75 MHz watchdog/LFO rate
WDTLFO_OSC_2_10	2.1 MHz watchdog/LFO rate
WDTLFO_OSC_2_40	2.4 MHz watchdog/LFO rate
WDTLFO_OSC_2_70	2.7 MHz watchdog/LFO rate
WDTLFO_OSC_3_00	3.0 MHz watchdog/LFO rate
WDTLFO_OSC_3_25	3.25 MHz watchdog/LFO rate
WDTLFO_OSC_3_50	3.5 MHz watchdog/LFO rate
WDTLFO_OSC_3_75	3.75 MHz watchdog/LFO rate
WDTLFO_OSC_4_00	4.0 MHz watchdog/LFO rate
WDTLFO_OSC_4_20	4.2 MHz watchdog/LFO rate
WDTLFO_OSC_4_40	4.4 MHz watchdog/LFO rate
WDTLFO_OSC_4_60	4.6 MHz watchdog/LFO rate

Definition at line 155 of file clock_11xx.h.

Function Documentation

STATIC INLINE void Chip_Clock_DisablePeriphClock ( CHIP_SYSCTL_CLOCK_T clk )

Disable a system or peripheral clock.

Disables power and clocking for a peripheral.

Parameters

clk	: Clock to disable

Returns: Nothing

Definition at line 322 of file clock_11xx.h.

STATIC INLINE void Chip_Clock_EnablePeriphClock ( CHIP_SYSCTL_CLOCK_T clk )

Enable a system or peripheral clock.

Enables power and clocking for a peripheral.

Parameters

clk	: Clock to enable

Returns: Nothing

Definition at line 312 of file clock_11xx.h.

STATIC INLINE uint32_t Chip_Clock_GetIntOscRate ( void )

Returns the internal oscillator (IRC) clock rate.

Returns: internal oscillator (IRC) clock rate

Definition at line 482 of file clock_11xx.h.

uint32_t Chip_Clock_GetMainClockRate ( void )

Return main clock rate.

Returns: main clock rate

Definition at line 248 of file clock_11xx.c.

STATIC INLINE CHIP_SYSCTL_MAINCLKSRC_T Chip_Clock_GetMainClockSource ( void )

Returns the main clock source.

Returns: Which clock is used for the core clock source?

Definition at line 225 of file clock_11xx.h.

STATIC INLINE uint32_t Chip_Clock_GetMainOscRate ( void )

Returns the main oscillator clock rate.

Returns: main oscillator clock rate

Definition at line 473 of file clock_11xx.h.

STATIC INLINE uint32_t Chip_Clock_GetSSP0ClockDiv ( void )

Return SSP0 divider.

Returns: divider for SSP0 clock

Note: A value of 0 means the clock is disabled.

Definition at line 344 of file clock_11xx.h.

uint32_t Chip_Clock_GetSystemClockRate ( void )

Return system clock rate.

Returns: system clock rate

Definition at line 281 of file clock_11xx.c.

uint32_t Chip_Clock_GetSystemPllInClockRate ( void )

Return System PLL input clock rate.

Returns: System PLL input clock rate

Definition at line 183 of file clock_11xx.c.

uint32_t Chip_Clock_GetSystemPllOutClockRate ( void )

Return System PLL output clock rate.

Returns: System PLL output clock rate

Definition at line 210 of file clock_11xx.c.

STATIC INLINE uint32_t Chip_Clock_GetUARTClockDiv ( void )

Return UART divider.

Returns: divider for UART clock

Note: A value of 0 means the clock is disabled.

Definition at line 366 of file clock_11xx.h.

uint32_t Chip_Clock_GetWDTOSCRate ( void )

Return estimated watchdog oscillator rate.

Returns: Estimated watchdog oscillator rate

Note: This rate is accurate to plus or minus 40%.

Definition at line 168 of file clock_11xx.c.

STATIC INLINE bool Chip_Clock_IsSystemPLLLocked ( void )

Read System PLL lock status.

Returns: true of the PLL is locked. false if not locked

Definition at line 80 of file clock_11xx.h.

void Chip_Clock_SetCLKOUTSource	(	CHIP_SYSCTL_CLKOUTSRC_T	src,
		uint32_t	div
	)

Set CLKOUT clock source and divider.

Parameters

src	: Clock source for CLKOUT
div	: divider for CLKOUT clock

Returns: Nothing

Note: Use 0 to disable, or a divider value of 1 to 255. The CLKOUT clock rate is the clock source divided by the divider. This function will also toggle the clock source update register to update the clock source.

Definition at line 157 of file clock_11xx.c.

void Chip_Clock_SetMainClockSource ( CHIP_SYSCTL_MAINCLKSRC_T src )

Set main system clock source.

Parameters

src	: Clock source for main system

Returns: Nothing

Note: This function will also toggle the clock source update register to update the clock source.

Definition at line 124 of file clock_11xx.c.

void Chip_Clock_SetPLLBypass	(	bool	bypass,
		bool	highfr
	)

Bypass System Oscillator and set oscillator frequency range.

Parameters

bypass	: Flag to bypass oscillator
highfr	: Flag to set oscillator range from 15-25 MHz

Returns: Nothing

Note: Sets the PLL input to bypass the oscillator. This would be used if an external clock that is not an oscillator is attached to the XTALIN pin.

Definition at line 98 of file clock_11xx.c.

STATIC INLINE void Chip_Clock_SetSSP0ClockDiv ( uint32_t div )

Set SSP0 divider.

Parameters

div	: divider for SSP0 clock

Returns: Nothing

Note: Use 0 to disable, or a divider value of 1 to 255. The SSP0 clock rate is the main system clock divided by this value.

Definition at line 334 of file clock_11xx.h.

STATIC INLINE void Chip_Clock_SetSysClockDiv ( uint32_t div )

Set system clock divider.

Parameters

div	: divider for system clock

Returns: Nothing

Note: Use 0 to disable, or a divider value of 1 to 255. The system clock rate is the main system clock divided by this value.

Definition at line 237 of file clock_11xx.h.

void Chip_Clock_SetSystemPllSource ( CHIP_SYSCTL_PLLCLKSRC_T src )

Set System PLL clock source.

Parameters

src	: Clock source for system PLL

Returns: Nothing

Note: This function will also toggle the clock source update register to update the clock source.

Definition at line 90 of file clock_11xx.c.

STATIC INLINE void Chip_Clock_SetUARTClockDiv ( uint32_t div )

Set UART divider clock.

Parameters

div	: divider for UART clock

Returns: Nothing

Note: Use 0 to disable, or a divider value of 1 to 255. The UART clock rate is the main system clock divided by this value.

Definition at line 356 of file clock_11xx.h.

STATIC INLINE void Chip_Clock_SetupSystemPLL	(	uint8_t	msel,
		uint8_t	psel
	)

Set System PLL divider values.

Parameters

msel	: PLL feedback divider value. M = msel + 1.
psel	: PLL post divider value. P = (1<<psel).

Returns: Nothing

Note: See the user manual for how to setup the PLL.

Definition at line 71 of file clock_11xx.h.

STATIC INLINE void Chip_Clock_SetWDTOSC	(	CHIP_WDTLFO_OSC_T	wdtclk,
		uint8_t	div
	)

Setup Watchdog oscillator rate and divider.

Parameters

wdtclk	: Selected watchdog clock rate
div	: Watchdog divider value, even value between 2 and 64

Returns: Nothing

Note: Watchdog rate = selected rate divided by divider rate

Definition at line 181 of file clock_11xx.h.

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