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LPCOpen Platform for NXP LPC Microcontrollers
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IP: Ethernet register block and driver (002)
IP drivers: Common drivers used on multiple NXP devices

Detailed Description

This MAC/Ethernet driver provides hardware support for controllers found in LPC2xxx, LPC17xx/40xx, and LPC32xx devices.

Data Structures

struct  IP_ENET_002_MAC_T
 Ethernet (002) MAC register block structure. More...
 
struct  IP_ENET_002_TRANSFER_INFO_T
 Ethernet Transfer register Block Structure. More...
 
struct  IP_ENET_002_CONTROL_T
 Ethernet Control register block structure. More...
 
struct  IP_ENET_002_RXFILTER_T
 Ethernet Receive Filter register block structure. More...
 
struct  IP_ENET_002_MODULE_CTRL_T
 Ethernet Module Control register block structure. More...
 
struct  IP_ENET_002_T
 Ethernet register block structure. More...
 
struct  IP_ENET_002_RXDESC_T
 RX Descriptor structure. More...
 
struct  IP_ENET_002_RXSTAT_T
 RX Status structure. More...
 
struct  IP_ENET_002_TXDESC_T
 TX Descriptor structure. More...
 
struct  IP_ENET_002_TXSTAT_T
 TX Status structure. More...
 

Macros

#define ENET_MAC1_MASK   0xcf1f
 MAC Configuration Register 1 bit definitions.
 
#define ENET_MAC1_RXENABLE   0x00000001
 
#define ENET_MAC1_PARF   0x00000002
 
#define ENET_MAC1_RXFLOWCTRL   0x00000004
 
#define ENET_MAC1_TXFLOWCTRL   0x00000008
 
#define ENET_MAC1_LOOPBACK   0x00000010
 
#define ENET_MAC1_RESETTX   0x00000100
 
#define ENET_MAC1_RESETMCSTX   0x00000200
 
#define ENET_MAC1_RESETRX   0x00000400
 
#define ENET_MAC1_RESETMCSRX   0x00000800
 
#define ENET_MAC1_SIMRESET   0x00004000
 
#define ENET_MAC1_SOFTRESET   0x00008000
 
#define ENET_MAC2_MASK   0x73ff
 MAC Configuration Register 2 bit definitions.
 
#define ENET_MAC2_FULLDUPLEX   0x00000001
 
#define ENET_MAC2_FLC   0x00000002
 
#define ENET_MAC2_HFEN   0x00000004
 
#define ENET_MAC2_DELAYEDCRC   0x00000008
 
#define ENET_MAC2_CRCEN   0x00000010
 
#define ENET_MAC2_PADCRCEN   0x00000020
 
#define ENET_MAC2_VLANPADEN   0x00000040
 
#define ENET_MAC2_AUTODETPADEN   0x00000080
 
#define ENET_MAC2_PPENF   0x00000100
 
#define ENET_MAC2_LPENF   0x00000200
 
#define ENET_MAC2_NOBACKOFF   0x00001000
 
#define ENET_MAC2_BP_NOBACKOFF   0x00002000
 
#define ENET_MAC2_EXCESSDEFER   0x00004000
 
#define ENET_IPGT_BTOBINTEGAP(n)   ((n) & 0x7F)
 Back-to-Back Inter-Packet-Gap Register bit definitions.
 
#define ENET_IPGT_FULLDUPLEX   (ENET_IPGT_BTOBINTEGAP(0x15))
 
#define ENET_IPGT_HALFDUPLEX   (ENET_IPGT_BTOBINTEGAP(0x12))
 
#define ENET_IPGR_NBTOBINTEGAP2(n)   ((n) & 0x7F)
 Non Back-to-Back Inter-Packet-Gap Register bit definitions.
 
#define ENET_IPGR_P2_DEF   (ENET_IPGR_NBTOBINTEGAP2(0x12))
 
#define ENET_IPGR_NBTOBINTEGAP1(n)   (((n) & 0x7F) << 8)
 
#define ENET_IPGR_P1_DEF   ENET_IPGR_NBTOBINTEGAP1(0x0C)
 
#define ENET_CLRT_RETRANSMAX(n)   ((n) & 0x0F)
 Collision Window/Retry Register bit definitions.
 
#define ENET_CLRT_COLLWIN(n)   (((n) & 0x3F) << 8)
 
#define ENET_CLRT_DEF   ((ENET_CLRT_RETRANSMAX(0x0F)) | (ENET_CLRT_COLLWIN(0x37)))
 
#define ENET_MAXF_MAXFLEN(n)   ((n) & 0xFFFF)
 Maximum Frame Register bit definitions.
 
#define ENET_MAXF_MAXFLEN_DEF   (0x600)
 
#define ENET_SUPP_100Mbps_SPEED   0x00000100
 
#define ENET_TEST_SCPQ   0x00000001
 Test Register bit definitions.
 
#define ENET_TEST_TESTPAUSE   0x00000002
 
#define ENET_TEST_TESTBP   0x00000004
 
#define ENET_MCFG_SCANINC   0x00000001
 MII Management Configuration Register bit definitions.
 
#define ENET_MCFG_SUPPPREAMBLE   0x00000002
 
#define ENET_MCFG_CLOCKSEL(n)   (((n) & 0x0F) << 2)
 
#define ENET_MCFG_RES_MII   0x00008000
 
#define ENET_MCFG_RESETMIIMGMT   2500000UL
 
#define ENET_MCMD_READ   0x00000001
 MII Management Command Register bit definitions.
 
#define ENET_MCMD_SCAN   0x00000002
 
#define ENET_MII_WR_TOUT   0x00050000
 
#define ENET_MII_RD_TOUT   0x00050000
 
#define ENET_MADR_REGADDR(n)   ((n) & 0x1F)
 MII Management Address Register bit definitions.
 
#define ENET_MADR_PHYADDR(n)   (((n) & 0x1F) << 8)
 
#define ENET_MWTD_DATA(n)   ((n) & 0xFFFF)
 MII Management Write Data Register bit definitions.
 
#define ENET_MRDD_DATA(n)   ((n) & 0xFFFF)
 MII Management Read Data Register bit definitions.
 
#define ENET_MIND_BUSY   0x00000001
 MII Management Indicators Register bit definitions.
 
#define ENET_MIND_SCANNING   0x00000002
 
#define ENET_MIND_NOTVALID   0x00000004
 
#define ENET_MIND_MIILINKFAIL   0x00000008
 
#define ENET_COMMAND_RXENABLE   0x00000001
 Command Register bit definitions.
 
#define ENET_COMMAND_TXENABLE   0x00000002
 
#define ENET_COMMAND_REGRESET   0x00000008
 
#define ENET_COMMAND_TXRESET   0x00000010
 
#define ENET_COMMAND_RXRESET   0x00000020
 
#define ENET_COMMAND_PASSRUNTFRAME   0x00000040
 
#define ENET_COMMAND_PASSRXFILTER   0x00000080
 
#define ENET_COMMAND_TXFLOWCONTROL   0x00000100
 
#define ENET_COMMAND_RMII   0x00000200
 
#define ENET_COMMAND_FULLDUPLEX   0x00000400
 
#define ENET_STATUS_RXSTATUS   0x00000001
 Status Register bit definitions.
 
#define ENET_STATUS_TXSTATUS   0x00000002
 
#define ENET_TSV0_CRCERR   0x00000001
 Transmit Status Vector 0 Register bit definitions.
 
#define ENET_TSV0_LCE   0x00000002
 
#define ENET_TSV0_LOR   0x00000004
 
#define ENET_TSV0_DONE   0x00000008
 
#define ENET_TSV0_MULTICAST   0x00000010
 
#define ENET_TSV0_BROADCAST   0x00000020
 
#define ENET_TSV0_PACKETDEFER   0x00000040
 
#define ENET_TSV0_EXDF   0x00000080
 
#define ENET_TSV0_EXCOL   0x00000100
 
#define ENET_TSV0_LCOL   0x00000200
 
#define ENET_TSV0_GIANT   0x00000400
 
#define ENET_TSV0_UNDERRUN   0x00000800
 
#define ENET_TSV0_TOTALBYTES   0x0FFFF000
 
#define ENET_TSV0_CONTROLFRAME   0x10000000
 
#define ENET_TSV0_PAUSE   0x20000000
 
#define ENET_TSV0_BACKPRESSURE   0x40000000
 
#define ENET_TSV0_VLAN   0x80000000
 
#define ENET_TSV1_TBC   0x0000FFFF
 Transmit Status Vector 0 Register bit definitions.
 
#define ENET_TSV1_TCC   0x000F0000
 
#define ENET_RSV_RBC   0x0000FFFF
 Receive Status Vector Register bit definitions.
 
#define ENET_RSV_PPI   0x00010000
 
#define ENET_RSV_RXDVSEEN   0x00020000
 
#define ENET_RSV_CESEEN   0x00040000
 
#define ENET_RSV_RCV   0x00080000
 
#define ENET_RSV_CRCERR   0x00100000
 
#define ENET_RSV_LCERR   0x00200000
 
#define ENET_RSV_LOR   0x00400000
 
#define ENET_RSV_ROK   0x00800000
 
#define ENET_RSV_MULTICAST   0x01000000
 
#define ENET_RSV_BROADCAST   0x02000000
 
#define ENET_RSV_DRIBBLENIBBLE   0x04000000
 
#define ENET_RSV_CONTROLFRAME   0x08000000
 
#define ENET_RSV_PAUSE   0x10000000
 
#define ENET_RSV_UO   0x20000000
 
#define ENET_RSV_VLAN   0x40000000
 
#define ENET_FLOWCONTROLCOUNTER_MC(n)   ((n) & 0xFFFF)
 Flow Control Counter Register bit definitions.
 
#define ENET_FLOWCONTROLCOUNTER_PT(n)   (((n) & 0xFFFF) << 16)
 
#define ENET_FLOWCONTROLSTATUS_MCC(n)   ((n) & 0xFFFF)
 Flow Control Status Register bit definitions.
 
#define ENET_RXFILTERCTRL_AUE   0x00000001
 Receive Filter Control Register bit definitions.
 
#define ENET_RXFILTERCTRL_ABE   0x00000002
 
#define ENET_RXFILTERCTRL_AME   0x00000004
 
#define ENET_RXFILTERCTRL_AUHE   0x00000008
 
#define ENET_RXFILTERCTRL_AMHE   0x00000010
 
#define ENET_RXFILTERCTRL_APE   0x00000020
 
#define ENET_RXFILTERCTRL_MPEW   0x00001000
 
#define ENET_RXFILTERCTRL_RFEW   0x00002000
 
#define ENET_RXFILTERWOLSTATUS_AUW   0x00000001
 Receive Filter WoL Status/Clear Register bit definitions.
 
#define ENET_RXFILTERWOLSTATUS_ABW   0x00000002
 
#define ENET_RXFILTERWOLSTATUS_AMW   0x00000004
 
#define ENET_RXFILTERWOLSTATUS_AUHW   0x00000008
 
#define ENET_RXFILTERWOLSTATUS_AMHW   0x00000010
 
#define ENET_RXFILTERWOLSTATUS_APW   0x00000020
 
#define ENET_RXFILTERWOLSTATUS_RFW   0x00000080
 
#define ENET_RXFILTERWOLSTATUS_MPW   0x00000100
 
#define ENET_RXFILTERWOLSTATUS_BITMASK   0x01BF
 
#define ENET_INT_RXOVERRUN   0x00000001
 Interrupt Status/Enable/Clear/Set Register bit definitions.
 
#define ENET_INT_RXERROR   0x00000002
 
#define ENET_INT_RXFINISHED   0x00000004
 
#define ENET_INT_RXDONE   0x00000008
 
#define ENET_INT_TXUNDERRUN   0x00000010
 
#define ENET_INT_TXERROR   0x00000020
 
#define ENET_INT_TXFINISHED   0x00000040
 
#define ENET_INT_TXDONE   0x00000080
 
#define ENET_INT_SOFT   0x00001000
 
#define ENET_INT_WAKEUP   0x00002000
 
#define ENET_POWERDOWN_PD   0x80000000
 Power Down Register bit definitions.
 
#define ENET_RCTRL_SIZE(n)   (((n) - 1) & 0x7FF)
 RX Descriptor Control structure type definition.
 
#define ENET_RCTRL_INT   0x80000000
 
#define ENET_RHASH_SA   0x000001FF
 RX Status Hash CRC Word definition.
 
#define ENET_RHASH_DA   0x001FF000
 
#define ENET_RINFO_SIZE(n)   (((n) & 0x7FF) + 1)
 
#define ENET_RINFO_CTRL_FRAME   0x00040000
 
#define ENET_RINFO_VLAN   0x00080000
 
#define ENET_RINFO_FAIL_FILT   0x00100000
 
#define ENET_RINFO_MCAST   0x00200000
 
#define ENET_RINFO_BCAST   0x00400000
 
#define ENET_RINFO_CRC_ERR   0x00800000
 
#define ENET_RINFO_SYM_ERR   0x01000000
 
#define ENET_RINFO_LEN_ERR   0x02000000
 
#define ENET_RINFO_RANGE_ERR   0x04000000
 
#define ENET_RINFO_ALIGN_ERR   0x08000000
 
#define ENET_RINFO_OVERRUN   0x10000000
 
#define ENET_RINFO_NO_DESCR   0x20000000
 
#define ENET_RINFO_LAST_FLAG   0x40000000
 
#define ENET_RINFO_ERR   0x80000000
 
#define ENET_RINFO_ERR_MASK
 
#define ENET_TCTRL_SIZE(n)   (((n) - 1) & 0x7FF)
 TX Descriptor Control structure type definition.
 
#define ENET_TCTRL_OVERRIDE   0x04000000
 
#define ENET_TCTRL_HUGE   0x08000000
 
#define ENET_TCTRL_PAD   0x10000000
 
#define ENET_TCTRL_CRC   0x20000000
 
#define ENET_TCTRL_LAST   0x40000000
 
#define ENET_TCTRL_INT   0x80000000
 
#define ENET_TINFO_COL_CNT   0x01E00000
 
#define ENET_TINFO_DEFER   0x02000000
 
#define ENET_TINFO_EXCESS_DEF   0x04000000
 
#define ENET_TINFO_EXCESS_COL   0x08000000
 
#define ENET_TINFO_LATE_COL   0x10000000
 
#define ENET_TINFO_UNDERRUN   0x20000000
 
#define ENET_TINFO_NO_DESCR   0x40000000
 
#define ENET_TINFO_ERR   0x80000000
 
#define ENET_ETH_MAX_FLEN   (1536)
 Maximum size of an ethernet buffer.
 

Enumerations

enum  IP_ENET_002_BUFF_STATUS_T { ENET_BUFF_EMPTY, ENET_BUFF_PARTIAL_FULL, ENET_BUFF_FULL }
 ENET Buffer status definition. More...
 

Functions

STATIC INLINE void IP_ENET_TXEnable (IP_ENET_002_T *pENET)
 Enables ethernet transmit.
 
STATIC INLINE void IP_ENET_TXDisable (IP_ENET_002_T *pENET)
 Disables ethernet transmit.
 
STATIC INLINE void IP_ENET_RXEnable (IP_ENET_002_T *pENET)
 Enables ethernet packet reception.
 
STATIC INLINE void IP_ENET_RXDisable (IP_ENET_002_T *pENET)
 Disables ethernet packet reception.
 
STATIC INLINE void IP_ENET_ResetTXLogic (IP_ENET_002_T *pENET)
 Reset Tx Logic.
 
STATIC INLINE void IP_ENET_ResetRXLogic (IP_ENET_002_T *pENET)
 Reset Rx Logic.
 
STATIC INLINE void IP_ENET_EnableRXFilter (IP_ENET_002_T *pENET, uint32_t mask)
 Enable Rx Filter.
 
STATIC INLINE void IP_ENET_DisableRXFilter (IP_ENET_002_T *pENET, uint32_t mask)
 Disable Rx Filter.
 
STATIC INLINE void IP_ENET_SetFullDuplex (IP_ENET_002_T *pENET)
 Sets full duplex for the ENET interface.
 
STATIC INLINE void IP_ENET_SetHalfDuplex (IP_ENET_002_T *pENET)
 Sets half duplex for the ENET interface.
 
STATIC INLINE void IP_ENET_Set100Mbps (IP_ENET_002_T *pENET)
 Selects 100Mbps for the current operating speed.
 
STATIC INLINE void IP_ENET_Set10Mbps (IP_ENET_002_T *pENET)
 Selects 10Mbps for the current operating speed.
 
STATIC INLINE uint16_t IP_ENET_GetTXProduceIndex (IP_ENET_002_T *pENET)
 Get the current Tx Produce Descriptor Index.
 
STATIC INLINE uint16_t IP_ENET_GetTXConsumeIndex (IP_ENET_002_T *pENET)
 Get the current Tx Consume Descriptor Index.
 
STATIC INLINE uint16_t IP_ENET_GetRXProduceIndex (IP_ENET_002_T *pENET)
 Get the current Rx Produce Descriptor Index.
 
STATIC INLINE uint16_t IP_ENET_GetRXConsumeIndex (IP_ENET_002_T *pENET)
 Get the current Rx Consume Descriptor Index.
 
STATIC INLINE void IP_ENET_EnableInt (IP_ENET_002_T *pENET, uint32_t mask)
 Enable ENET interrupts.
 
STATIC INLINE void IP_ENET_DisableInt (IP_ENET_002_T *pENET, uint32_t mask)
 Disable ENET interrupts.
 
STATIC INLINE uint32_t IP_ENET_GetIntStatus (IP_ENET_002_T *pENET)
 Get the interrupt status.
 
STATIC INLINE void IP_ENET_ClearIntStatus (IP_ENET_002_T *pENET, uint32_t mask)
 Clear the interrupt status.
 
void IP_ENET_Reset (IP_ENET_002_T *pENET)
 Resets the ethernet interface.
 
void IP_ENET_SetADDR (IP_ENET_002_T *pENET, const uint8_t *macAddr)
 Sets the address of the interface.
 
void IP_ENET_Init (IP_ENET_002_T *pENET)
 Initialize ethernet interface.
 
void IP_ENET_SetupMII (IP_ENET_002_T *pENET, uint8_t div, uint8_t addr)
 Sets up the PHY link clock divider and PHY address.
 
void IP_ENET_DeInit (IP_ENET_002_T *pENET)
 De-initialize the ethernet interface.
 
void IP_ENET_StartMIIWrite (IP_ENET_002_T *pENET, uint8_t reg, uint16_t data)
 Starts a PHY write via the MII.
 
void IP_ENET_StartMIIRead (IP_ENET_002_T *pENET, uint8_t reg)
 Starts a PHY read via the MII.
 
bool IP_ENET_IsMIIBusy (IP_ENET_002_T *pENET)
 Returns MII link (PHY) busy status.
 
uint16_t IP_ENET_ReadMIIData (IP_ENET_002_T *pENET)
 Returns the value read from the PHY.
 
void IP_ENET_InitTxDescriptors (IP_ENET_002_T *pENET, IP_ENET_002_TXDESC_T *pDescs, IP_ENET_002_TXSTAT_T *pStatus, uint32_t descNum)
 Configures the initial ethernet transmit descriptors.
 
void IP_ENET_InitRxDescriptors (IP_ENET_002_T *pENET, IP_ENET_002_RXDESC_T *pDescs, IP_ENET_002_RXSTAT_T *pStatus, uint32_t descNum)
 Configures the initial ethernet receive descriptors.
 
IP_ENET_002_BUFF_STATUS_T IP_ENET_GetBufferStatus (uint16_t produceIndex, uint16_t consumeIndex, uint16_t buffSize)
 Get status for the descriptor list.
 
uint32_t IP_ENET_GetFillDescNum (uint16_t produceIndex, uint16_t consumeIndex, uint16_t buffSize)
 Get the number of descriptors filled.
 
STATIC INLINE uint32_t IP_ENET_GetFreeDescNum (uint16_t produceIndex, uint16_t consumeIndex, uint16_t buffSize)
 Get the number of free descriptors.
 
STATIC INLINE bool IP_ENET_IsTxFull (IP_ENET_002_T *pENET)
 Check if Tx buffer is full.
 
STATIC INLINE bool IP_ENET_IsRxEmpty (IP_ENET_002_T *pENET)
 Check if Rx buffer is empty.
 
uint16_t IP_ENET_IncTXProduceIndex (IP_ENET_002_T *pENET)
 Increase the current Tx Produce Descriptor Index.
 
uint16_t IP_ENET_IncRXConsumeIndex (IP_ENET_002_T *pENET)
 Increase the current Rx Consume Descriptor Index.
 

Macro Definition Documentation

#define ENET_CLRT_COLLWIN (   n)    (((n) & 0x3F) << 8)

Programmable field representing the slot time or collision window during which collisions occur in properly configured networks

Definition at line 213 of file enet_002.h.

#define ENET_CLRT_DEF   ((ENET_CLRT_RETRANSMAX(0x0F)) | (ENET_CLRT_COLLWIN(0x37)))

Default value for Collision Window / Retry register

Definition at line 216 of file enet_002.h.

#define ENET_CLRT_RETRANSMAX (   n)    ((n) & 0x0F)

Collision Window/Retry Register bit definitions.

Programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions

Definition at line 209 of file enet_002.h.

#define ENET_COMMAND_FULLDUPLEX   0x00000400

Full Duplex

Definition at line 288 of file enet_002.h.

#define ENET_COMMAND_PASSRUNTFRAME   0x00000040

Pass Runt Frames

Definition at line 284 of file enet_002.h.

#define ENET_COMMAND_PASSRXFILTER   0x00000080

Pass RX Filter

Definition at line 285 of file enet_002.h.

#define ENET_COMMAND_REGRESET   0x00000008

Reset Host Registers

Definition at line 281 of file enet_002.h.

#define ENET_COMMAND_RMII   0x00000200

Reduced MII Interface

Definition at line 287 of file enet_002.h.

#define ENET_COMMAND_RXENABLE   0x00000001

Command Register bit definitions.

Enable Receive

Definition at line 279 of file enet_002.h.

#define ENET_COMMAND_RXRESET   0x00000020

Reset Receive Datapath

Definition at line 283 of file enet_002.h.

#define ENET_COMMAND_TXENABLE   0x00000002

Enable Transmit

Definition at line 280 of file enet_002.h.

#define ENET_COMMAND_TXFLOWCONTROL   0x00000100

TX Flow Control

Definition at line 286 of file enet_002.h.

#define ENET_COMMAND_TXRESET   0x00000010

Reset Transmit Datapath

Definition at line 282 of file enet_002.h.

#define ENET_ETH_MAX_FLEN   (1536)

Maximum size of an ethernet buffer.

Definition at line 486 of file enet_002.h.

#define ENET_FLOWCONTROLCOUNTER_MC (   n)    ((n) & 0xFFFF)

Flow Control Counter Register bit definitions.

Mirror Counter

Definition at line 346 of file enet_002.h.

#define ENET_FLOWCONTROLCOUNTER_PT (   n)    (((n) & 0xFFFF) << 16)

Pause Timer

Definition at line 347 of file enet_002.h.

#define ENET_FLOWCONTROLSTATUS_MCC (   n)    ((n) & 0xFFFF)

Flow Control Status Register bit definitions.

Mirror Counter Current

Definition at line 352 of file enet_002.h.

#define ENET_INT_RXDONE   0x00000008

Receive Done

Definition at line 385 of file enet_002.h.

#define ENET_INT_RXERROR   0x00000002

Receive Error

Definition at line 383 of file enet_002.h.

#define ENET_INT_RXFINISHED   0x00000004

RX Finished Process Descriptors

Definition at line 384 of file enet_002.h.

#define ENET_INT_RXOVERRUN   0x00000001

Interrupt Status/Enable/Clear/Set Register bit definitions.

Overrun Error in RX Queue

Definition at line 382 of file enet_002.h.

#define ENET_INT_SOFT   0x00001000

Software Triggered Interrupt

Definition at line 390 of file enet_002.h.

#define ENET_INT_TXDONE   0x00000080

Transmit Done

Definition at line 389 of file enet_002.h.

#define ENET_INT_TXERROR   0x00000020

Transmit Error

Definition at line 387 of file enet_002.h.

#define ENET_INT_TXFINISHED   0x00000040

TX Finished Process Descriptors

Definition at line 388 of file enet_002.h.

#define ENET_INT_TXUNDERRUN   0x00000010

Transmit Underrun

Definition at line 386 of file enet_002.h.

#define ENET_INT_WAKEUP   0x00002000

Wakeup Event Interrupt

Definition at line 391 of file enet_002.h.

#define ENET_IPGR_NBTOBINTEGAP1 (   n)    (((n) & 0x7F) << 8)

Programmable field representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'

Definition at line 199 of file enet_002.h.

#define ENET_IPGR_NBTOBINTEGAP2 (   n)    ((n) & 0x7F)

Non Back-to-Back Inter-Packet-Gap Register bit definitions.

Programmable field representing the Non-Back-to-Back Inter-Packet-Gap

Definition at line 192 of file enet_002.h.

#define ENET_IPGR_P1_DEF   ENET_IPGR_NBTOBINTEGAP1(0x0C)

Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2

Definition at line 202 of file enet_002.h.

#define ENET_IPGR_P2_DEF   (ENET_IPGR_NBTOBINTEGAP2(0x12))

Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1

Definition at line 195 of file enet_002.h.

#define ENET_IPGT_BTOBINTEGAP (   n)    ((n) & 0x7F)

Back-to-Back Inter-Packet-Gap Register bit definitions.

Programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next

Definition at line 175 of file enet_002.h.

#define ENET_IPGT_FULLDUPLEX   (ENET_IPGT_BTOBINTEGAP(0x15))

Recommended value for Full Duplex of Programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next

Definition at line 180 of file enet_002.h.

#define ENET_IPGT_HALFDUPLEX   (ENET_IPGT_BTOBINTEGAP(0x12))

Recommended value for Half Duplex of Programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next

Definition at line 185 of file enet_002.h.

#define ENET_MAC1_LOOPBACK   0x00000010

Loop Back Mode

Definition at line 144 of file enet_002.h.

#define ENET_MAC1_MASK   0xcf1f

MAC Configuration Register 1 bit definitions.

MAC1 register mask

Definition at line 139 of file enet_002.h.

#define ENET_MAC1_PARF   0x00000002

Pass All Receive Frames

Definition at line 141 of file enet_002.h.

#define ENET_MAC1_RESETMCSRX   0x00000800

Reset MAC RX Control Sublayer

Definition at line 148 of file enet_002.h.

#define ENET_MAC1_RESETMCSTX   0x00000200

Reset MAC TX Control Sublayer

Definition at line 146 of file enet_002.h.

#define ENET_MAC1_RESETRX   0x00000400

Reset RX Logic

Definition at line 147 of file enet_002.h.

#define ENET_MAC1_RESETTX   0x00000100

Reset TX Logic

Definition at line 145 of file enet_002.h.

#define ENET_MAC1_RXENABLE   0x00000001

Receive Enable

Definition at line 140 of file enet_002.h.

#define ENET_MAC1_RXFLOWCTRL   0x00000004

RX Flow Control

Definition at line 142 of file enet_002.h.

#define ENET_MAC1_SIMRESET   0x00004000

Simulation Reset

Definition at line 149 of file enet_002.h.

#define ENET_MAC1_SOFTRESET   0x00008000

Soft Reset MAC

Definition at line 150 of file enet_002.h.

#define ENET_MAC1_TXFLOWCTRL   0x00000008

TX Flow Control

Definition at line 143 of file enet_002.h.

#define ENET_MAC2_AUTODETPADEN   0x00000080

Auto Detect Pad Enable

Definition at line 163 of file enet_002.h.

#define ENET_MAC2_BP_NOBACKOFF   0x00002000

Backoff Presurre / No Backoff

Definition at line 167 of file enet_002.h.

#define ENET_MAC2_CRCEN   0x00000010

Append CRC to every Frame

Definition at line 160 of file enet_002.h.

#define ENET_MAC2_DELAYEDCRC   0x00000008

Delayed CRC Mode

Definition at line 159 of file enet_002.h.

#define ENET_MAC2_EXCESSDEFER   0x00004000

Excess Defer

Definition at line 168 of file enet_002.h.

#define ENET_MAC2_FLC   0x00000002

Frame Length Checking

Definition at line 157 of file enet_002.h.

#define ENET_MAC2_FULLDUPLEX   0x00000001

Full-Duplex Mode

Definition at line 156 of file enet_002.h.

#define ENET_MAC2_HFEN   0x00000004

Huge Frame Enable

Definition at line 158 of file enet_002.h.

#define ENET_MAC2_LPENF   0x00000200

Long Preamble Enforcement

Definition at line 165 of file enet_002.h.

#define ENET_MAC2_MASK   0x73ff

MAC Configuration Register 2 bit definitions.

MAC2 register mask

Definition at line 155 of file enet_002.h.

#define ENET_MAC2_NOBACKOFF   0x00001000

No Backoff Algorithm

Definition at line 166 of file enet_002.h.

#define ENET_MAC2_PADCRCEN   0x00000020

Pad all Short Frames

Definition at line 161 of file enet_002.h.

#define ENET_MAC2_PPENF   0x00000100

Pure Preamble Enforcement

Definition at line 164 of file enet_002.h.

#define ENET_MAC2_VLANPADEN   0x00000040

VLAN Pad Enable

Definition at line 162 of file enet_002.h.

#define ENET_MADR_PHYADDR (   n)    (((n) & 0x1F) << 8)

PHY Address Field

Definition at line 256 of file enet_002.h.

#define ENET_MADR_REGADDR (   n)    ((n) & 0x1F)

MII Management Address Register bit definitions.

MII Register Address field

Definition at line 255 of file enet_002.h.

#define ENET_MAXF_MAXFLEN (   n)    ((n) & 0xFFFF)

Maximum Frame Register bit definitions.

Represents a maximum receive frame of 1536 octets

Definition at line 222 of file enet_002.h.

#define ENET_MAXF_MAXFLEN_DEF   (0x600)

Definition at line 223 of file enet_002.h.

#define ENET_MCFG_CLOCKSEL (   n)    (((n) & 0x0F) << 2)

Clock Select Field

Definition at line 240 of file enet_002.h.

#define ENET_MCFG_RES_MII   0x00008000

Reset MII Management Hardware

Definition at line 241 of file enet_002.h.

#define ENET_MCFG_RESETMIIMGMT   2500000UL

MII Clock max

Definition at line 242 of file enet_002.h.

#define ENET_MCFG_SCANINC   0x00000001

MII Management Configuration Register bit definitions.

Scan Increment PHY Address

Definition at line 238 of file enet_002.h.

#define ENET_MCFG_SUPPPREAMBLE   0x00000002

Suppress Preamble

Definition at line 239 of file enet_002.h.

#define ENET_MCMD_READ   0x00000001

MII Management Command Register bit definitions.

MII Read

Definition at line 247 of file enet_002.h.

#define ENET_MCMD_SCAN   0x00000002

MII Scan continuously

Definition at line 248 of file enet_002.h.

#define ENET_MII_RD_TOUT   0x00050000

MII Read timeout count

Definition at line 250 of file enet_002.h.

#define ENET_MII_WR_TOUT   0x00050000

MII Write timeout count

Definition at line 249 of file enet_002.h.

#define ENET_MIND_BUSY   0x00000001

MII Management Indicators Register bit definitions.

MII is Busy

Definition at line 271 of file enet_002.h.

#define ENET_MIND_MIILINKFAIL   0x00000008

MII Link Failed

Definition at line 274 of file enet_002.h.

#define ENET_MIND_NOTVALID   0x00000004

MII Read Data not valid

Definition at line 273 of file enet_002.h.

#define ENET_MIND_SCANNING   0x00000002

MII Scanning in Progress

Definition at line 272 of file enet_002.h.

#define ENET_MRDD_DATA (   n)    ((n) & 0xFFFF)

MII Management Read Data Register bit definitions.

Data field for MMI Management Read Data register

Definition at line 266 of file enet_002.h.

#define ENET_MWTD_DATA (   n)    ((n) & 0xFFFF)

MII Management Write Data Register bit definitions.

Data field for MMI Management Write Data register

Definition at line 261 of file enet_002.h.

#define ENET_POWERDOWN_PD   0x80000000

Power Down Register bit definitions.

Power Down MAC

Definition at line 396 of file enet_002.h.

#define ENET_RCTRL_INT   0x80000000

Generate RxDone Interrupt

Definition at line 410 of file enet_002.h.

#define ENET_RCTRL_SIZE (   n)    (((n) - 1) & 0x7FF)

RX Descriptor Control structure type definition.

Buffer size field

Definition at line 409 of file enet_002.h.

#define ENET_RHASH_DA   0x001FF000

Hash CRC for Destination Address

Definition at line 425 of file enet_002.h.

#define ENET_RHASH_SA   0x000001FF

RX Status Hash CRC Word definition.

Hash CRC for Source Address

Definition at line 424 of file enet_002.h.

#define ENET_RINFO_ALIGN_ERR   0x08000000

Alignment Error

Definition at line 438 of file enet_002.h.

#define ENET_RINFO_BCAST   0x00400000

Broadcast Frame

Definition at line 433 of file enet_002.h.

#define ENET_RINFO_CRC_ERR   0x00800000

CRC Error in Frame

Definition at line 434 of file enet_002.h.

#define ENET_RINFO_CTRL_FRAME   0x00040000

Control Frame

Definition at line 429 of file enet_002.h.

#define ENET_RINFO_ERR   0x80000000

Error Occured (OR of all errors)

Definition at line 442 of file enet_002.h.

#define ENET_RINFO_ERR_MASK
Value:
(ENET_RINFO_FAIL_FILT | ENET_RINFO_CRC_ERR | ENET_RINFO_SYM_ERR | \
ENET_RINFO_LEN_ERR | ENET_RINFO_ALIGN_ERR | ENET_RINFO_OVERRUN)

RX Error status mask

Definition at line 444 of file enet_002.h.

#define ENET_RINFO_FAIL_FILT   0x00100000

RX Filter Failed

Definition at line 431 of file enet_002.h.

#define ENET_RINFO_LAST_FLAG   0x40000000

Last Fragment in Frame

Definition at line 441 of file enet_002.h.

#define ENET_RINFO_LEN_ERR   0x02000000

Length Error

Definition at line 436 of file enet_002.h.

#define ENET_RINFO_MCAST   0x00200000

Multicast Frame

Definition at line 432 of file enet_002.h.

#define ENET_RINFO_NO_DESCR   0x20000000

No new Descriptor available

Definition at line 440 of file enet_002.h.

#define ENET_RINFO_OVERRUN   0x10000000

Receive overrun

Definition at line 439 of file enet_002.h.

#define ENET_RINFO_RANGE_ERR   0x04000000

Range Error (exceeded max. size)

Definition at line 437 of file enet_002.h.

#define ENET_RINFO_SIZE (   n)    (((n) & 0x7FF) + 1)

Data size in bytes

Definition at line 428 of file enet_002.h.

#define ENET_RINFO_SYM_ERR   0x01000000

Symbol Error from PHY

Definition at line 435 of file enet_002.h.

#define ENET_RINFO_VLAN   0x00080000

VLAN Frame

Definition at line 430 of file enet_002.h.

#define ENET_RSV_BROADCAST   0x02000000

Broadcast Frame

Definition at line 336 of file enet_002.h.

#define ENET_RSV_CESEEN   0x00040000

Carrier Event Previously Seen

Definition at line 329 of file enet_002.h.

#define ENET_RSV_CONTROLFRAME   0x08000000

Control Frame

Definition at line 338 of file enet_002.h.

#define ENET_RSV_CRCERR   0x00100000

CRC Error

Definition at line 331 of file enet_002.h.

#define ENET_RSV_DRIBBLENIBBLE   0x04000000

Dribble Nibble

Definition at line 337 of file enet_002.h.

#define ENET_RSV_LCERR   0x00200000

Length Check Error

Definition at line 332 of file enet_002.h.

#define ENET_RSV_LOR   0x00400000

Length Out of Range

Definition at line 333 of file enet_002.h.

#define ENET_RSV_MULTICAST   0x01000000

Multicast Frame

Definition at line 335 of file enet_002.h.

#define ENET_RSV_PAUSE   0x10000000

Pause Frame

Definition at line 339 of file enet_002.h.

#define ENET_RSV_PPI   0x00010000

Packet Previously Ignored

Definition at line 327 of file enet_002.h.

#define ENET_RSV_RBC   0x0000FFFF

Receive Status Vector Register bit definitions.

Receive Byte Count

Definition at line 326 of file enet_002.h.

#define ENET_RSV_RCV   0x00080000

Receive Code Violation

Definition at line 330 of file enet_002.h.

#define ENET_RSV_ROK   0x00800000

Frame Received OK

Definition at line 334 of file enet_002.h.

#define ENET_RSV_RXDVSEEN   0x00020000

RXDV Event Previously Seen

Definition at line 328 of file enet_002.h.

#define ENET_RSV_UO   0x20000000

Unsupported Opcode

Definition at line 340 of file enet_002.h.

#define ENET_RSV_VLAN   0x40000000

VLAN Frame

Definition at line 341 of file enet_002.h.

#define ENET_RXFILTERCTRL_ABE   0x00000002

Accept Broadcast Frames Enable

Definition at line 358 of file enet_002.h.

#define ENET_RXFILTERCTRL_AME   0x00000004

Accept Multicast Frames Enable

Definition at line 359 of file enet_002.h.

#define ENET_RXFILTERCTRL_AMHE   0x00000010

Accept Multicast Hash Filter Fram

Definition at line 361 of file enet_002.h.

#define ENET_RXFILTERCTRL_APE   0x00000020

Accept Perfect Match Enable

Definition at line 362 of file enet_002.h.

#define ENET_RXFILTERCTRL_AUE   0x00000001

Receive Filter Control Register bit definitions.

Accept Unicast Frames Enable

Definition at line 357 of file enet_002.h.

#define ENET_RXFILTERCTRL_AUHE   0x00000008

Accept Unicast Hash Filter Frames

Definition at line 360 of file enet_002.h.

#define ENET_RXFILTERCTRL_MPEW   0x00001000

Magic Packet Filter WoL Enable

Definition at line 363 of file enet_002.h.

#define ENET_RXFILTERCTRL_RFEW   0x00002000

Perfect Filter WoL Enable

Definition at line 364 of file enet_002.h.

#define ENET_RXFILTERWOLSTATUS_ABW   0x00000002

Broadcast Frame caused WoL

Definition at line 370 of file enet_002.h.

#define ENET_RXFILTERWOLSTATUS_AMHW   0x00000010

Multicast Hash Filter Frame WoL

Definition at line 373 of file enet_002.h.

#define ENET_RXFILTERWOLSTATUS_AMW   0x00000004

Multicast Frame caused WoL

Definition at line 371 of file enet_002.h.

#define ENET_RXFILTERWOLSTATUS_APW   0x00000020

Perfect Filter WoL

Definition at line 374 of file enet_002.h.

#define ENET_RXFILTERWOLSTATUS_AUHW   0x00000008

Unicast Hash Filter Frame WoL

Definition at line 372 of file enet_002.h.

#define ENET_RXFILTERWOLSTATUS_AUW   0x00000001

Receive Filter WoL Status/Clear Register bit definitions.

Unicast Frame caused WoL

Definition at line 369 of file enet_002.h.

#define ENET_RXFILTERWOLSTATUS_BITMASK   0x01BF

Receive Filter WoL Status/Clear bitmasl value

Definition at line 377 of file enet_002.h.

#define ENET_RXFILTERWOLSTATUS_MPW   0x00000100

Magic Packet Filter caused WoL

Definition at line 376 of file enet_002.h.

#define ENET_RXFILTERWOLSTATUS_RFW   0x00000080

RX Filter caused WoL

Definition at line 375 of file enet_002.h.

#define ENET_STATUS_RXSTATUS   0x00000001

Status Register bit definitions.

Receive Channel Active Status

Definition at line 293 of file enet_002.h.

#define ENET_STATUS_TXSTATUS   0x00000002

Transmit Channel Active Status

Definition at line 294 of file enet_002.h.

#define ENET_SUPP_100Mbps_SPEED   0x00000100

Reduced MII Logic Current Speed

Definition at line 226 of file enet_002.h.

#define ENET_TCTRL_CRC   0x20000000

Append a hardware CRC to Frame

Definition at line 462 of file enet_002.h.

#define ENET_TCTRL_HUGE   0x08000000

Enable Huge Frame

Definition at line 460 of file enet_002.h.

#define ENET_TCTRL_INT   0x80000000

Generate TxDone Interrupt

Definition at line 464 of file enet_002.h.

#define ENET_TCTRL_LAST   0x40000000

Last Descriptor for TX Frame

Definition at line 463 of file enet_002.h.

#define ENET_TCTRL_OVERRIDE   0x04000000

Override Default MAC Registers

Definition at line 459 of file enet_002.h.

#define ENET_TCTRL_PAD   0x10000000

Pad short Frames to 64 bytes

Definition at line 461 of file enet_002.h.

#define ENET_TCTRL_SIZE (   n)    (((n) - 1) & 0x7FF)

TX Descriptor Control structure type definition.

Size of data buffer in bytes

Definition at line 458 of file enet_002.h.

#define ENET_TEST_SCPQ   0x00000001

Test Register bit definitions.

Shortcut Pause Quanta

Definition at line 231 of file enet_002.h.

#define ENET_TEST_TESTBP   0x00000004

Test Back Pressure

Definition at line 233 of file enet_002.h.

#define ENET_TEST_TESTPAUSE   0x00000002

Test Pause

Definition at line 232 of file enet_002.h.

#define ENET_TINFO_COL_CNT   0x01E00000

Collision Count

Definition at line 474 of file enet_002.h.

#define ENET_TINFO_DEFER   0x02000000

Packet Deferred (not an error)

Definition at line 475 of file enet_002.h.

#define ENET_TINFO_ERR   0x80000000

Error Occured (OR of all errors)

Definition at line 481 of file enet_002.h.

#define ENET_TINFO_EXCESS_COL   0x08000000

Excessive Collision

Definition at line 477 of file enet_002.h.

#define ENET_TINFO_EXCESS_DEF   0x04000000

Excessive Deferral

Definition at line 476 of file enet_002.h.

#define ENET_TINFO_LATE_COL   0x10000000

Late Collision Occured

Definition at line 478 of file enet_002.h.

#define ENET_TINFO_NO_DESCR   0x40000000

No new Descriptor available

Definition at line 480 of file enet_002.h.

#define ENET_TINFO_UNDERRUN   0x20000000

Transmit Underrun

Definition at line 479 of file enet_002.h.

#define ENET_TSV0_BACKPRESSURE   0x40000000

Backpressure Method Applied

Definition at line 314 of file enet_002.h.

#define ENET_TSV0_BROADCAST   0x00000020

Broadcast Destination

Definition at line 304 of file enet_002.h.

#define ENET_TSV0_CONTROLFRAME   0x10000000

Control Frame

Definition at line 312 of file enet_002.h.

#define ENET_TSV0_CRCERR   0x00000001

Transmit Status Vector 0 Register bit definitions.

CRC error

Definition at line 299 of file enet_002.h.

#define ENET_TSV0_DONE   0x00000008

Tramsmission Completed

Definition at line 302 of file enet_002.h.

#define ENET_TSV0_EXCOL   0x00000100

Excessive Collision

Definition at line 307 of file enet_002.h.

#define ENET_TSV0_EXDF   0x00000080

Excessive Packet Deferral

Definition at line 306 of file enet_002.h.

#define ENET_TSV0_GIANT   0x00000400

Giant Frame

Definition at line 309 of file enet_002.h.

#define ENET_TSV0_LCE   0x00000002

Length Check Error

Definition at line 300 of file enet_002.h.

#define ENET_TSV0_LCOL   0x00000200

Late Collision Occured

Definition at line 308 of file enet_002.h.

#define ENET_TSV0_LOR   0x00000004

Length Out of Range

Definition at line 301 of file enet_002.h.

#define ENET_TSV0_MULTICAST   0x00000010

Multicast Destination

Definition at line 303 of file enet_002.h.

#define ENET_TSV0_PACKETDEFER   0x00000040

Packet Deferred

Definition at line 305 of file enet_002.h.

#define ENET_TSV0_PAUSE   0x20000000

Pause Frame

Definition at line 313 of file enet_002.h.

#define ENET_TSV0_TOTALBYTES   0x0FFFF000

Total Bytes Transferred

Definition at line 311 of file enet_002.h.

#define ENET_TSV0_UNDERRUN   0x00000800

Buffer Underrun

Definition at line 310 of file enet_002.h.

#define ENET_TSV0_VLAN   0x80000000

VLAN Frame

Definition at line 315 of file enet_002.h.

#define ENET_TSV1_TBC   0x0000FFFF

Transmit Status Vector 0 Register bit definitions.

Transmit Byte Count

Definition at line 320 of file enet_002.h.

#define ENET_TSV1_TCC   0x000F0000

Transmit Collision Count

Definition at line 321 of file enet_002.h.

Enumeration Type Documentation

enum IP_ENET_002_BUFF_STATUS_T

ENET Buffer status definition.

Enumerator:
ENET_BUFF_EMPTY 
ENET_BUFF_PARTIAL_FULL 
ENET_BUFF_FULL 

Definition at line 491 of file enet_002.h.

Function Documentation

STATIC INLINE void IP_ENET_ClearIntStatus ( IP_ENET_002_T *  pENET,
uint32_t  mask 
)

Clear the interrupt status.

Parameters
pENET: Pointer to selected ENET peripheral
mask: Interrupt mask (Or-ed bit values of ENET_INT_*)
Returns
Nothing

Definition at line 706 of file enet_002.h.

void IP_ENET_DeInit ( IP_ENET_002_T *  pENET)

De-initialize the ethernet interface.

Parameters
pENET: Pointer to selected ENET peripheral
Returns
Nothing

Definition at line 116 of file enet_002.c.

STATIC INLINE void IP_ENET_DisableInt ( IP_ENET_002_T *  pENET,
uint32_t  mask 
)

Disable ENET interrupts.

Parameters
pENET: Pointer to selected ENET peripheral
mask: Interrupt mask (Or-ed bit values of ENET_INT_*)
Returns
Nothing

Definition at line 685 of file enet_002.h.

STATIC INLINE void IP_ENET_DisableRXFilter ( IP_ENET_002_T *  pENET,
uint32_t  mask 
)

Disable Rx Filter.

Parameters
pENET: Pointer to selected ENET peripheral
mask: Filter mask (Or-ed bit values of ENET_RXFILTERCTRL_*)
Returns
Nothing

Definition at line 579 of file enet_002.h.

STATIC INLINE void IP_ENET_EnableInt ( IP_ENET_002_T *  pENET,
uint32_t  mask 
)

Enable ENET interrupts.

Parameters
pENET: Pointer to selected ENET peripheral
mask: Interrupt mask (Or-ed bit values of ENET_INT_*)
Returns
Nothing

Definition at line 674 of file enet_002.h.

STATIC INLINE void IP_ENET_EnableRXFilter ( IP_ENET_002_T *  pENET,
uint32_t  mask 
)

Enable Rx Filter.

Parameters
pENET: Pointer to selected ENET peripheral
mask: Filter mask (Or-ed bit values of ENET_RXFILTERCTRL_*)
Returns
Nothing

Definition at line 567 of file enet_002.h.

IP_ENET_002_BUFF_STATUS_T IP_ENET_GetBufferStatus ( uint16_t  produceIndex,
uint16_t  consumeIndex,
uint16_t  buffSize 
)

Get status for the descriptor list.

Parameters
produceIndex: Produce Index
consumeIndex: Consume Index
buffSize: Buffer size
Returns
Status (One of status value: ENET_BUFF_EMPTY/ENET_BUFF_FULL/ENET_BUFF_PARTIAL_FULL)

Definition at line 190 of file enet_002.c.

uint32_t IP_ENET_GetFillDescNum ( uint16_t  produceIndex,
uint16_t  consumeIndex,
uint16_t  buffSize 
)

Get the number of descriptors filled.

Parameters
produceIndex: Produce Index
consumeIndex: Consume Index
buffSize: Buffer size
Returns
the number of descriptors

Definition at line 212 of file enet_002.c.

STATIC INLINE uint32_t IP_ENET_GetFreeDescNum ( uint16_t  produceIndex,
uint16_t  consumeIndex,
uint16_t  buffSize 
)

Get the number of free descriptors.

Parameters
produceIndex: Produce Index
consumeIndex: Consume Index
buffSize: Buffer size
Returns
the number of descriptors

Definition at line 841 of file enet_002.h.

STATIC INLINE uint32_t IP_ENET_GetIntStatus ( IP_ENET_002_T *  pENET)

Get the interrupt status.

Parameters
pENET: Pointer to selected ENET peripheral
Returns
interrupt status (Or-ed bit values of ENET_INT_*)

Definition at line 695 of file enet_002.h.

STATIC INLINE uint16_t IP_ENET_GetRXConsumeIndex ( IP_ENET_002_T *  pENET)

Get the current Rx Consume Descriptor Index.

Parameters
pENET: Pointer to selected ENET peripheral
Returns
Rx Consume Index

Definition at line 663 of file enet_002.h.

STATIC INLINE uint16_t IP_ENET_GetRXProduceIndex ( IP_ENET_002_T *  pENET)

Get the current Rx Produce Descriptor Index.

Parameters
pENET: Pointer to selected ENET peripheral
Returns
Rx Produce Index

Definition at line 653 of file enet_002.h.

STATIC INLINE uint16_t IP_ENET_GetTXConsumeIndex ( IP_ENET_002_T *  pENET)

Get the current Tx Consume Descriptor Index.

Parameters
pENET: Pointer to selected ENET peripheral
Returns
Tx Consume Index

Definition at line 643 of file enet_002.h.

STATIC INLINE uint16_t IP_ENET_GetTXProduceIndex ( IP_ENET_002_T *  pENET)

Get the current Tx Produce Descriptor Index.

Parameters
pENET: Pointer to selected ENET peripheral
Returns
Tx Produce Index

Definition at line 633 of file enet_002.h.

uint16_t IP_ENET_IncRXConsumeIndex ( IP_ENET_002_T *  pENET)

Increase the current Rx Consume Descriptor Index.

Parameters
pENET: Pointer to selected ENET peripheral
Returns
The new index value

Definition at line 243 of file enet_002.c.

uint16_t IP_ENET_IncTXProduceIndex ( IP_ENET_002_T *  pENET)

Increase the current Tx Produce Descriptor Index.

Parameters
pENET: Pointer to selected ENET peripheral
Returns
The new index value

Definition at line 227 of file enet_002.c.

void IP_ENET_Init ( IP_ENET_002_T *  pENET)

Initialize ethernet interface.

Parameters
pENET: Pointer to selected ENET peripheral
Returns
Nothing
Note
Performs basic initialization of the ethernet interface in a default state. This is enough to place the interface in a usable state, but may require more setup outside this function.

Definition at line 75 of file enet_002.c.

void IP_ENET_InitRxDescriptors ( IP_ENET_002_T *  pENET,
IP_ENET_002_RXDESC_T *  pDescs,
IP_ENET_002_RXSTAT_T *  pStatus,
uint32_t  descNum 
)

Configures the initial ethernet receive descriptors.

Parameters
pENET: Pointer to selected ENET peripheral
pDescs: Pointer to TX descriptor list
pStatus: Pointer to TX status list
descNum: Number of desciptors
Returns
Nothing

Definition at line 177 of file enet_002.c.

void IP_ENET_InitTxDescriptors ( IP_ENET_002_T *  pENET,
IP_ENET_002_TXDESC_T *  pDescs,
IP_ENET_002_TXSTAT_T *  pStatus,
uint32_t  descNum 
)

Configures the initial ethernet transmit descriptors.

Parameters
pENET: Pointer to selected ENET peripheral
pDescs: Pointer to TX descriptor list
pStatus: Pointer to TX status list
descNum: Number of desciptors
Returns
Nothing

Definition at line 164 of file enet_002.c.

bool IP_ENET_IsMIIBusy ( IP_ENET_002_T *  pENET)

Returns MII link (PHY) busy status.

Parameters
pENET: Pointer to selected ENET peripheral
Returns
Returns true if busy, otherwise false

Definition at line 147 of file enet_002.c.

STATIC INLINE bool IP_ENET_IsRxEmpty ( IP_ENET_002_T *  pENET)

Check if Rx buffer is empty.

Parameters
pENET: Pointer to selected ENET peripheral
Returns
true/false

Definition at line 863 of file enet_002.h.

STATIC INLINE bool IP_ENET_IsTxFull ( IP_ENET_002_T *  pENET)

Check if Tx buffer is full.

Parameters
pENET: Pointer to selected ENET peripheral
Returns
true/false

Definition at line 851 of file enet_002.h.

uint16_t IP_ENET_ReadMIIData ( IP_ENET_002_T *  pENET)

Returns the value read from the PHY.

Parameters
pENET: Pointer to selected ENET peripheral
Returns
Read value from PHY

Definition at line 157 of file enet_002.c.

void IP_ENET_Reset ( IP_ENET_002_T *  pENET)

Resets the ethernet interface.

Parameters
pENET: Pointer to selected ENET peripheral
Returns
Nothing
Note
Resets the ethernet interface. This should be called prior to IP_ENET_Init with a small delay after this call.

Definition at line 54 of file enet_002.c.

STATIC INLINE void IP_ENET_ResetRXLogic ( IP_ENET_002_T *  pENET)

Reset Rx Logic.

Parameters
pENET: Pointer to selected ENET peripheral
Returns
Nothing

Definition at line 556 of file enet_002.h.

STATIC INLINE void IP_ENET_ResetTXLogic ( IP_ENET_002_T *  pENET)

Reset Tx Logic.

Parameters
pENET: Pointer to selected ENET peripheral
Returns
Nothing

Definition at line 546 of file enet_002.h.

STATIC INLINE void IP_ENET_RXDisable ( IP_ENET_002_T *  pENET)

Disables ethernet packet reception.

Parameters
pENET: Pointer to selected ENET peripheral
Returns
Nothing

Definition at line 535 of file enet_002.h.

STATIC INLINE void IP_ENET_RXEnable ( IP_ENET_002_T *  pENET)

Enables ethernet packet reception.

Parameters
pENET: Pointer to selected ENET peripheral
Returns
Nothing

Definition at line 523 of file enet_002.h.

STATIC INLINE void IP_ENET_Set100Mbps ( IP_ENET_002_T *  pENET)

Selects 100Mbps for the current operating speed.

Parameters
pENET: Pointer to selected ENET peripheral
Returns
Nothing

Definition at line 613 of file enet_002.h.

STATIC INLINE void IP_ENET_Set10Mbps ( IP_ENET_002_T *  pENET)

Selects 10Mbps for the current operating speed.

Parameters
pENET: Pointer to selected ENET peripheral
Returns
Nothing

Definition at line 623 of file enet_002.h.

void IP_ENET_SetADDR ( IP_ENET_002_T *  pENET,
const uint8_t *  macAddr 
)

Sets the address of the interface.

Parameters
pENET: Pointer to selected ENET peripheral
macAddr: Pointer to the 6 bytes MAC address
Returns
Nothing

Definition at line 66 of file enet_002.c.

STATIC INLINE void IP_ENET_SetFullDuplex ( IP_ENET_002_T *  pENET)

Sets full duplex for the ENET interface.

Parameters
pENET: Pointer to selected ENET peripheral
Returns
Nothing

Definition at line 589 of file enet_002.h.

STATIC INLINE void IP_ENET_SetHalfDuplex ( IP_ENET_002_T *  pENET)

Sets half duplex for the ENET interface.

Parameters
pENET: Pointer to selected ENET peripheral
Returns
Nothing

Definition at line 601 of file enet_002.h.

void IP_ENET_SetupMII ( IP_ENET_002_T *  pENET,
uint8_t  div,
uint8_t  addr 
)

Sets up the PHY link clock divider and PHY address.

Parameters
pENET: Pointer to selected ENET peripheral
div: Divider value, may vary per chip
addr: PHY address, used with MII read and write
Returns
Nothing

Definition at line 103 of file enet_002.c.

void IP_ENET_StartMIIRead ( IP_ENET_002_T *  pENET,
uint8_t  reg 
)

Starts a PHY read via the MII.

Parameters
pENET: Pointer to selected ENET peripheral
reg: PHY register to read
Returns
Nothing
Note
Start a PHY read operation. Does not block, requires calling IP_ENET_IsMIIBusy to determine when read is complete and calling IP_ENET_ReadMIIData to get the data.

Definition at line 139 of file enet_002.c.

void IP_ENET_StartMIIWrite ( IP_ENET_002_T *  pENET,
uint8_t  reg,
uint16_t  data 
)

Starts a PHY write via the MII.

Parameters
pENET: Pointer to selected ENET peripheral
reg: PHY register to write
data: Data to write to PHY register
Returns
Nothing
Note
Start a PHY write operation. Does not block, requires calling IP_ENET_IsMIIBusy to determine when write is complete.

Definition at line 130 of file enet_002.c.

STATIC INLINE void IP_ENET_TXDisable ( IP_ENET_002_T *  pENET)

Disables ethernet transmit.

Parameters
pENET: Pointer to selected ENET peripheral
Returns
Nothing

Definition at line 513 of file enet_002.h.

STATIC INLINE void IP_ENET_TXEnable ( IP_ENET_002_T *  pENET)

Enables ethernet transmit.

Parameters
pENET: Pointer to selected ENET peripheral
Returns
Nothing

Definition at line 502 of file enet_002.h.