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LPCOpen Platform
v1.03
LPCOpen Platform for NXP LPC Microcontrollers
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LPCOpen Platform
v1.03
LPCOpen Platform for NXP LPC Microcontrollers
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Data Structures | |
| struct | IP_SPI_002_T |
| SPI register block structure. More... | |
| struct | IP_SPI_CONFIG_T |
| SPI Configure Struct. More... | |
| struct | IP_SPI_DELAY_CONFIG_T |
| SPI Delay Configure Struct. More... | |
Macros | |
| #define | SPI_CFG_BITMASK ((uint32_t) 0x1BD) |
| #define | SPI_CFG_SPI_EN ((uint32_t) (1 << 0)) |
| #define | SPI_CFG_SLAVE_EN ((uint32_t) 0) |
| #define | SPI_CFG_MASTER_EN ((uint32_t) (1 << 2)) |
| #define | SPI_CFG_MSB_FIRST_EN ((uint32_t) 0) /*Data will be transmitted and received in standard order (MSB first).*/ |
| #define | SPI_CFG_LSB_FIRST_EN ((uint32_t) (1 << 3))/*Data will be transmitted and received in reverse order (LSB first).*/ |
| #define | SPI_CFG_CPHA_FIRST ((uint32_t) (0)) /*Capture data on the first edge, Change data on the following edge*/ |
| #define | SPI_CFG_CPHA_SECOND ((uint32_t) (1 << 4)) /*Change data on the first edge, Capture data on the following edge*/ |
| #define | SPI_CFG_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/ |
| #define | SPI_CFG_CPOL_HI ((uint32_t) (1 << 5)) /* The rest state of the clock (between frames) is high.*/ |
| #define | SPI_CFG_LBM_EN ((uint32_t) (1 << 7)) |
| #define | SPI_CFG_SPOL_LO ((uint32_t) (0)) /* SSEL is active Low */ |
| #define | SPI_CFG_SPOL_HI ((uint32_t) (1 << 8)) /* SSEL is active High */ |
| #define | SPI_DLY_BITMASK ((uint32_t) 0xFFFF) |
| #define | SPI_DLY_PRE_DELAY(n) ((uint32_t) ((n) & 0x0F)) /* Time Unit: SPI clock time */ |
| #define | SPI_DLY_POST_DELAY(n) ((uint32_t) (((n) & 0x0F) << 4)) /* Time Unit: SPI clock time */ |
| #define | SPI_DLY_FRAME_DELAY(n) ((uint32_t) (((n) & 0x0F) << 8)) /* Time Unit: SPI clock time */ |
| #define | SPI_DLY_TRANSFER_DELAY(n) ((uint32_t) (((n) & 0x0F) << 12)) /* Time Unit: SPI clock time */ |
| #define | SPI_STAT_BITMASK ((uint32_t) 0x1FF) |
| #define | SPI_STAT_RXRDY ((uint32_t) (1 << 0)) /* Data is ready for read */ |
| #define | SPI_STAT_TXRDY ((uint32_t) (1 << 1)) /* Data may be written to transmit buffer */ |
| #define | SPI_STAT_RXOV ((uint32_t) (1 << 2)) /* Data comes while receiver buffer is in used */ |
| #define | SPI_STAT_TXUR ((uint32_t) (1 << 3)) /* There is no data to be sent in the next input clock */ |
| #define | SPI_STAT_SSA ((uint32_t) (1 << 4)) /* There is SSEL transition from deasserted to asserted */ |
| #define | SPI_STAT_SSD ((uint32_t) (1 << 5)) /* There is SSEL transition from asserted to deasserted */ |
| #define | SPI_STAT_STALLED ((uint32_t) (1 << 6)) /* SPI is currently in a stall condition. */ |
| #define | SPI_STAT_EOT ((uint32_t) (1 << 7)) /* The current frame is the last frame of the current transfer. */ |
| #define | SPI_STAT_LE ((uint32_t) (1 << 8)) /* SPI master function is fully idle. */ |
| #define | SPI_STAT_CLR_RXOV ((uint32_t) (1 << 2)) |
| #define | SPI_STAT_CLR_TXUR ((uint32_t) (1 << 3)) |
| #define | SPI_STAT_CLR_SSA ((uint32_t) (1 << 4)) |
| #define | SPI_STAT_CLR_SSD ((uint32_t) (1 << 5)) |
| #define | SPI_STAT_FORCE_EOT ((uint32_t) (1 << 7)) |
| #define | SPI_INTENSET_BITMASK ((uint32_t) 0x3F) |
| #define | SPI_INTENSET_RXDYEN ((uint32_t) (1 << 0)) |
| #define | SPI_INTENSET_TXDYEN ((uint32_t) (1 << 1)) |
| #define | SPI_INTENSET_RXOVEN ((uint32_t) (1 << 2)) |
| #define | SPI_INTENSET_TXUREN ((uint32_t) (1 << 3)) |
| #define | SPI_INTENSET_SSAEN ((uint32_t) (1 << 2)) |
| #define | SPI_INTENSET_SSDEN ((uint32_t) (1 << 2)) |
| #define | SPI_INTENCLR_BITMASK ((uint32_t) 0x3F) |
| #define | SPI_INTENCLR_RXDYEN ((uint32_t) (1 << 0)) |
| #define | SPI_INTENCLR_TXDYEN ((uint32_t) (1 << 1)) |
| #define | SPI_INTENCLR_RXOVEN ((uint32_t) (1 << 2)) |
| #define | SPI_INTENCLR_TXUREN ((uint32_t) (1 << 3)) |
| #define | SPI_INTENCLR_SSAEN ((uint32_t) (1 << 2)) |
| #define | SPI_INTENCLR_SSDEN ((uint32_t) (1 << 2)) |
| #define | SPI_RXDAT_BITMASK ((uint32_t) 0x11FFFF) |
| #define | SPI_RXDAT_DATA(n) ((uint32_t) ((n) & 0xFFFF)) |
| #define | SPI_RXDAT_RXSSELN_ACTIVE ((uint32_t) 0) /* SSEL is in active state */ |
| #define | SPI_RXDAT_RXSSELN_INACTIVE ((uint32_t) (1 << 16)) /* SSEL is in inactive state */ |
| #define | SPI_RXDAT_SOT ((uint32_t) (1 << 20)) /* This is the first frame received after SSEL is asserted */ |
| #define | SPI_TXDATCTL_BITMASK ((uint32_t) 0xF71FFFF) |
| #define | SPI_TXDATCTL_DATA(n) ((uint32_t) ((n) & 0xFFFF)) |
| #define | SPI_TXDATCTL_ASSERT_SSEL ((uint32_t) 0) |
| #define | SPI_TXDATCTL_DEASSERT_SSEL ((uint32_t) (1 << 16)) |
| #define | SPI_TXDATCTL_EOT ((uint32_t) (1 << 20)) /* This is the last frame of the current transfer */ |
| #define | SPI_TXDATCTL_EOF ((uint32_t) (1 << 21)) /* This is the last part of the current frame */ |
| #define | SPI_TXDATCTL_RXIGNORE ((uint32_t) (1 << 22)) /* Received data is ignored */ |
| #define | SPI_TXDATCTL_FLEN(n) ((uint32_t) (((n) & 0x0F) << 24)) /* Frame Length -1 */ |
| #define | SPI_TXDAT_DATA(n) ((uint32_t) ((n) & 0xFFFF)) |
| #define | SPI_TXCTL_BITMASK ((uint32_t) 0xF71FF00) |
| #define | SPI_TXCTL_ASSERT_SSEL ((uint32_t) 0) |
| #define | SPI_TXCTL_DEASSERT_SSEL ((uint32_t) (1 << 16)) |
| #define | SPI_TXCTL_EOT ((uint32_t) (1 << 20)) /* This is the last frame of the current transfer */ |
| #define | SPI_TXCTL_EOF ((uint32_t) (1 << 21)) /* This is the last part of the current frame */ |
| #define | SPI_TXCTL_RXIGNORE ((uint32_t) (1 << 22)) /* Received data is ignored */ |
| #define | SPI_TXCTL_FLEN(n) ((uint32_t) (((n) & 0x0F) << 24)) /* Frame Length -1 */ |
| #define | SPI_DIV_VAL(n) ((uint32_t) ((n) & 0xFFFF)) /* SPI_CLK = PCLK/(DIV_VAL+1)*/ |
| #define | SPI_INTSTAT_BITMASK ((uint32_t) 0x3F) |
| #define | SPI_INTSTAT_RXRDY ((uint32_t) (1 << 0)) /* Data is ready for read */ |
| #define | SPI_INTSTAT_TXRDY ((uint32_t) (1 << 1)) /* Data may be written to transmit buffer */ |
| #define | SPI_INTSTAT_RXOV ((uint32_t) (1 << 2)) /* Data comes while receiver buffer is in used */ |
| #define | SPI_INTSTAT_TXUR ((uint32_t) (1 << 3)) /* There is no data to be sent in the next input clock */ |
| #define | SPI_INTSTAT_SSA ((uint32_t) (1 << 4)) /* There is SSEL transition from deasserted to asserted */ |
| #define | SPI_INTSTAT_SSD ((uint32_t) (1 << 5)) /* There is SSEL transition from asserted to deasserted */ |
Enumerations | |
| enum | IP_SPI_MODE_T { SPI_MODE_MASTER = SPI_CR_MASTER_EN, SPI_MODE_SLAVE = SPI_CR_SLAVE_EN, SPI_MODE_MASTER = SPI_CFG_MASTER_EN, SPI_MODE_SLAVE = SPI_CFG_SLAVE_EN } |
| SPI Mode. More... | |
| enum | IP_SPI_CLOCK_MODE_T { SPI_CLOCK_CPHA0_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_FIRST, SPI_CLOCK_CPHA0_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_FIRST, SPI_CLOCK_CPHA1_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_SECOND, SPI_CLOCK_CPHA1_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_SECOND, SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0, SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0, SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1, SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1, SPI_CLOCK_CPHA0_CPOL0 = SPI_CFG_CPOL_LO | SPI_CFG_CPHA_FIRST, SPI_CLOCK_CPHA0_CPOL1 = SPI_CFG_CPOL_HI | SPI_CFG_CPHA_FIRST, SPI_CLOCK_CPHA1_CPOL0 = SPI_CFG_CPOL_LO | SPI_CFG_CPHA_SECOND, SPI_CLOCK_CPHA1_CPOL1 = SPI_CFG_CPOL_HI | SPI_CFG_CPHA_SECOND, SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0, SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0, SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1, SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1 } |
| SPI Clock Mode. More... | |
| enum | IP_SPI_DATA_ORDER_T { SPI_DATA_MSB_FIRST = SPI_CR_MSB_FIRST_EN, SPI_DATA_LSB_FIRST = SPI_CR_LSB_FIRST_EN, SPI_DATA_MSB_FIRST = SPI_CFG_MSB_FIRST_EN, SPI_DATA_LSB_FIRST = SPI_CFG_LSB_FIRST_EN } |
| SPI Data Order Mode. More... | |
| enum | IP_SPI_SSEL_POL_T { SPI_SSEL_ACTIVE_LO = SPI_CFG_SPOL_LO, SPI_SSEL_ACTIVE_HI = SPI_CFG_SPOL_HI } |
| SPI SSEL Polarity definition. More... | |
Functions | |
| STATIC INLINE void | IP_SPI_Enable (IP_SPI_002_T *pSPI) |
| Enable SPI peripheral. | |
| STATIC INLINE void | IP_SPI_Disable (IP_SPI_002_T *pSPI) |
| Disable SPI peripheral. | |
| STATIC INLINE void | IP_SPI_DeInit (IP_SPI_002_T *pSPI) |
| Deinitialise the SPI. | |
| STATIC INLINE void | IP_SPI_EnableLoopBack (IP_SPI_002_T *pSPI) |
| Enable loopback mode. | |
| STATIC INLINE void | IP_SPI_DisableLoopBack (IP_SPI_002_T *pSPI) |
| Disable loopback mode. | |
| STATIC INLINE uint32_t | IP_SPI_GetStatus (IP_SPI_002_T *pSPI) |
| Get the current status of SPI controller. | |
| STATIC INLINE void | IP_SPI_ForceEOT (IP_SPI_002_T *pSPI) |
| Force to end of transfer. | |
| STATIC INLINE void | IP_SPI_ClearStatus (IP_SPI_002_T *pSPI, uint32_t Flag) |
| Clear SPI status. | |
| STATIC INLINE void | IP_SPI_IntEnable (IP_SPI_002_T *pSPI, uint32_t IntEnMsk) |
| Enable the interrupt(s) for the SPI. | |
| STATIC INLINE void | IP_SPI_IntDisable (IP_SPI_002_T *pSPI, uint32_t IntDisMsk) |
| Disable the interrupt(s) for the SPI. | |
| STATIC INLINE uint32_t | IP_SPI_GetIntStatus (IP_SPI_002_T *pSPI) |
| Get the masked interrupt status. | |
| STATIC INLINE void | IP_SPI_SendFrame (IP_SPI_002_T *pSPI, uint16_t data) |
| Send SPI 16-bit data. | |
| STATIC INLINE void | IP_SPI_SetControlInfo (IP_SPI_002_T *pSPI, uint8_t Flen, uint32_t Flag) |
| Set control information including SSEL, EOT, EOF RXIGNORE and FLEN. | |
| STATIC INLINE void | IP_SPI_SendFrameAndControl (IP_SPI_002_T *pSPI, uint16_t TxData, uint8_t Flen, uint32_t Flag) |
| Send SPI 16-bit data and control information simutaneously. | |
| STATIC INLINE uint16_t | IP_SPI_ReceiveFrame (IP_SPI_002_T *pSPI) |
| Get received SPI data. | |
| void | IP_SPI_Init (IP_SPI_002_T *pSPI, IP_SPI_CONFIG_T *pConfig) |
| Initialise the SPI. | |
| void | IP_SPI_DelayConfig (IP_SPI_002_T *pSPI, IP_SPI_DELAY_CONFIG_T *pConfig) |
| Configure the SPI Delay parameters. | |
| #define SPI_CFG_BITMASK ((uint32_t) 0x1BD) |
| #define SPI_CFG_CPHA_FIRST ((uint32_t) (0)) /*Capture data on the first edge, Change data on the following edge*/ |
| #define SPI_CFG_CPHA_SECOND ((uint32_t) (1 << 4)) /*Change data on the first edge, Capture data on the following edge*/ |
| #define SPI_CFG_CPOL_HI ((uint32_t) (1 << 5)) /* The rest state of the clock (between frames) is high.*/ |
| #define SPI_CFG_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/ |
| #define SPI_CFG_LBM_EN ((uint32_t) (1 << 7)) |
| #define SPI_CFG_LSB_FIRST_EN ((uint32_t) (1 << 3))/*Data will be transmitted and received in reverse order (LSB first).*/ |
| #define SPI_CFG_MASTER_EN ((uint32_t) (1 << 2)) |
| #define SPI_CFG_MSB_FIRST_EN ((uint32_t) 0) /*Data will be transmitted and received in standard order (MSB first).*/ |
| #define SPI_CFG_SLAVE_EN ((uint32_t) 0) |
| #define SPI_CFG_SPOL_HI ((uint32_t) (1 << 8)) /* SSEL is active High */ |
| #define SPI_CFG_SPOL_LO ((uint32_t) (0)) /* SSEL is active Low */ |
| #define SPI_DIV_VAL | ( | n | ) | ((uint32_t) ((n) & 0xFFFF)) /* SPI_CLK = PCLK/(DIV_VAL+1)*/ |
| #define SPI_DLY_BITMASK ((uint32_t) 0xFFFF) |
| #define SPI_DLY_FRAME_DELAY | ( | n | ) | ((uint32_t) (((n) & 0x0F) << 8)) /* Time Unit: SPI clock time */ |
| #define SPI_DLY_POST_DELAY | ( | n | ) | ((uint32_t) (((n) & 0x0F) << 4)) /* Time Unit: SPI clock time */ |
| #define SPI_DLY_PRE_DELAY | ( | n | ) | ((uint32_t) ((n) & 0x0F)) /* Time Unit: SPI clock time */ |
| #define SPI_DLY_TRANSFER_DELAY | ( | n | ) | ((uint32_t) (((n) & 0x0F) << 12)) /* Time Unit: SPI clock time */ |
| #define SPI_INTENCLR_BITMASK ((uint32_t) 0x3F) |
| #define SPI_INTENCLR_RXDYEN ((uint32_t) (1 << 0)) |
| #define SPI_INTENCLR_RXOVEN ((uint32_t) (1 << 2)) |
| #define SPI_INTENCLR_SSAEN ((uint32_t) (1 << 2)) |
| #define SPI_INTENCLR_SSDEN ((uint32_t) (1 << 2)) |
| #define SPI_INTENCLR_TXDYEN ((uint32_t) (1 << 1)) |
| #define SPI_INTENCLR_TXUREN ((uint32_t) (1 << 3)) |
| #define SPI_INTENSET_BITMASK ((uint32_t) 0x3F) |
| #define SPI_INTENSET_RXDYEN ((uint32_t) (1 << 0)) |
| #define SPI_INTENSET_RXOVEN ((uint32_t) (1 << 2)) |
| #define SPI_INTENSET_SSAEN ((uint32_t) (1 << 2)) |
| #define SPI_INTENSET_SSDEN ((uint32_t) (1 << 2)) |
| #define SPI_INTENSET_TXDYEN ((uint32_t) (1 << 1)) |
| #define SPI_INTENSET_TXUREN ((uint32_t) (1 << 3)) |
| #define SPI_INTSTAT_BITMASK ((uint32_t) 0x3F) |
| #define SPI_INTSTAT_RXRDY ((uint32_t) (1 << 0)) /* Data is ready for read */ |
| #define SPI_INTSTAT_SSA ((uint32_t) (1 << 4)) /* There is SSEL transition from deasserted to asserted */ |
| #define SPI_INTSTAT_SSD ((uint32_t) (1 << 5)) /* There is SSEL transition from asserted to deasserted */ |
| #define SPI_INTSTAT_TXUR ((uint32_t) (1 << 3)) /* There is no data to be sent in the next input clock */ |
| #define SPI_RXDAT_BITMASK ((uint32_t) 0x11FFFF) |
| #define SPI_RXDAT_DATA | ( | n | ) | ((uint32_t) ((n) & 0xFFFF)) |
| #define SPI_RXDAT_RXSSELN_ACTIVE ((uint32_t) 0) /* SSEL is in active state */ |
| #define SPI_RXDAT_RXSSELN_INACTIVE ((uint32_t) (1 << 16)) /* SSEL is in inactive state */ |
| #define SPI_RXDAT_SOT ((uint32_t) (1 << 20)) /* This is the first frame received after SSEL is asserted */ |
| #define SPI_STAT_BITMASK ((uint32_t) 0x1FF) |
| #define SPI_STAT_EOT ((uint32_t) (1 << 7)) /* The current frame is the last frame of the current transfer. */ |
| #define SPI_STAT_LE ((uint32_t) (1 << 8)) /* SPI master function is fully idle. */ |
| #define SPI_STAT_RXRDY ((uint32_t) (1 << 0)) /* Data is ready for read */ |
| #define SPI_STAT_SSA ((uint32_t) (1 << 4)) /* There is SSEL transition from deasserted to asserted */ |
| #define SPI_STAT_SSD ((uint32_t) (1 << 5)) /* There is SSEL transition from asserted to deasserted */ |
| #define SPI_STAT_STALLED ((uint32_t) (1 << 6)) /* SPI is currently in a stall condition. */ |
| #define SPI_STAT_TXUR ((uint32_t) (1 << 3)) /* There is no data to be sent in the next input clock */ |
| #define SPI_TXCTL_BITMASK ((uint32_t) 0xF71FF00) |
| #define SPI_TXCTL_EOF ((uint32_t) (1 << 21)) /* This is the last part of the current frame */ |
| #define SPI_TXCTL_EOT ((uint32_t) (1 << 20)) /* This is the last frame of the current transfer */ |
| #define SPI_TXCTL_FLEN | ( | n | ) | ((uint32_t) (((n) & 0x0F) << 24)) /* Frame Length -1 */ |
| #define SPI_TXCTL_RXIGNORE ((uint32_t) (1 << 22)) /* Received data is ignored */ |
| #define SPI_TXDAT_DATA | ( | n | ) | ((uint32_t) ((n) & 0xFFFF)) |
| #define SPI_TXDATCTL_BITMASK ((uint32_t) 0xF71FFFF) |
| #define SPI_TXDATCTL_DATA | ( | n | ) | ((uint32_t) ((n) & 0xFFFF)) |
| #define SPI_TXDATCTL_EOF ((uint32_t) (1 << 21)) /* This is the last part of the current frame */ |
| #define SPI_TXDATCTL_EOT ((uint32_t) (1 << 20)) /* This is the last frame of the current transfer */ |
| #define SPI_TXDATCTL_FLEN | ( | n | ) | ((uint32_t) (((n) & 0x0F) << 24)) /* Frame Length -1 */ |
| #define SPI_TXDATCTL_RXIGNORE ((uint32_t) (1 << 22)) /* Received data is ignored */ |
| enum IP_SPI_CLOCK_MODE_T |
SPI Clock Mode.
| enum IP_SPI_DATA_ORDER_T |
| enum IP_SPI_MODE_T |
| enum IP_SPI_SSEL_POL_T |
| STATIC INLINE void IP_SPI_ClearStatus | ( | IP_SPI_002_T * | pSPI, |
| uint32_t | Flag | ||
| ) |
| STATIC INLINE void IP_SPI_DeInit | ( | IP_SPI_002_T * | pSPI | ) |
| void IP_SPI_DelayConfig | ( | IP_SPI_002_T * | pSPI, |
| IP_SPI_DELAY_CONFIG_T * | pConfig | ||
| ) |
| STATIC INLINE void IP_SPI_Disable | ( | IP_SPI_002_T * | pSPI | ) |
| STATIC INLINE void IP_SPI_DisableLoopBack | ( | IP_SPI_002_T * | pSPI | ) |
| STATIC INLINE void IP_SPI_Enable | ( | IP_SPI_002_T * | pSPI | ) |
| STATIC INLINE void IP_SPI_EnableLoopBack | ( | IP_SPI_002_T * | pSPI | ) |
| STATIC INLINE void IP_SPI_ForceEOT | ( | IP_SPI_002_T * | pSPI | ) |
| STATIC INLINE uint32_t IP_SPI_GetIntStatus | ( | IP_SPI_002_T * | pSPI | ) |
| STATIC INLINE uint32_t IP_SPI_GetStatus | ( | IP_SPI_002_T * | pSPI | ) |
| void IP_SPI_Init | ( | IP_SPI_002_T * | pSPI, |
| IP_SPI_CONFIG_T * | pConfig | ||
| ) |
| STATIC INLINE void IP_SPI_IntDisable | ( | IP_SPI_002_T * | pSPI, |
| uint32_t | IntDisMsk | ||
| ) |
| STATIC INLINE void IP_SPI_IntEnable | ( | IP_SPI_002_T * | pSPI, |
| uint32_t | IntEnMsk | ||
| ) |
| STATIC INLINE uint16_t IP_SPI_ReceiveFrame | ( | IP_SPI_002_T * | pSPI | ) |
| STATIC INLINE void IP_SPI_SendFrame | ( | IP_SPI_002_T * | pSPI, |
| uint16_t | data | ||
| ) |
| STATIC INLINE void IP_SPI_SendFrameAndControl | ( | IP_SPI_002_T * | pSPI, |
| uint16_t | TxData, | ||
| uint8_t | Flen, | ||
| uint32_t | Flag | ||
| ) |
| STATIC INLINE void IP_SPI_SetControlInfo | ( | IP_SPI_002_T * | pSPI, |
| uint8_t | Flen, | ||
| uint32_t | Flag | ||
| ) |
Set control information including SSEL, EOT, EOF RXIGNORE and FLEN.
| pSPI | : The base of SPI peripheral on the chip |
| Flen | : Data size (1-16) |
| Flag | : Flag control (Or-ed values of SPI_TXCTL_*) |
1.8.2 
