iocon_13xx.h

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/*
 * @brief IOCON registers and control functions
 *
 * @note
 * Copyright(C) NXP Semiconductors, 2012
 * All rights reserved.
 *
 * @par
 * Software that is described herein is for illustrative purposes only
 * which provides customers with programming information regarding the
 * LPC products.  This software is supplied "AS IS" without any warranties of
 * any kind, and NXP Semiconductors and its licensor disclaim any and
 * all warranties, express or implied, including all implied warranties of
 * merchantability, fitness for a particular purpose and non-infringement of
 * intellectual property rights.  NXP Semiconductors assumes no responsibility
 * or liability for the use of the software, conveys no license or rights under any
 * patent, copyright, mask work right, or any other intellectual property rights in
 * or to any products. NXP Semiconductors reserves the right to make changes
 * in the software without notification. NXP Semiconductors also makes no
 * representation or warranty that such application will be suitable for the
 * specified use without further testing or modification.
 *
 * @par
 * Permission to use, copy, modify, and distribute this software and its
 * documentation is hereby granted, under NXP Semiconductors' and its
 * licensor's relevant copyrights in the software, without fee, provided that it
 * is used in conjunction with NXP Semiconductors microcontrollers.  This
 * copyright, permission, and disclaimer notice must appear in all copies of
 * this code.
 */

#ifndef __IOCON_13XX_H_
#define __IOCON_13XX_H_

#ifdef __cplusplus
extern "C" {
#endif

#if defined(CHIP_LPC1347)
typedef struct {      
 __IO uint32_t  PIO0[24];
 __IO uint32_t  PIO1[32];
} LPC_IOCON_T;

#else

typedef enum CHIP_IOCON_PIO {
 IOCON_PIO0_0 = (0x00C >> 2),
 IOCON_PIO0_1 = (0x010 >> 2),
 IOCON_PIO0_2 = (0x01C >> 2),
 IOCON_PIO0_3 = (0x02C >> 2),
 IOCON_PIO0_4 = (0x030 >> 2),
 IOCON_PIO0_5 = (0x034 >> 2),
 IOCON_PIO0_6 = (0x04C >> 2),
 IOCON_PIO0_7 = (0x050 >> 2),
 IOCON_PIO0_8 = (0x060 >> 2),
 IOCON_PIO0_9 = (0x064 >> 2),
 IOCON_PIO0_11 = (0x074 >> 2),

 IOCON_PIO1_0 = (0x078 >> 2),
 IOCON_PIO1_1 = (0x07C >> 2),
 IOCON_PIO1_2 = (0x080 >> 2),
 IOCON_PIO1_3 = (0x090 >> 2),
 IOCON_PIO1_4 = (0x094 >> 2),
 IOCON_PIO1_5 = (0x0A0 >> 2),
 IOCON_PIO1_6 = (0x0A4 >> 2),
 IOCON_PIO1_7 = (0x0A8 >> 2),
 IOCON_PIO1_8 = (0x014 >> 2),
 IOCON_PIO1_9 = (0x038 >> 2),
 IOCON_PIO1_10 = (0x06C >> 2),
 IOCON_PIO1_11 = (0x098 >> 2),

 IOCON_PIO2_0 = (0x008 >> 2),
 IOCON_PIO2_1 = (0x028 >> 2),
 IOCON_PIO2_2 = (0x05C >> 2),
 IOCON_PIO2_3 = (0x08C >> 2),
 IOCON_PIO2_4 = (0x040 >> 2),
 IOCON_PIO2_5 = (0x044 >> 2),
 IOCON_PIO2_6 = (0x000 >> 2),
 IOCON_PIO2_7 = (0x020 >> 2),
 IOCON_PIO2_8 = (0x024 >> 2),
 IOCON_PIO2_9 = (0x054 >> 2),
 IOCON_PIO2_10 = (0x058 >> 2),
 IOCON_PIO2_11 = (0x070 >> 2),

 IOCON_PIO3_0 = (0x084 >> 2),
 IOCON_PIO3_1 = (0x088 >> 2),
 IOCON_PIO3_2 = (0x09C >> 2),
 IOCON_PIO3_3 = (0x0AC >> 2),
 IOCON_PIO3_4 = (0x03C >> 2),
 IOCON_PIO3_5 = (0x048 >> 2),
} CHIP_IOCON_PIO_T;

typedef enum CHIP_IOCON_PIN_LOC {
 IOCON_SCKLOC_PIO0_10        = (0xB0),  
 IOCON_SCKLOC_PIO2_11        = (0xB0 | 1), 
 IOCON_SCKLOC_PIO0_6         = (0xB0 | 2), 
 IOCON_DSRLOC_PIO2_1         = (0xB4),  
 IOCON_DSRLOC_PIO3_1         = (0xB4 | 1), 
 IOCON_DCDLOC_PIO2_2         = (0xB8),  
 IOCON_DCDLOC_PIO3_2         = (0xB8 | 1), 
 IOCON_RILOC_PIO2_3          = (0xBC),  
 IOCON_RILOC_PIO3_3          = (0xBC | 1), 
} CHIP_IOCON_PIN_LOC_T;

typedef struct {      
 __IO uint32_t  REG[48];
} LPC_IOCON_T;
#endif

#define IOCON_FUNC0             0x0    
#define IOCON_FUNC1             0x1    
#define IOCON_FUNC2             0x2    
#define IOCON_FUNC3             0x3    
#define IOCON_FUNC4             0x4    
#define IOCON_FUNC5             0x5    
#define IOCON_FUNC6             0x6    
#define IOCON_FUNC7             0x7    
#define IOCON_MODE_INACT        (0x0 << 3)  
#define IOCON_MODE_PULLDOWN     (0x1 << 3)  
#define IOCON_MODE_PULLUP       (0x2 << 3)  
#define IOCON_MODE_REPEATER     (0x3 << 3)  
#define IOCON_HYS_EN            (0x1 << 5)  
#define IOCON_INV_EN            (0x1 << 6)  
#define IOCON_ADMODE_EN         (0x0 << 7)  
#define IOCON_DIGMODE_EN        (0x1 << 7)  
#define IOCON_SFI2C_EN          (0x0 << 8)  
#define IOCON_STDI2C_EN         (0x1 << 8)  
#define IOCON_FASTI2C_EN        (0x2 << 8)  
#define IOCON_FILT_DIS          (0x1 << 8)  
#define IOCON_OPENDRAIN_EN      (0x1 << 10)  
#define MD_PUP     (0x0 << 3)  
#define MD_BUK     (0x1 << 3)  
#define MD_PLN     (0x2 << 3)  
#define MD_PDN     (0x3 << 3)  
#define MD_HYS     (0x1 << 5)  
#define MD_INV     (0x1 << 6)  
#define MD_ADMODE    (0x0 << 7)  
#define MD_DIGMODE    (0x1 << 7)  
#define MD_DISFIL    (0x0 << 8)  
#define MD_ENFIL    (0x1 << 8)  
#define MD_SFI2C    (0x0 << 8)  
#define MD_STDI2C    (0x1 << 8)  
#define MD_FASTI2C    (0x2 << 8)  
#define MD_OPENDRAIN   (0x1 << 10)  
#define FUNC0 0x0
#define FUNC1 0x1
#define FUNC2 0x2
#define FUNC3 0x3
#define FUNC4 0x4
#define FUNC5 0x5
#define FUNC6 0x6
#define FUNC7 0x7

#if defined(CHIP_LPC1347)

void Chip_IOCON_PinMuxSet(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint32_t modefunc);

STATIC INLINE void Chip_IOCON_PinMux(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint16_t mode, uint8_t func)
{
 Chip_IOCON_PinMuxSet(pIOCON, port, pin, (uint32_t) (mode | func));
}

#else

STATIC INLINE void Chip_IOCON_PinMuxSet(LPC_IOCON_T *pIOCON, CHIP_IOCON_PIO_T pin, uint32_t modefunc)
{
 pIOCON->REG[pin] = modefunc;
}

STATIC INLINE void Chip_IOCON_PinMux(LPC_IOCON_T *pIOCON, CHIP_IOCON_PIO_T pin, uint16_t mode, uint8_t func)
{
 Chip_IOCON_PinMuxSet(pIOCON, pin, (uint32_t) (mode | func));
}

STATIC INLINE void Chip_IOCON_PinLocSel(LPC_IOCON_T *pIOCON, CHIP_IOCON_PIN_LOC_T sel)
{
 pIOCON->REG[sel >> 2] = sel & 0x03;
}

#endif /* defined(CHIP_LPC1347) */

#ifdef __cplusplus
}
#endif

#endif /* __IOCON_13XX_H_ */