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cpu_c.c
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1 /*
2 *********************************************************************************************************
3 * uC/CPU
4 * CPU CONFIGURATION & PORT LAYER
5 *
6 * (c) Copyright 2004-2011; Micrium, Inc.; Weston, FL
7 *
8 * All rights reserved. Protected by international copyright laws.
9 *
10 * uC/CPU is provided in source form to registered licensees ONLY. It is
11 * illegal to distribute this source code to any third party unless you receive
12 * written permission by an authorized Micrium representative. Knowledge of
13 * the source code may NOT be used to develop a similar product.
14 *
15 * Please help us continue to provide the Embedded community with the finest
16 * software available. Your honesty is greatly appreciated.
17 *
18 * You can contact us at www.micrium.com.
19 *********************************************************************************************************
20 */
21 
22 /*
23 *********************************************************************************************************
24 *
25 * CPU PORT FILE
26 *
27 * ARM-Cortex-M3
28 * Code Red LPCXpresso Tool chain
29 * GNU GCC Tool chain
30 *
31 * Filename : cpu_c.c
32 * Version : V1.28.00.00
33 * Programmer(s) : JJL
34 * BAN
35 * FT
36 *********************************************************************************************************
37 */
38 
39 
40 /*
41 *********************************************************************************************************
42 * INCLUDE FILES
43 *********************************************************************************************************
44 */
45 
46 #include <cpu.h>
47 #include <cpu_core.h>
48 
49 #include <lib_def.h>
50 
51 
52 /*$PAGE*/
53 /*
54 *********************************************************************************************************
55 * LOCAL DEFINES
56 *********************************************************************************************************
57 */
58 
59 #define CPU_INT_SRC_POS_MAX ((((CPU_REG_NVIC_NVIC + 1) & 0x1F) * 32) + 16)
60 
61 #define CPU_BIT_BAND_SRAM_REG_LO 0x20000000
62 #define CPU_BIT_BAND_SRAM_REG_HI 0x200FFFFF
63 #define CPU_BIT_BAND_SRAM_BASE 0x22000000
64 
65 
66 #define CPU_BIT_BAND_PERIPH_REG_LO 0x40000000
67 #define CPU_BIT_BAND_PERIPH_REG_HI 0x400FFFFF
68 #define CPU_BIT_BAND_PERIPH_BASE 0x42000000
69 
70 
71 /*
72 *********************************************************************************************************
73 * LOCAL CONSTANTS
74 *********************************************************************************************************
75 */
76 
77 
78 /*
79 *********************************************************************************************************
80 * LOCAL DATA TYPES
81 *********************************************************************************************************
82 */
83 
84 
85 /*
86 *********************************************************************************************************
87 * LOCAL TABLES
88 *********************************************************************************************************
89 */
90 
91 
92 /*
93 *********************************************************************************************************
94 * LOCAL GLOBAL VARIABLES
95 *********************************************************************************************************
96 */
97 
98 
99 /*
100 *********************************************************************************************************
101 * LOCAL FUNCTION PROTOTYPES
102 *********************************************************************************************************
103 */
104 
105 
106 /*
107 *********************************************************************************************************
108 * LOCAL CONFIGURATION ERRORS
109 *********************************************************************************************************
110 */
111 
112 
113 /*$PAGE*/
114 /*
115 *********************************************************************************************************
116 * CPU_BitBandClr()
117 *
118 * Description : Clear bit in bit-band region.
119 *
120 * Argument(s) : addr Byte address in memory space.
121 *
122 * bit_nbr Bit number in byte.
123 *
124 * Return(s) : none.
125 *
126 * Caller(s) : Application.
127 *
128 * Note(s) : none.
129 *********************************************************************************************************
130 */
131 
132 void CPU_BitBandClr (CPU_ADDR addr,
133  CPU_INT08U bit_nbr)
134 {
135  CPU_ADDR bit_word_off;
136  CPU_ADDR bit_word_addr;
137 
138 
139  if ((addr >= CPU_BIT_BAND_SRAM_REG_LO) &&
140  (addr <= CPU_BIT_BAND_SRAM_REG_HI)) {
141  bit_word_off = ((addr - CPU_BIT_BAND_SRAM_REG_LO ) * 32) + (bit_nbr * 4);
142  bit_word_addr = CPU_BIT_BAND_SRAM_BASE + bit_word_off;
143 
144  *(volatile CPU_INT32U *)(bit_word_addr) = 0;
145 
146  } else if ((addr >= CPU_BIT_BAND_PERIPH_REG_LO) &&
147  (addr <= CPU_BIT_BAND_PERIPH_REG_HI)) {
148  bit_word_off = ((addr - CPU_BIT_BAND_PERIPH_REG_LO) * 32) + (bit_nbr * 4);
149  bit_word_addr = CPU_BIT_BAND_PERIPH_BASE + bit_word_off;
150 
151  *(volatile CPU_INT32U *)(bit_word_addr) = 0;
152  }
153 }
154 
155 
156 /*$PAGE*/
157 /*
158 *********************************************************************************************************
159 * CPU_BitBandSet()
160 *
161 * Description : Set bit in bit-band region.
162 *
163 * Argument(s) : addr Byte address in memory space.
164 *
165 * bit_nbr Bit number in byte.
166 *
167 * Return(s) : none.
168 *
169 * Caller(s) : Application.
170 *
171 * Note(s) : none.
172 *********************************************************************************************************
173 */
174 
175 void CPU_BitBandSet (CPU_ADDR addr,
176  CPU_INT08U bit_nbr)
177 {
178  CPU_ADDR bit_word_off;
179  CPU_ADDR bit_word_addr;
180 
181 
182  if ((addr >= CPU_BIT_BAND_SRAM_REG_LO) &&
183  (addr <= CPU_BIT_BAND_SRAM_REG_HI)) {
184  bit_word_off = ((addr - CPU_BIT_BAND_SRAM_REG_LO ) * 32) + (bit_nbr * 4);
185  bit_word_addr = CPU_BIT_BAND_SRAM_BASE + bit_word_off;
186 
187  *(volatile CPU_INT32U *)(bit_word_addr) = 1;
188 
189  } else if ((addr >= CPU_BIT_BAND_PERIPH_REG_LO) &&
190  (addr <= CPU_BIT_BAND_PERIPH_REG_HI)) {
191  bit_word_off = ((addr - CPU_BIT_BAND_PERIPH_REG_LO) * 32) + (bit_nbr * 4);
192  bit_word_addr = CPU_BIT_BAND_PERIPH_BASE + bit_word_off;
193 
194  *(volatile CPU_INT32U *)(bit_word_addr) = 1;
195  }
196 }
197 
198 
199 /*$PAGE*/
200 /*
201 *********************************************************************************************************
202 * CPU_IntSrcDis()
203 *
204 * Description : Disable an interrupt source.
205 *
206 * Argument(s) : pos Position of interrupt vector in interrupt table :
207 *
208 * 0 Invalid (see Note #1a).
209 * 1 Invalid (see Note #1b).
210 * 2 Non-maskable interrupt.
211 * 3 Hard Fault.
212 * 4 Memory Management.
213 * 5 Bus Fault.
214 * 6 Usage Fault.
215 * 7-10 Reserved.
216 * 11 SVCall
217 * 12 Debug monitor.
218 * 13 Reserved
219 * 14 PendSV.
220 * 15 SysTick.
221 * 16+ External Interrupt.
222 *
223 * Return(s) : none.
224 *
225 * Caller(s) : Application.
226 *
227 * Note(s) : (1) Several table positions do not contain interrupt sources :
228 *
229 * (a) Position 0 contains the stack pointer.
230 * (b) Positions 7-10, 13 are reserved.
231 *
232 * (2) Several interrupts cannot be disabled/enabled :
233 *
234 * (a) Reset.
235 * (b) NMI.
236 * (c) Hard fault.
237 * (d) SVCall.
238 * (e) Debug monitor.
239 * (f) PendSV.
240 *
241 * (3) The maximum Cortex-M3 table position is 256. A particular Cortex-M3 may have fewer
242 * than 240 external exceptions and, consequently, fewer than 256 table positions.
243 * This function assumes that the specified table position is valid if the interrupt
244 * controller type register's INTLINESNUM field is large enough so that the position
245 * COULD be valid.
246 *********************************************************************************************************
247 */
248 /*$PAGE*/
249 void CPU_IntSrcDis (CPU_INT08U pos)
250 {
251  CPU_INT08U group;
252  CPU_INT08U pos_max;
253  CPU_INT08U nbr;
254  CPU_SR_ALLOC();
255 
256 
257  switch (pos) {
258  case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
259  case CPU_INT_RSVD_07:
260  case CPU_INT_RSVD_08:
261  case CPU_INT_RSVD_09:
262  case CPU_INT_RSVD_10:
263  case CPU_INT_RSVD_13:
264  break;
265 
266 
267  /* ----------------- SYSTEM EXCEPTIONS ---------------- */
268  case CPU_INT_RESET: /* Reset (see Note #2). */
269  case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
270  case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
271  case CPU_INT_SVCALL: /* SVCall (see Note #2). */
272  case CPU_INT_DBGMON: /* Debug monitor (see Note #2). */
273  case CPU_INT_PENDSV: /* PendSV (see Note #2). */
274  break;
275 
276  case CPU_INT_MEM: /* Memory management. */
277  CPU_CRITICAL_ENTER();
278  CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_MEMFAULTENA;
279  CPU_CRITICAL_EXIT();
280  break;
281 
282  case CPU_INT_BUSFAULT: /* Bus fault. */
283  CPU_CRITICAL_ENTER();
284  CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_BUSFAULTENA;
285  CPU_CRITICAL_EXIT();
286  break;
287 
288  case CPU_INT_USAGEFAULT: /* Usage fault. */
289  CPU_CRITICAL_ENTER();
290  CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_USGFAULTENA;
291  CPU_CRITICAL_EXIT();
292  break;
293 
294  case CPU_INT_SYSTICK: /* SysTick. */
295  CPU_CRITICAL_ENTER();
296  CPU_REG_NVIC_ST_CTRL &= ~CPU_REG_NVIC_ST_CTRL_ENABLE;
297  CPU_CRITICAL_EXIT();
298  break;
299 
300 
301  /* ---------------- EXTERNAL INTERRUPT ---------------- */
302  default:
303  pos_max = CPU_INT_SRC_POS_MAX;
304  if (pos < pos_max) { /* See Note #3. */
305  group = (pos - 16) / 32;
306  nbr = (pos - 16) % 32;
307 
308  CPU_CRITICAL_ENTER();
309  CPU_REG_NVIC_CLREN(group) = DEF_BIT(nbr);
310  CPU_CRITICAL_EXIT();
311  }
312  break;
313  }
314 }
315 
316 
317 /*$PAGE*/
318 /*
319 *********************************************************************************************************
320 * CPU_IntSrcEn()
321 *
322 * Description : Enable an interrupt source.
323 *
324 * Argument(s) : pos Position of interrupt vector in interrupt table (see 'CPU_IntSrcDis()').
325 *
326 * Return(s) : none.
327 *
328 * Caller(s) : Application.
329 *
330 * Note(s) : (1) See 'CPU_IntSrcDis() Note #1'.
331 *
332 * (2) See 'CPU_IntSrcDis() Note #2'.
333 *
334 * (3) See 'CPU_IntSrcDis() Note #3'.
335 *********************************************************************************************************
336 */
337 
338 void CPU_IntSrcEn (CPU_INT08U pos)
339 {
340  CPU_INT08U group;
341  CPU_INT08U nbr;
342  CPU_INT08U pos_max;
343  CPU_SR_ALLOC();
344 
345 
346  switch (pos) {
347  case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
348  case CPU_INT_RSVD_07:
349  case CPU_INT_RSVD_08:
350  case CPU_INT_RSVD_09:
351  case CPU_INT_RSVD_10:
352  case CPU_INT_RSVD_13:
353  break;
354 
355 
356  /* ----------------- SYSTEM EXCEPTIONS ---------------- */
357  case CPU_INT_RESET: /* Reset (see Note #2). */
358  case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
359  case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
360  case CPU_INT_SVCALL: /* SVCall (see Note #2). */
361  case CPU_INT_DBGMON: /* Debug monitor (see Note #2). */
362  case CPU_INT_PENDSV: /* PendSV (see Note #2). */
363  break;
364 
365  case CPU_INT_MEM: /* Memory management. */
366  CPU_CRITICAL_ENTER();
367  CPU_REG_NVIC_SHCSR |= CPU_REG_NVIC_SHCSR_MEMFAULTENA;
368  CPU_CRITICAL_EXIT();
369  break;
370 
371  case CPU_INT_BUSFAULT: /* Bus fault. */
372  CPU_CRITICAL_ENTER();
373  CPU_REG_NVIC_SHCSR |= CPU_REG_NVIC_SHCSR_BUSFAULTENA;
374  CPU_CRITICAL_EXIT();
375  break;
376 
377  case CPU_INT_USAGEFAULT: /* Usage fault. */
378  CPU_CRITICAL_ENTER();
379  CPU_REG_NVIC_SHCSR |= CPU_REG_NVIC_SHCSR_USGFAULTENA;
380  CPU_CRITICAL_EXIT();
381  break;
382 
383  case CPU_INT_SYSTICK: /* SysTick. */
384  CPU_CRITICAL_ENTER();
385  CPU_REG_NVIC_ST_CTRL |= CPU_REG_NVIC_ST_CTRL_ENABLE;
386  CPU_CRITICAL_EXIT();
387  break;
388 
389 
390  /* ---------------- EXTERNAL INTERRUPT ---------------- */
391  default:
392  pos_max = CPU_INT_SRC_POS_MAX;
393  if (pos < pos_max) { /* See Note #3. */
394  group = (pos - 16) / 32;
395  nbr = (pos - 16) % 32;
396 
397  CPU_CRITICAL_ENTER();
398  CPU_REG_NVIC_SETEN(group) = DEF_BIT(nbr);
399  CPU_CRITICAL_EXIT();
400  }
401  break;
402  }
403 }
404 
405 /*$PAGE*/
406 /*
407 *********************************************************************************************************
408 * CPU_IntSrcPendClr()
409 *
410 * Description : Clear a pending interrupt.
411 *
412 * Argument(s) : pos Position of interrupt vector in interrupt table (see 'CPU_IntSrcDis()').
413 *
414 * Return(s) : none.
415 *
416 * Caller(s) : Application.
417 *
418 * Note(s) : (1) See 'CPU_IntSrcDis() Note #1'.
419 *
420 * (2) The pending status of several interrupts cannot be clear/set :
421 *
422 * (a) Reset.
423 * (b) NMI.
424 * (c) Hard fault.
425 * (d) Memory Managment.
426 * (e) Bus Fault.
427 * (f) Usage Fault.
428 * (g) SVCall.
429 * (h) Debug monitor.
430 * (i) PendSV.
431 * (j) Systick
432 *
433 * (3) See 'CPU_IntSrcDis() Note #3'.
434 *********************************************************************************************************
435 */
436 
437 void CPU_IntSrcPendClr (CPU_INT08U pos)
438 
439 {
440  CPU_INT08U group;
441  CPU_INT08U nbr;
442  CPU_INT08U pos_max;
443  CPU_SR_ALLOC();
444 
445 
446  switch (pos) {
447  case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
448  case CPU_INT_RSVD_07:
449  case CPU_INT_RSVD_08:
450  case CPU_INT_RSVD_09:
451  case CPU_INT_RSVD_10:
452  case CPU_INT_RSVD_13:
453  break;
454  /* ----------------- SYSTEM EXCEPTIONS ---------------- */
455  case CPU_INT_RESET: /* Reset (see Note #2). */
456  case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
457  case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
458  case CPU_INT_MEM: /* Memory management (see Note #2). */
459  case CPU_INT_SVCALL: /* SVCall (see Note #2). */
460  case CPU_INT_DBGMON: /* Debug monitor (see Note #2). */
461  case CPU_INT_PENDSV: /* PendSV (see Note #2). */
462  case CPU_INT_BUSFAULT: /* Bus fault. */
463  case CPU_INT_USAGEFAULT: /* Usage fault. */
464  case CPU_INT_SYSTICK: /* SysTick. */
465  break;
466  /* ---------------- EXTERNAL INTERRUPT ---------------- */
467  default:
468  pos_max = CPU_INT_SRC_POS_MAX;
469  if (pos < pos_max) { /* See Note #3. */
470  group = (pos - 16) / 32;
471  nbr = (pos - 16) % 32;
472 
473  CPU_CRITICAL_ENTER();
474  CPU_REG_NVIC_CLRPEND(group) = DEF_BIT(nbr);
475  CPU_CRITICAL_EXIT();
476  }
477  break;
478  }
479 }
480 
481 
482 /*$PAGE*/
483 /*
484 *********************************************************************************************************
485 * CPU_IntSrcPrioSet()
486 *
487 * Description : Set priority of an interrupt source.
488 *
489 * Argument(s) : pos Position of interrupt vector in interrupt table (see 'CPU_IntSrcDis()').
490 *
491 * prio Priority. Use a lower priority number for a higher priority.
492 *
493 * Return(s) : none.
494 *
495 * Caller(s) : Application.
496 *
497 * Note(s) : (1) See 'CPU_IntSrcDis() Note #1'.
498 *
499 * (2) Several interrupts priorities CANNOT be set :
500 *
501 * (a) Reset (always -3).
502 * (b) NMI (always -2).
503 * (c) Hard fault (always -1).
504 *
505 * (3) See 'CPU_IntSrcDis() Note #3'.
506 *********************************************************************************************************
507 */
508 
509 void CPU_IntSrcPrioSet (CPU_INT08U pos,
510  CPU_INT08U prio)
511 {
512  CPU_INT08U group;
513  CPU_INT08U nbr;
514  CPU_INT08U pos_max;
515  CPU_INT32U prio_32;
516  CPU_INT32U temp;
517  CPU_SR_ALLOC();
518 
519 
520  prio_32 = CPU_RevBits((CPU_INT08U)prio);
521  prio = (CPU_INT08U)(prio_32 >> (3 * DEF_OCTET_NBR_BITS));
522 
523  switch (pos) {
524  case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
525  case CPU_INT_RSVD_07:
526  case CPU_INT_RSVD_08:
527  case CPU_INT_RSVD_09:
528  case CPU_INT_RSVD_10:
529  case CPU_INT_RSVD_13:
530  break;
531 
532 
533  /* ----------------- SYSTEM EXCEPTIONS ---------------- */
534  case CPU_INT_RESET: /* Reset (see Note #2). */
535  case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
536  case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
537  break;
538 
539  case CPU_INT_MEM: /* Memory management. */
540  CPU_CRITICAL_ENTER();
541  temp = CPU_REG_NVIC_SHPRI1;
542  temp &= ~(DEF_OCTET_MASK << (0 * DEF_OCTET_NBR_BITS));
543  temp |= (prio << (0 * DEF_OCTET_NBR_BITS));
544  CPU_REG_NVIC_SHPRI1 = temp;
545  CPU_CRITICAL_EXIT();
546  break;
547 
548  case CPU_INT_BUSFAULT: /* Bus fault. */
549  CPU_CRITICAL_ENTER();
550  temp = CPU_REG_NVIC_SHPRI1;
551  temp &= ~(DEF_OCTET_MASK << (1 * DEF_OCTET_NBR_BITS));
552  temp |= (prio << (1 * DEF_OCTET_NBR_BITS));
553  CPU_REG_NVIC_SHPRI1 = temp;
554  CPU_CRITICAL_EXIT();
555  break;
556 
557  case CPU_INT_USAGEFAULT: /* Usage fault. */
558  CPU_CRITICAL_ENTER();
559  temp = CPU_REG_NVIC_SHPRI1;
560  temp &= ~(DEF_OCTET_MASK << (2 * DEF_OCTET_NBR_BITS));
561  temp |= (prio << (2 * DEF_OCTET_NBR_BITS));
562  CPU_REG_NVIC_SHPRI1 = temp;
563  CPU_CRITICAL_EXIT();
564  break;
565 
566  case CPU_INT_SVCALL: /* SVCall. */
567  CPU_CRITICAL_ENTER();
568  temp = CPU_REG_NVIC_SHPRI2;
569  temp &= ~((CPU_INT32U)DEF_OCTET_MASK << (3 * DEF_OCTET_NBR_BITS));
570  temp |= (prio << (3 * DEF_OCTET_NBR_BITS));
571  CPU_REG_NVIC_SHPRI2 = temp;
572  CPU_CRITICAL_EXIT();
573  break;
574 
575  case CPU_INT_DBGMON: /* Debug monitor. */
576  CPU_CRITICAL_ENTER();
577  temp = CPU_REG_NVIC_SHPRI3;
578  temp &= ~(DEF_OCTET_MASK << (0 * DEF_OCTET_NBR_BITS));
579  temp |= (prio << (0 * DEF_OCTET_NBR_BITS));
580  CPU_REG_NVIC_SHPRI3 = temp;
581  CPU_CRITICAL_EXIT();
582  break;
583 
584  case CPU_INT_PENDSV: /* PendSV. */
585  CPU_CRITICAL_ENTER();
586  temp = CPU_REG_NVIC_SHPRI3;
587  temp &= ~(DEF_OCTET_MASK << (2 * DEF_OCTET_NBR_BITS));
588  temp |= (prio << (2 * DEF_OCTET_NBR_BITS));
589  CPU_REG_NVIC_SHPRI3 = temp;
590  CPU_CRITICAL_EXIT();
591  break;
592 
593  case CPU_INT_SYSTICK: /* SysTick. */
594  CPU_CRITICAL_ENTER();
595  temp = CPU_REG_NVIC_SHPRI3;
596  temp &= ~((CPU_INT32U)DEF_OCTET_MASK << (3 * DEF_OCTET_NBR_BITS));
597  temp |= (prio << (3 * DEF_OCTET_NBR_BITS));
598  CPU_REG_NVIC_SHPRI3 = temp;
599  CPU_CRITICAL_EXIT();
600  break;
601 
602 
603  /* ---------------- EXTERNAL INTERRUPT ---------------- */
604  default:
605  pos_max = CPU_INT_SRC_POS_MAX;
606  if (pos < pos_max) { /* See Note #3. */
607  group = (pos - 16) / 4;
608  nbr = (pos - 16) % 4;
609 
610  CPU_CRITICAL_ENTER();
611  temp = CPU_REG_NVIC_PRIO(group);
612  temp &= ~(DEF_OCTET_MASK << (nbr * DEF_OCTET_NBR_BITS));
613  temp |= (prio << (nbr * DEF_OCTET_NBR_BITS));
614  CPU_REG_NVIC_PRIO(group) = temp;
615  CPU_CRITICAL_EXIT();
616  }
617  break;
618  }
619 }
620 
621 
622 /*$PAGE*/
623 /*
624 *********************************************************************************************************
625 * CPU_IntSrcPrioGet()
626 *
627 * Description : Get priority of an interrupt source.
628 *
629 * Argument(s) : pos Position of interrupt vector in interrupt table (see 'CPU_IntSrcDis()').
630 *
631 * Return(s) : Priority of interrupt source. If the interrupt source specified is invalid, then
632 * DEF_INT_16S_MIN_VAL is returned.
633 *
634 * Caller(s) : Application.
635 *
636 * Note(s) : (1) See 'CPU_IntSrcDis() Note #1'.
637 *
638 * (2) See 'CPU_IntSrcPrioSet() Note #2'.
639 *
640 * (3) See 'CPU_IntSrcDis() Note #3'.
641 *********************************************************************************************************
642 */
643 
644 CPU_INT16S CPU_IntSrcPrioGet (CPU_INT08U pos)
645 {
646  CPU_INT08U group;
647  CPU_INT08U nbr;
648  CPU_INT08U pos_max;
649  CPU_INT16S prio;
650  CPU_INT32U prio_32;
651  CPU_INT32U temp;
652  CPU_SR_ALLOC();
653 
654 
655  switch (pos) {
656  case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
657  case CPU_INT_RSVD_07:
658  case CPU_INT_RSVD_08:
659  case CPU_INT_RSVD_09:
660  case CPU_INT_RSVD_10:
661  case CPU_INT_RSVD_13:
662  prio = DEF_INT_16S_MIN_VAL;
663  break;
664 
665 
666  /* ----------------- SYSTEM EXCEPTIONS ---------------- */
667  case CPU_INT_RESET: /* Reset (see Note #2). */
668  prio = -3;
669  break;
670 
671  case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
672  prio = -2;
673  break;
674 
675  case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
676  prio = -1;
677  break;
678 
679 
680  case CPU_INT_MEM: /* Memory management. */
681  CPU_CRITICAL_ENTER();
682  temp = CPU_REG_NVIC_SHPRI1;
683  prio = (temp >> (0 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
684  CPU_CRITICAL_EXIT();
685  break;
686 
687 
688  case CPU_INT_BUSFAULT: /* Bus fault. */
689  CPU_CRITICAL_ENTER();
690  temp = CPU_REG_NVIC_SHPRI1;
691  prio = (temp >> (1 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
692  CPU_CRITICAL_EXIT();
693  break;
694 
695 
696  case CPU_INT_USAGEFAULT: /* Usage fault. */
697  CPU_CRITICAL_ENTER();
698  temp = CPU_REG_NVIC_SHPRI1;
699  prio = (temp >> (2 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
700  break;
701 
702  case CPU_INT_SVCALL: /* SVCall. */
703  CPU_CRITICAL_ENTER();
704  temp = CPU_REG_NVIC_SHPRI2;
705  prio = (temp >> (3 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
706  CPU_CRITICAL_EXIT();
707  break;
708 
709  case CPU_INT_DBGMON: /* Debug monitor. */
710  CPU_CRITICAL_ENTER();
711  temp = CPU_REG_NVIC_SHPRI3;
712  prio = (temp >> (0 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
713  CPU_CRITICAL_EXIT();
714  break;
715 
716  case CPU_INT_PENDSV: /* PendSV. */
717  CPU_CRITICAL_ENTER();
718  temp = CPU_REG_NVIC_SHPRI3;
719  prio = (temp >> (2 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
720  CPU_CRITICAL_EXIT();
721  break;
722 
723  case CPU_INT_SYSTICK: /* SysTick. */
724  CPU_CRITICAL_ENTER();
725  temp = CPU_REG_NVIC_SHPRI3;
726  prio = (temp >> (3 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
727  CPU_CRITICAL_EXIT();
728  break;
729 
730 
731  /* ---------------- EXTERNAL INTERRUPT ---------------- */
732  default:
733  pos_max = CPU_INT_SRC_POS_MAX;
734  if (pos < pos_max) { /* See Note #3. */
735  group = (pos - 16) / 4;
736  nbr = (pos - 16) % 4;
737 
738  CPU_CRITICAL_ENTER();
739  temp = CPU_REG_NVIC_PRIO(group);
740  CPU_CRITICAL_EXIT();
741 
742  prio = (temp >> (nbr * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
743  } else {
744  prio = DEF_INT_16S_MIN_VAL;
745  }
746  break;
747  }
748 
749  if (prio >= 0) {
750  prio_32 = CPU_RevBits((CPU_INT32U)prio);
751  prio = (CPU_INT16S)(prio_32 >> (3 * DEF_OCTET_NBR_BITS));
752  }
753 
754  return (prio);
755 }
756